JP5101991B2 - Analog switch and selector circuit using the same - Google Patents

Description

  The present invention relates to an analog switch.

  An analog switch is used for the purpose of blocking the propagation path of the analog signal or switching the propagation path. As a general analog switch, a transfer gate is often used. The transfer gate includes an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a P-channel MOSFET that are provided in parallel and are connected to both ends in common.

JP 58-13027 A Japanese Patent Laid-Open No. 58-13028 Japanese Patent Laid-Open No. 9-8625 JP 2006-157132 A

  Consider a case where an analog signal is propagated to a transfer gate. When the transfer gate is on, a high level (power supply voltage) is applied to the gate of the N-channel MOSFET and a low level (ground voltage or negative power supply voltage) is applied to the gate of the P-channel MOSFET, thereby fixing the voltage. . In this state, when an analog input signal that changes with time is input to the input terminal of the analog switch, the gate-source voltage of the MOSFET changes according to the change of the input signal.

  When the gate-source voltage changes, the on-resistance of the MOSFET fluctuates, so that the waveform of the analog signal appearing at the output terminal is distorted. Propagating a signal that requires low distortion, such as an analog audio signal or an analog video signal, to such an analog switch causes problems such as deterioration in sound quality and image quality.

  The present invention has been made in view of such problems, and an object thereof is to provide an analog switch with reduced distortion.

  An analog switch according to an aspect of the present invention includes an input terminal to which an analog signal is input, an output terminal for outputting the analog signal, and an N-channel first MOSFET (Metal Oxide) provided between the input terminal and the output terminal. Semiconductor Field Effect Transistor) and a first diode arranged between the gate of the first MOSFET and the first fixed voltage terminal in such a direction that the cathode is on the gate side.

  According to this aspect, the first diode has a high impedance between the first fixed voltage terminal and the gate of the first MOSFET. When an analog signal is applied to the input terminal in this state, the gate-source capacitance (or gate-drain capacitance) couples between the input terminal and the gate, and the gate voltage changes in phase with the input signal. As a result, fluctuations in the voltage between the gate and source of the first MOSFET are suppressed, and fluctuations in on-resistance are also suppressed, so that distortion of the analog signal can be reduced.

  In the ON state of the analog switch, a power supply voltage may be applied to the first fixed voltage terminal. That is, the first fixed voltage terminal may be a power supply terminal. If this analog switch is used, it is only necessary to supply a power supply voltage, and a negative bias voltage is not required, so that the circuit can be simplified.

  The analog switch according to an aspect may further include an N-channel second MOSFET connected in series with the first MOSFET between the input terminal and the output terminal, and having a gate connected in common with the gate of the first MOSFET.

The analog switch of an aspect may further include a first capacitor provided between the input terminal and the gate of the first MOSFET.
In this case, since the gate and the input terminal are coupled by the first capacitor in addition to the gate-source capacitance of the MOSFET (gate-drain capacitance), the followability of the gate voltage to the input signal can be improved. Further, distortion can be reduced.

The analog switch according to an aspect may further include a second capacitor provided between the output terminal and the gate of the first MOSFET.
In this case, since the gate and the input terminal are coupled by the second capacitor in addition to the gate-source capacitance of the MOSFET (gate-drain capacitance), the followability of the gate voltage to the input signal can be improved. Further, distortion can be reduced.

  The analog switch of a certain aspect may further include a third MOSFET that is provided between the first fixed voltage terminal and the anode of the first diode, and whose gate voltage is controlled according to ON / OFF of the analog switch.

  The analog switch of a certain aspect further includes a fourth MOSFET that is provided between the connection point of the first MOSFET and the second MOSFET and the cathode of the first diode, and whose gate voltage is controlled according to whether the analog switch is on or off. Good.

  The analog switch of a certain aspect may further include a fifth MOSFET that is provided between the connection point of the first MOSFET and the second MOSFET and the ground terminal and whose gate voltage is controlled according to the on / off of the analog switch.

The analog switch according to an aspect may further include a first resistor provided in series with the first diode between the gate of the first MOSFET and the first fixed voltage terminal.
By providing the resistor, the impedance between the gate and the first fixed voltage terminal can be adjusted, and the gain characteristic and phase characteristic of the analog switch can be adjusted.

  An analog switch according to an aspect includes a P-channel sixth MOSFET provided between an input terminal and an output terminal, and an anode disposed between the gate of the sixth MOSFET and the second fixed voltage terminal so that the anode is on the gate side. And a second diode.

  Another aspect of the present invention is also an analog switch. This analog switch has an input terminal for inputting an analog signal, an output terminal for outputting the analog signal, and a sixth MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided between the input terminal and the output terminal. And a second diode arranged between the gate of the sixth MOSFET and the second fixed voltage terminal so that the anode is on the gate side.

  According to this aspect, the first diode provides high impedance between the second fixed voltage terminal and the gate of the second MOSFET. When an analog signal is applied to the input terminal in this state, the gate-source capacitance (or gate-drain capacitance) couples between the input terminal and the gate, and the gate voltage changes in phase with the input signal. As a result, fluctuations in the voltage between the gate and source of the first MOSFET are suppressed, and fluctuations in on-resistance are also suppressed, so that distortion of the analog signal can be reduced.

  In the on state of the analog switch, a ground voltage may be applied to the second fixed voltage terminal. That is, the second fixed voltage terminal may be a ground terminal. Alternatively, the second fixed voltage terminal may be a negative voltage.

  The analog switch according to an embodiment may further include a P-channel seventh MOSFET connected in series with the sixth MOSFET between the input terminal and the output terminal, and having a gate commonly connected to the gate of the sixth MOSFET.

  Yet another embodiment of the present invention is also an analog switch. The analog switch includes an input terminal for inputting an analog signal, an output terminal for outputting the analog signal, a first MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided between the input terminal and the output terminal, An impedance element provided between the gate of the 1MOSFET and the first fixed voltage terminal and charging / discharging the gate of the first MOSFET in accordance with the voltage of the analog signal.

  The analog signal is an audio signal, and an electroacoustic transducer may be connected to the output terminal as a load. An electroacoustic transducer refers to a device that converts an analog electrical signal into an acoustic wave (sound), such as a speaker, headphones, and earphones. Since the impedance of the electroacoustic transducer is as small as several Ω to several tens of Ω, the above-described analog switch that suppresses fluctuations in the on-resistance of the MOSFET can be suitably used.

Yet another embodiment of the present invention is a selector circuit. This selector circuit includes a plurality of the analog switches described above. The output terminals of the plurality of analog switches are connected in common.
According to this aspect, a low distortion multiplexer can be provided.

Yet another embodiment of the present invention is also a selector circuit. This selector circuit includes a plurality of the analog switches described above. The input terminals of the plurality of analog switches are connected in common.
According to this aspect, a low distortion demultiplexer can be provided.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, etc. are also effective as an aspect of the present invention.

  According to the present invention, an analog switch with low distortion can be provided.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are in an electrically connected state. Including the case of being indirectly connected through other members that do not affect the above. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 1 is a circuit diagram showing a main part of the configuration of the analog switch 10a according to the embodiment. The analog switch 10a includes an input terminal P1, an output terminal P2, a first diode D1, and a capacitor C1.

  The analog switch 10a outputs the input signal IN input to the input terminal P1 from the output terminal P2 in the on state, and the output terminal P2 in the off state is uncorrelated with the input signal IN, for example, a high impedance state or a predetermined voltage. It is assumed to be in a fixed state.

  The input signal IN is an analog signal that requires low distortion, such as an audio signal or a video signal. However, the input signal IN may be any other signal. In the following description, it is assumed that the input signal IN has a waveform that swings positive and negative with the ground voltage (0 V) as a midpoint.

  The first transistor M1 is an N-channel MOSFET and is provided between the input terminal P1 and the output terminal P2. Here, for convenience of explanation, a terminal on the input terminal P1 side of the first transistor M1 is called a source, and a terminal on the output terminal P2 side is called a drain.

  The first diode D1 is provided between the gate of the first transistor M1 and the first fixed voltage terminal P3. The first diode D1 is arranged in such a direction that the cathode is on the gate side of the first transistor M1 and the anode is on the first fixed voltage terminal P3 side.

  In the state where the analog switch 10a is on, the power supply voltage Vdd is applied to the first fixed voltage terminal P3. When the analog switch 10a is turned off, the first transistor M1 may be turned off, and the method is not particularly limited. For example, a ground voltage or a negative voltage may be applied to the first fixed voltage terminal P3. Alternatively, a switch element may be provided in series with the first diode D1, and this may be turned off to cut off the bias applied to the gate of the first transistor M1. FIG. 1 shows only the most basic components of the analog switch 10a, and does not show a configuration for switching on and off. In other words, FIG. 1 shows an equivalent circuit of the analog switch 10a in the ON state.

  A first capacitor C1 is provided between the gate of the first transistor M1 and the input terminal P1. The first capacitor C1 may be formed as an MIM (Metal Insulator Metal) capacitor, or the gate-source capacitance of the first transistor M1 may be used. When formed as an MIM capacitor, there is an advantage that the capacitance value can be designed independently of the size of the first transistor M1. When the gate-source capacitance is used, the transistor size is designed to a value that provides a desired capacitance. Hereinafter, the capacitance between the input terminal P1 and the gate of the first transistor M1 is referred to as a first capacitor C1, regardless of whether it is a MIM capacitor or a parasitic capacitor.

  Similarly, a second capacitor may be provided between the gate of the first transistor M1 and the output terminal P2. Although not shown in FIG. 1, the second capacitor exists as a gate-drain capacitance of the first transistor M1. In addition to the gate-drain capacitance, an MIM capacitor may be provided.

  The above is the basic configuration of the analog switch 10a according to the embodiment. Next, the operation of the analog switch 10a in FIG. 1 will be described. FIG. 2 is a time chart showing the operating state of the analog switch 10a of FIG. The vertical axis and horizontal axis in FIG. 2 are enlarged or reduced as appropriate for easy understanding, and the waveforms shown are also simplified for easy understanding.

  In order to clarify the effect of the circuit of FIG. 1, the operation of a circuit without the first diode D1 will be considered. For example, when the first diode D1 is not provided at the gate of the transistor as in the conventional transfer gate, the gate voltage Vg of the first transistor M1 is fixed to the power supply voltage Vdd as shown by the broken line in FIG. The gate-source voltage Vgs of M1 changes with time in accordance with the voltage value of the input signal IN as indicated by a broken line in FIG. As a result, the on-resistance of the first transistor M1 varies and the drain-source voltage of the first transistor M1 changes, so that the output signal OUT is distorted with respect to the input signal IN.

  In contrast, the analog switch 10a of FIG. 1 operates as follows. The first diode D1 provides high impedance between the first fixed voltage terminal P3 and the gate of the first transistor M1. That is, the gate voltage Vg of the first transistor M1 is not fixed to the power supply voltage Vdd. The first diode D1 functions as an element that charges the first transistor M1.

  In this state, when the input signal IN that swings with the ground voltage (0 V) as shown in FIG. 2 as a bias point is applied to the input terminal P1, the gate between the input terminal P1 and the gate is coupled by the first capacitor C1. The voltage Vg changes in phase with the input signal IN. As shown in FIG. 2, the gate voltage Vg is clamped to (Vdd−Vf) or more by the first diode D1.

  The voltage of the input signal IN corresponds to the source voltage of the first transistor M1. The gate-source voltage Vgs of the first transistor M1 is a potential difference between the gate voltage Vg of the first transistor M1 and the input signal IN. As shown in FIG. 2, as the input signal IN is input, the amount of variation in the gate-source voltage Vgs decreases with time, and is stabilized to a substantially constant value. By stabilizing the gate-source voltage Vgs of the first transistor M1, fluctuations in the on-resistance Ron are suppressed, so that distortion of the output signal OUT with respect to the input signal IN can be reduced.

  In particular, when a load having an impedance of several Ω to several tens of Ω, such as a speaker or a headphone, is connected to the output terminal P2, distortion of the output signal OUT due to fluctuations in the on-resistance of the first transistor M1 becomes significant. Therefore, the analog switch 10 of FIG. 1 and a modification described later can be suitably used for audio applications.

  In the case of a conventional transfer gate, in order to propagate an input signal IN that swings positive and negative with 0 V as a bias point, it is common to bias the gate voltage of the P-channel MOSFET to a negative power supply voltage (−Vdd). Met. On the other hand, the circuit of FIG. 1 uses only the power supply voltage Vdd and does not require a negative power supply, which has the advantage that the circuit can be simplified.

  In addition, since the gate of the first transistor M1 is set to the high impedance state by the first diode D1, the phase delay can be reduced compared to the case where the resistance is set to high impedance.

  Hereinafter, some modifications based on the configuration of FIG. 1 will be described.

FIG. 3 is a circuit diagram showing a configuration of the analog switch 10b according to the first modification. The analog switch 10b of FIG. 3 further includes a second transistor M2 and a second capacitor C2 in addition to the configuration of the analog switch 10a of FIG.
The second transistor M2 is an N-channel MOSFET of the same type as the first transistor M1, and is connected in series with the first transistor M1 between the input terminal P1 and the output terminal P2. The gate of the second transistor M2 is connected in common with the gate of the first transistor M1. For convenience of explanation, the terminal on the output terminal P2 side of the second transistor M2 is called a source, and the terminal on the first transistor M1 side is called a drain.

  The back gate of the first transistor M1 is connected to the connection point N1 side of the first transistor M1 and the second transistor M2, that is, the drain side of the first transistor M1, and the back gate of the second transistor M2 is connected to the connection point N1 side, That is, it is desirable to connect to the drain side of the second transistor M2.

  The second capacitor C2 is provided between the gate of the second transistor M2 and the output terminal P2. The second capacitor C2 may be formed as a MIM (Metal Insulator Metal) capacitor, or the gate-source capacitance of the second transistor M2 may be used. Hereinafter, the capacitance between the output terminal P2 and the gate of the second transistor M2 is referred to as a second capacitor C2, regardless of whether it is a MIM capacitor or a parasitic capacitor.

  According to the modification of FIG. 3, the body diode (not shown) of the first transistor M1 and the body diode (not shown) of the second transistor M2 are connected in the opposite directions between the input terminal P1 and the output terminal P2. . As a result, it is possible to increase the isolation between the input terminal P1 and the output terminal P2 when the analog switch 10b is in the off state.

  FIG. 4 is a circuit diagram showing a configuration of an analog switch 10c according to the second modification. The analog switch 10c of FIG. 4 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, an eighth transistor M8, and a ninth transistor M9 in addition to the configuration of FIG. The transistors M3, M4, M5, M8, and M9 are provided to switch the analog switch 10c on and off. In FIG. 4, the first capacitor C1 and the second capacitor C2 are omitted.

  The third transistor M3 is provided between the first fixed voltage terminal P3 and the anode of the first diode D1, and the gate voltage is controlled according to whether the analog switch 10c is turned on or off. That is, the control signal #CNT (# indicates logic inversion in the specification) that is low level when the analog switch 10c is on is input to the gate of the third transistor M3.

  The fourth transistor M4 is provided between the connection point N1 of the first transistor M1 and the second transistor M2 and the cathode of the first diode D1. The gate voltage of the fourth transistor M4 is controlled according to whether the analog switch 10c is turned on or off. A resistor R3 is provided between the gate of the fourth transistor M4 and the connection point N1. In addition, an eighth transistor M8 having a control signal CNT input to the gate is provided between the power supply terminal and the gate of the fourth transistor M4. When the control signal CNT is at a high level, the eighth transistor M8 is turned off. At this time, the gate of the fourth transistor M4 is pulled down by the resistor R3, and the fourth transistor M4 is turned off. When the control signal CNT is at a low level, the eighth transistor M8 is turned on, the gate of the fourth transistor M4 is at a high level, and the fourth transistor M4 is turned on.

  The fifth transistor M5 and the ninth transistor M9 are provided in series between the connection point N1 of the first transistor M1 and the second transistor M2 and the ground terminal. The gate voltages of the fifth transistor M5 and the ninth transistor M9 are controlled according to the control signal CNT. The gate of the fifth transistor M5 is connected in common with the gate of the fourth transistor M4. When the control signal CNT is high level and the eighth transistor M8 is turned off, the gate of the fifth transistor M5 is pulled up by the resistor R3, and the fifth transistor M5 is turned off. The control signal #CNT is input to the gate of the ninth transistor M9.

  According to the analog switch 10c of FIG. 4, when the control signal CNT is at a high level, the fourth transistor M4, the fifth transistor M5, and the ninth transistor M9 are turned off, and the third transistor M3 is turned on. It becomes the same state as the analog switch 10b, and the input signal IN of the input terminal P1 can be output from the output terminal P2.

  When the control signal CNT is at a low level, the fifth transistor M5 and the ninth transistor M9 are turned on, and the connection point N1 is grounded. Further, since the fourth transistor M4 is turned on, the gates of the first transistor M1 and the second transistor M2 are also grounded. As a result, at least one of the first transistor M1 and the second transistor M2 is always turned off, so that the input terminal P1 and the output terminal P2 can be blocked. Moreover, it is possible to prevent a wasteful current from flowing from the first fixed voltage terminal P3 to the ground by turning off the third transistor M3.

  Although the fifth transistor M5, the ninth transistor M9, the fourth transistor M4, the third transistor M3, and the eighth transistor M8 have the advantages described above, some transistors may be selectively used.

  FIG. 5 is a circuit diagram showing a configuration of an analog switch 10d according to a third modification. The analog switch 10d of FIG. 5 includes a sixth transistor M6, a second diode D2, a third capacitor C3, and a fourth capacitor C4 in addition to the analog switch 10a of FIG.

  The sixth transistor M6 is a P-channel MOSFET, and is provided between the input terminal P1 and the output terminal P2. The second diode D2 is disposed between the gate of the sixth transistor M6 and the second fixed voltage terminal P4 so that the anode is on the gate side of the sixth transistor M6. Preferably, the ground voltage is applied to the second fixed voltage terminal P4 when the analog switch 10d is on.

  A third capacitor C3 is provided between the gate of the second transistor M2 and the input terminal P1, and a fourth capacitor C4 is provided between the gate and the output terminal P2. The third capacitor C3 and the fourth capacitor C4 may be MIM capacitances, or may be parasitic capacitances (gate-source capacitances, gate-drain capacitances) of the sixth transistor M6.

  According to the circuit of FIG. 5, since the gate of the sixth transistor M6 is grounded via the second diode D2, it has a high impedance. Since the third capacitor C3 is coupled between the input terminal P1 and the gate of the sixth transistor M6, the gate voltage of the sixth transistor M6 also swings in phase with the input signal IN. As a result, the gate-source voltage of the sixth transistor M6 is kept constant, fluctuations in the on-resistance of the sixth transistor M6 are suppressed, and signal distortion can be reduced.

  According to the analog switch 10d of FIG. 5, since the combined impedance between the input terminal P1 and the output terminal P2 is smaller than that of FIG. 1, signal attenuation can be reduced.

  FIGS. 6A and 6B are circuit diagrams showing configurations of analog switches 10e and 10f according to the fourth modification. FIG. 6A is a modification of FIG. 5 and is a circuit in which the fifth transistor M5, the first diode D1, the first capacitor C1, and the second capacitor C2 are omitted.

  The analog switch 10f in FIG. 6B includes a seventh transistor M7 in addition to the configuration in FIG. The seventh transistor M7 is a P-channel MOSFET, and is connected in series with the sixth transistor M6 between the input terminal P1 and the output terminal P2. The gate of the seventh transistor M7 is connected in common with the gate of the sixth transistor M6. That is, it can be understood that the analog switches 10e and 10f in FIGS. 6A and 6B are replaced with the P-channel MOSFETs of the analog switches 10a and 10b in FIGS. . Therefore, the modification described with reference to FIG. 4 can be applied to the circuits of FIGS. 6A and 6B.

  FIG. 7 is a circuit diagram showing a configuration of an analog switch 10g according to a fifth modification. The analog switch 10g in FIG. 7 further includes a first resistor R1 provided in series with the first diode D1 between the gate of the first transistor M1 and the first fixed voltage terminal P3. By providing the resistor R1, the impedance between the gate of the first transistor M1 and the first fixed voltage terminal P3 can be adjusted. The positions of the resistor R1 and the first diode D1 may be reversed. Further, a resistor may be provided in series with the second diode D2 shown in FIG. 5, FIG. 6 (a), (b).

  From a different point of view, some of the analog switches described above can be grasped as follows. That is, an analog switch of an aspect includes an input terminal P1 to which an analog signal IN is input, an output terminal P2 for outputting the analog signal OUT, a MOSFET provided between the input terminal P1 and the output terminal P2, An impedance element that is provided between the gate of the MOSFET and the fixed voltage terminal and charges the gate of the MOSFET. The “impedance element” means a circuit element having an impedance that can change without the gate voltage of the MOSFET being restricted by the voltage of the fixed voltage terminal. In the embodiment, the impedance element is a diode or a combination of a diode and a resistor.

  FIGS. 8A and 8B are block diagrams showing a configuration of a selector circuit using any one of the above-described analog switches 10 to 10g (simply referred to as 10). FIG. 8A shows the multiplexer 20, and FIG. 8B shows the demultiplexer 30. The multiplexer 20 in FIG. 8A includes a plurality of analog switches 10. The analog switch may be any of the circuits described above. The output terminals of the plurality of analog switches 10 are connected in common, and different signals are input to the respective input terminals. The demultiplexer 30 in FIG. 8B includes a plurality of analog switches 10. The analog switch may be any of the circuits described above. The input terminals of the plurality of analog switches 10 are connected in common, and different circuit blocks are connected to the respective output terminals. According to the multiplexer 20 and the demultiplexer 30, it is possible to reduce the distortion of the propagated signal.

  In the embodiment, the case where an analog signal is propagated to the analog switch 10 has been described. However, a digital signal may be propagated. Further, a differential signal may be propagated by using two analog switches in pairs.

  Although the present invention has been described above based on the embodiments, it should be understood that the embodiments merely illustrate the principles and applications of the present invention, and the embodiments are within the scope of the claims. Needless to say, many modifications and arrangements can be made without departing from the concept of the present invention.

It is a circuit diagram which shows the principal part of the structure of the analog switch which concerns on embodiment. It is a time chart which shows the operation state of the analog switch of FIG. It is a circuit diagram which shows the structure of the analog switch which concerns on a 1st modification. It is a circuit diagram which shows the structure of the analog switch which concerns on a 2nd modification. It is a circuit diagram which shows the structure of the analog switch which concerns on a 3rd modification. 6A and 6B are circuit diagrams showing a configuration of an analog switch according to a fourth modification. It is a circuit diagram which shows the structure of the analog switch which concerns on a 5th modification. FIGS. 8A and 8B are block diagrams showing the configuration of a selector circuit using an analog switch.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Analog switch, P1 ... Input terminal, P2 ... Output terminal, P3 ... First fixed voltage terminal, P4 ... Second fixed voltage terminal, M1 ... First transistor, M2 ... Second transistor, M3 ... Third transistor, M4 ... 4th transistor, M5 ... 5th transistor, M6 ... 6th transistor, M7 ... 7th transistor, M8 ... 8th transistor, M9 ... 9th transistor, D1 ... 1st diode, D2 ... 2nd diode, C1 ... 1st 1 capacitor, C2 ... 2nd capacitor, C3 ... 3rd capacitor, C4 ... 4th capacitor, 20 ... multiplexer, 30 ... demultiplexer.

Claims (16)

An input terminal to which an analog signal is input;
An output terminal for outputting the analog signal;
An N-channel first MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided between the input terminal and the output terminal;
A first diode disposed between a gate of the first MOSFET and a first fixed voltage terminal in a direction in which a cathode is on the gate side;
An analog switch comprising:   2. The analog according to claim 1, wherein the analog signal is a signal that swings positive and negative with respect to a ground voltage, and a power supply voltage is applied to the first fixed voltage terminal in an ON state of the analog switch. switch.   2. The N-channel second MOSFET further connected in series with the first MOSFET between the input terminal and the output terminal and having a gate connected in common with the gate of the first MOSFET. Analog switch.   4. The analog switch according to claim 1, further comprising a first capacitor provided as a MIM (Metal Insulator Metal) capacitor between the input terminal and the gate of the first MOSFET. 5.   5. The analog switch according to claim 1, further comprising a second capacitor provided as an MIM capacitor between the output terminal and the gate of the first MOSFET.   4. The method according to claim 3, further comprising a third MOSFET provided between the first fixed voltage terminal and an anode of the first diode and having a gate voltage controlled in accordance with on / off of the analog switch. Analog switch described.   And a fourth MOSFET provided between a connection point of the first MOSFET and the second MOSFET and a cathode of the first diode, wherein a gate voltage is controlled according to ON / OFF of the analog switch. The analog switch according to claim 3.   4. The device according to claim 3, further comprising a fifth MOSFET provided between a connection point of the first MOSFET and the second MOSFET and a ground terminal, wherein a gate voltage is controlled according to on / off of the analog switch. Analog switch described.   4. The analog switch according to claim 1, further comprising a first resistor provided in series with the first diode between a gate of the first MOSFET and a first fixed voltage terminal. 5. A P-channel sixth MOSFET provided between the input terminal and the output terminal;
A second diode disposed between the gate of the sixth MOSFET and a second fixed voltage terminal in an orientation in which an anode is on the gate side;
The analog switch according to claim 1, further comprising: An input terminal to which an analog signal is input;
An output terminal for outputting the analog signal;
A P-channel sixth MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided between the input terminal and the output terminal;
A second diode disposed between the gate of the sixth MOSFET and a second fixed voltage terminal in an orientation in which an anode is on the gate side;
An analog switch comprising:   12. The analog according to claim 11, wherein the analog signal is a signal that swings positive and negative with respect to a ground voltage, and a ground voltage is applied to the second fixed voltage terminal when an analog switch is on. switch.   12. The seventh MOSFET according to claim 11, further comprising a P-channel seventh MOSFET connected in series with the sixth MOSFET between the input terminal and the output terminal, the gate of which is connected in common with the gate of the sixth MOSFET. Analog switch. The analog switch according to any one of claims 1 to 13 , wherein the analog signal is an audio signal, and an electroacoustic transducer is connected to the output terminal as a load. A plurality of analog switches according to any one of claims 1 to 13 ,
A selector circuit characterized in that output terminals of the plurality of analog switches are connected in common. A plurality of analog switches according to any one of claims 1 to 13 ,
A selector circuit, wherein input terminals of the plurality of analog switches are connected in common.

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