JP5091548B2 - メモリシステム - Google Patents

メモリシステム Download PDF

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Publication number
JP5091548B2
JP5091548B2 JP2007150548A JP2007150548A JP5091548B2 JP 5091548 B2 JP5091548 B2 JP 5091548B2 JP 2007150548 A JP2007150548 A JP 2007150548A JP 2007150548 A JP2007150548 A JP 2007150548A JP 5091548 B2 JP5091548 B2 JP 5091548B2
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JP
Japan
Prior art keywords
dram
cache memory
data
master
controller
Prior art date
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Expired - Fee Related
Application number
JP2007150548A
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English (en)
Japanese (ja)
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JP2008305082A (ja
JP2008305082A5 (enExample
Inventor
和憲 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kawasaki Microelectronics Inc
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Kawasaki Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Kawasaki Microelectronics Inc filed Critical Kawasaki Microelectronics Inc
Priority to JP2007150548A priority Critical patent/JP5091548B2/ja
Publication of JP2008305082A publication Critical patent/JP2008305082A/ja
Publication of JP2008305082A5 publication Critical patent/JP2008305082A5/ja
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Publication of JP5091548B2 publication Critical patent/JP5091548B2/ja
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  • Memory System Of A Hierarchy Structure (AREA)
JP2007150548A 2007-06-06 2007-06-06 メモリシステム Expired - Fee Related JP5091548B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007150548A JP5091548B2 (ja) 2007-06-06 2007-06-06 メモリシステム

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007150548A JP5091548B2 (ja) 2007-06-06 2007-06-06 メモリシステム

Publications (3)

Publication Number Publication Date
JP2008305082A JP2008305082A (ja) 2008-12-18
JP2008305082A5 JP2008305082A5 (enExample) 2010-07-22
JP5091548B2 true JP5091548B2 (ja) 2012-12-05

Family

ID=40233775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007150548A Expired - Fee Related JP5091548B2 (ja) 2007-06-06 2007-06-06 メモリシステム

Country Status (1)

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JP (1) JP5091548B2 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8933947B2 (en) 2009-09-10 2015-01-13 Ati Technologies Ulc Reading a local memory of a processing unit
JP7541731B2 (ja) * 2019-02-16 2024-08-29 国立大学法人東北大学 デバイス、センサノード及びマイクロコントローラにおける処理方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2522176B2 (ja) * 1993-08-13 1996-08-07 日本電気株式会社 プロセッサの制御方法
JP3445873B2 (ja) * 1994-06-06 2003-09-08 株式会社日立製作所 データプリフェッチ方法およびそのための情報処理装置
US6311260B1 (en) * 1999-02-25 2001-10-30 Nec Research Institute, Inc. Method for perfetching structured data
JP3594081B2 (ja) * 2001-01-23 2004-11-24 日本電気株式会社 情報処理装置

Also Published As

Publication number Publication date
JP2008305082A (ja) 2008-12-18

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