JP2008305082A5 - - Google Patents
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- Publication number
- JP2008305082A5 JP2008305082A5 JP2007150548A JP2007150548A JP2008305082A5 JP 2008305082 A5 JP2008305082 A5 JP 2008305082A5 JP 2007150548 A JP2007150548 A JP 2007150548A JP 2007150548 A JP2007150548 A JP 2007150548A JP 2008305082 A5 JP2008305082 A5 JP 2008305082A5
- Authority
- JP
- Japan
- Prior art keywords
- dram
- cache memory
- read command
- master
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007150548A JP5091548B2 (ja) | 2007-06-06 | 2007-06-06 | メモリシステム |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007150548A JP5091548B2 (ja) | 2007-06-06 | 2007-06-06 | メモリシステム |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2008305082A JP2008305082A (ja) | 2008-12-18 |
| JP2008305082A5 true JP2008305082A5 (enExample) | 2010-07-22 |
| JP5091548B2 JP5091548B2 (ja) | 2012-12-05 |
Family
ID=40233775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007150548A Expired - Fee Related JP5091548B2 (ja) | 2007-06-06 | 2007-06-06 | メモリシステム |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5091548B2 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8933947B2 (en) | 2009-09-10 | 2015-01-13 | Ati Technologies Ulc | Reading a local memory of a processing unit |
| JP7541731B2 (ja) * | 2019-02-16 | 2024-08-29 | 国立大学法人東北大学 | デバイス、センサノード及びマイクロコントローラにおける処理方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2522176B2 (ja) * | 1993-08-13 | 1996-08-07 | 日本電気株式会社 | プロセッサの制御方法 |
| JP3445873B2 (ja) * | 1994-06-06 | 2003-09-08 | 株式会社日立製作所 | データプリフェッチ方法およびそのための情報処理装置 |
| US6311260B1 (en) * | 1999-02-25 | 2001-10-30 | Nec Research Institute, Inc. | Method for perfetching structured data |
| JP3594081B2 (ja) * | 2001-01-23 | 2004-11-24 | 日本電気株式会社 | 情報処理装置 |
-
2007
- 2007-06-06 JP JP2007150548A patent/JP5091548B2/ja not_active Expired - Fee Related
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