JP5084922B2 - Solid-state imaging device, camera, and information processing device - Google Patents

Description

  The present invention relates to a solid-state imaging device such as a line sensor or an area sensor, and a camera and an information processing device including the solid-state imaging device.

  In general, in a solid-state imaging device such as a line sensor or an area sensor, a large number of sensor cells each including a photoelectric conversion element are arranged in a line shape or a two-dimensional shape. The output of each sensor cell is temporarily held in a hold capacitor, and then distributed to the common signal line via the switching transistor, whereby the potential of the common signal line changes. The potential on the common signal line is amplified and output by an amplifier.

  The common signal line has a wiring capacitance as a parasitic capacitance, and also has a parasitic capacitance corresponding to the drain capacitance of the switching transistor for the number of sensor cells in the line direction. This is due to the fact that switching transistors for the number of sensor cells in the line direction are connected to the common signal line.

  When the parasitic capacitance of the common signal line increases, the potential change of the common signal line when the charge held in the hold capacitor is distributed to the common signal line is reduced. In recent years, solid-state imaging devices have become larger in size and larger in size, and along with this, the parasitic capacitance of the common signal line increases due to an increase in the number of switching transistors (an increase in total source capacitance) and an increase in wiring capacitance. There is a tendency.

  A photoelectric conversion device that attempts to solve such a problem is disclosed in Japanese Patent Application Laid-Open No. 2-268063. FIG. 1 is a diagram illustrating a configuration of a photoelectric conversion device disclosed in the publication. In this photoelectric conversion device, one MOS transistor TH1 is provided for two photoelectric conversion elements S1 and S2. Therefore, the total number of MOS transistors connected to the common output signal line SL is ½ of the number of columns, and the parasitic capacitance of the output signal line SL is reduced. The photoelectric conversion elements S1 and S2 are connected to the signal line H1 via the MOS transistors Ts1 and Ts2. Outputs of the photoelectric conversion elements S1 and S2 are respectively stored in capacitors C1 and C2 connected in common to the signal line H1, and are sequentially distributed on the output signal line SL via the MOS transistor TH1.

JP 63-142781 A Japanese Patent No. 2590081 Japanese Patent Laid-Open No. 2001-257938 Japanese Patent No. 2678062

  However, in the photoelectric conversion device described in the above publication, capacitors C1 and C2 as hold capacitors are commonly connected to the signal line H1. Therefore, although the parasitic capacitance of the output signal line SL is reduced, the parasitic capacitance of the signal line H1 is increased. Such a disadvantage is slight when the number of capacitors commonly connected to the signal line H1 is small (that is, when the unit of blocking is small), but the number of capacitors commonly connected to the signal line H1. It can become apparent with the increase of. This means that the load to be driven by the photoelectric conversion elements S1 and S2 increases, which is not preferable. Further, since it is difficult to make the positional relationship between the capacitor C1 and the photoelectric conversion element S1 and the positional relationship between the capacitor C2 and the photoelectric conversion element S2 difficult, the readout path for the photoelectric conversion element S1 and the photoelectric conversion element It is difficult to ensure the identity of the conversion element S2 with the read path.

  The present invention has been made in view of the above background. For example, the parasitic capacitance of the common signal line can be reduced and / or read without increasing the load to be driven by the sensor cell including the photoelectric conversion element. It is an object of the present invention to reduce the parasitic capacitance of a common signal line while facilitating ensuring of path identity.

  A first aspect of the present invention relates to a solid-state imaging device in which a plurality of sensor cells each having a photoelectric conversion element are arranged, and the solid-state imaging device includes a plurality of hold capacitors that respectively hold signals from the plurality of sensor cells. A plurality of first switches that respectively transfer the signals of the plurality of hold capacitors; a plurality of blocking regions that connect outputs of the plurality of first switches in units of a predetermined number; a common signal line; And a plurality of second switches for transferring the charges in the blocked region to the common signal line.

  According to a preferred embodiment of the present invention, it is preferable that the solid-state imaging device further includes a capacitive feedback amplifier that amplifies a signal appearing on the common signal line. Here, the capacitive feedback amplifier includes, for example, a differential amplifier having an input terminal connected to the common signal line, and a feedback capacitor connected between the input terminal and the output terminal of the differential amplifier. Including.

  According to a preferred embodiment of the present invention, the array of the plurality of sensor cells includes an effective pixel portion and an optical black portion, and the effective pixel portion and the optical black portion belong to different blocks. preferable.

  According to a preferred embodiment of the present invention, the predetermined number is preferably a common divisor of the number of the optical black portions in the direction in which the plurality of hold capacitors are arranged.

  According to a preferred embodiment of the present invention, the solid-state imaging device supports the sum of signals of the predetermined number of hold capacitors sharing the block area for each block in the predetermined number. It is preferable that a control circuit for controlling the plurality of first switches is further provided so that a signal to be transmitted is transferred to the common signal line.

  According to a preferred embodiment of the present invention, the plurality of sensor cells may be arranged two-dimensionally in a horizontal direction and a vertical direction, and in this case, the solid-state imaging device is configured by arranging the plurality of sensor cells. It is preferable to further include a control circuit that executes control so that a signal corresponding to the sum of readout signals from the predetermined number of sensor cells is obtained for each block in the row with the predetermined number of columns as a unit. .

  According to a preferred embodiment of the present invention, the solid-state imaging device includes a scanning circuit that controls the plurality of first switches and the plurality of second switches so that the signals of the sensor cells are read in a predetermined order. It is preferable to further provide.

  According to a preferred embodiment of the present invention, the scanning circuit includes the first switch and the second switch among the plurality of first switches connected to the same blocked signal line by a common pulse. It is preferable that the second switch is turned off according to the timing when the first switch is turned on and the last first switch is turned on.

  According to a preferred embodiment of the present invention, the solid-state imaging device opens the second switch connected to the blocked area for a sensor cell from which a signal is to be read to open the blocked area and the common signal line. It is preferable to further include a drive circuit that controls a reset operation and a signal read operation so that the first switch for the sensor cell is opened and the signal of the sensor cell is read after the reset.

  According to a preferred embodiment of the present invention, it is preferable that a clamp circuit for clamping a signal from the sensor cell is further provided between the first switch and the sensor cell.

  According to a preferred embodiment of the present invention, the solid-state imaging device turns off the plurality of second switches for each block having the predetermined number as a unit, and the plurality of first switches Is turned on, the signals are averaged between the predetermined number of hold capacitors sharing the block area, and the averaged hold capacity signal is read out sequentially or in units of blocks or every several bits. It is desirable to further comprise a control circuit for controlling the plurality of first switches and second switches.

  According to a preferred embodiment of the present invention, in the solid-state imaging device, the plurality of sensor cells are arranged two-dimensionally in a horizontal direction and a vertical direction, and the solid-state imaging device includes the plurality of sensor cells. For each row in the array, a control circuit that further performs control is provided so that a signal corresponding to an average value of readout signals from the predetermined number of sensor cells is obtained for each block having the predetermined number of columns as a unit. Is desirable.

  A second aspect of the present invention relates to a camera such as an electronic camera, and includes the solid-state imaging device and a processor that processes an image captured by the solid-state imaging device.

  According to a third aspect of the present invention, the solid-state imaging device includes a processor that processes an image captured by the solid-state imaging device.

  According to the present invention, for example, it is possible to reduce the parasitic capacitance of the common signal line without increasing the load to be driven by the sensor cell including the photoelectric conversion element and / or to easily ensure the read path identity. The parasitic capacitance of the common signal line can be reduced.

  Thereby, for example, an image signal can be read with a high read gain or an SN ratio.

It is a figure which shows the structure of the conventional photoelectric conversion apparatus. It is a figure which shows the structure of the solid-state imaging device of suitable embodiment of this invention. It is a figure which shows the structural example of a sensor cell. It is a figure which shows the example of control of a 1st switch and a 2nd switch. It is a figure which shows the example of control of the 1st switch at the time of addition operation, and a 2nd switch. It is a figure which shows schematic structure of the camera incorporating the solid-state imaging device shown in FIG. It is a figure explaining a high resolution mode and a low resolution mode. It is a figure which shows notionally the solid-state imaging device provided with the optical black part. It is a figure which shows the specific structural example of a horizontal scanning circuit. It is a figure which shows the specific structural example of a horizontal scanning circuit. It is a figure which shows the specific structural example of a horizontal scanning circuit. 12 is a timing chart of the horizontal scanning circuit shown in FIGS. It is a figure which shows the concept of multistage block-ization. It is a figure which shows the structure of the solid-state imaging device of other embodiment of this invention. It is a figure which shows the structural example of a sensor cell. It is a figure which shows the structure of the solid-state imaging device of further another embodiment of this invention.

  Hereinafter, a solid-state imaging device according to a preferred embodiment of the present invention will be described. Although this embodiment is an example in which the present invention is applied to an area sensor, the present invention can also be applied to a line sensor.

  FIG. 2 is a diagram showing the configuration of the solid-state imaging device according to the preferred embodiment of the present invention. Here, for the sake of simplicity of explanation, a solid-state imaging device having a two-dimensional array of 4 rows and 4 columns will be described, but the present invention is naturally applicable to a solid-state imaging device having more pixels. Can do.

  In FIG. 2, the sensor cell 2 (2-11, 2-12, 2-13, 2-14, 2-21, 2-22, 2-23, 2-24, 2-31, 2-32, 2-33 , 2-34, 2-41, 2-41, 2-42, 2-43, 2-44) are arranged in 4 rows and 4 columns (4 columns in the horizontal direction and 4 rows in the vertical direction). As exemplarily shown in FIG. 3, each sensor cell 2 can be configured by, for example, a signal transfer transistor 41, a photodiode (photoelectric conversion element) 42, and a reset transistor 43. A charge signal generated in the photodiode 42 by light incident on the photodiode 42 is transferred to the vertical signal line (first common signal line) 5 as a voltage signal through the signal transfer transistor 41. The reset transistor 43 resets the photodiode 42 according to the reset signal 30 supplied from the vertical scanning circuit 4 or the like, for example.

  In the two-dimensionally arranged rows of sensor cells 2, the vertical scanning circuit 4 sets the corresponding selection signal line among the selection signal lines 3 (3-1, 3-2, 3-3, 3-4) to the active level (H level). ). The vertical scanning circuit 4 scans in the vertical direction by sequentially setting the four selection signal lines 3 to the active level according to the control signal VCON from the control circuit 14 when reading the signal from the sensor cell 2.

  Prior to reading of each row (more specifically, activation of the selection signal line), the vertical control for controlling the reset circuit 1 (1-1, 1-2, 1-3, 1-4) including MOS transistors or the like is performed. The reset signal VRST is set to an active level (H level), and the transfer signal line TRAN for controlling the transfer transistor 6 (6-1, 6-2, 6-3, 6-4) composed of a MOS transistor or the like is activated. By setting the level (H level), the vertical signal line 5 (5-1, 5-2, 5-3, 5-4) and the hold capacitor 7 (7-1, 7-2, 7-3, 7- 4) is reset.

  When the selection signal line (for example, 3-1) becomes an active level and the transfer transistor 41 (see FIG. 3) is turned on, the sensor cell (for example, 2-11, 2-12, 2-13, 2-14) is vertical. The signal line 5 (5-1, 5-2, 5-3, 5-4) is driven, and the voltage signal is transferred to the vertical signal line 5.

  The voltage signal appearing on the vertical signal line 5 (5-1, 5-2, 5-3, 5-4) passes through the transfer transistor 6 (6-1, 6-2, 6-3, 6-4). Hold capacitor 7 (7-1, 7-2, 7-3, 7-) having one end (signal terminal) connected to signal line 19 (19-1, 19-2, 19-3, 19-4). 4). For example, a ground potential is applied to the other end of each hold capacitor 7.

  The charges held in the hold capacitors 7-1 and 7-2 are blocked into horizontal signal lines (blocked regions) 9 via the first switches 8-1 and 8-2 configured by MOS transistors or the like. Distributed over -1. In other words, the charges held in the hold capacitors 7-1 and 7-2 are blocked from the capacitances visible on the signal lines 19-1 and 19-2 to which the signal terminals of the hold capacitors 7-1 and 7-2 are connected. Accordingly, a potential corresponding to the electric charge held in the hold capacitor 7-1 or 7-2 appears on the blocked horizontal signal line 9-1. Since the charges held in the hold capacitors 7-1 and 7-2 cannot be simultaneously distributed to the blocked horizontal signal line 9-1, the first switches 8-1 and 8-2 are turned on at different timings. Put into a state. The parasitic capacitance of the blocked horizontal signal line 9-1 includes not only the wiring capacitance but also the source capacitance of the first switches 8-1 and 8-2, the drain capacitance of the second switch 10-1, and the like.

  Similarly, the charges held in the hold capacitors 7-3 and 7-4 are transferred to the blocked horizontal signal lines (blocked) via the first switches 8-3 and 8-4 configured by MOS transistors or the like. Area) 9-2. That is, the charges held in the hold capacitors 7-3 and 7-4 are blocked from the capacitances visible on the signal lines 19-3 and 19-4 to which the signal terminals of the hold capacitors 7-3 and 7-4 are connected. Accordingly, a potential corresponding to the charge held in the hold capacitor 7-3 or 7-4 appears on the blocked horizontal signal line 9-2. Since the charges held in the hold capacitors 7-3 and 7-4 cannot be simultaneously distributed to the blocked horizontal signal line 9-2, the first switches 8-3 and 8-4 are turned on at different timings. Put into a state. The parasitic capacitance of the blocked horizontal signal line 9-2 includes the source capacitance of the first switches 8-3 and 8-4, the drain capacitance of the second switch 10-2, and the like in addition to the wiring capacitance.

  The charges appearing on the blocked horizontal signal line 9-1 by the charge distribution are further distributed on the common horizontal signal line (second common signal line) 11 via the second switch 10-1. That is, the charge held in the hold capacitor 7-1 (or 7-2) is transferred to the hold capacitor 7-1 (or via the first switch 8-1 (or 8-2) and the second switch 10-1. 7-2) is distributed by the capacity visible on the signal line 19-1 (or 19-2) to which the signal terminal is connected, the parasitic capacity of the blocked horizontal signal line 9-1, and the parasitic capacity of the horizontal signal line 11. . As a result, a potential corresponding to the charge held in the hold capacitor 7-1 (or 7-2) appears on the common horizontal signal line 11.

  Similarly, the charges appearing on the blocked horizontal signal line 9-2 by the charge distribution are further distributed onto the common horizontal signal line 11 via the second switch 10-2. That is, the electric charge held in the hold capacitor 7-3 (or 7-4) passes through the first switch 8-3 (or 8-4) and the second switch 10-2, and the hold capacitor 7-3 (or 7-4) is distributed by the capacitance visible on the signal line 19-3 (or 19-4) to which the signal terminal is connected, the parasitic capacitance of the blocked horizontal signal line 9-2, and the parasitic capacitance of the horizontal signal line 11. . As a result, a potential corresponding to the charge held in the hold capacitor 7-3 (or 7-4) appears on the common horizontal signal line 11.

  That is, in this embodiment, the array (or the first switch 8) of the sensor cells 2 in four columns is blocked in units of two columns, and the blocked horizontal signal lines 9-1 and 9-2 of each block are respectively second. The common horizontal signal line 11 is connected via the switches 10-1 and 10-2. Therefore, the parasitic capacitance of the switch (transistor) visible on the common horizontal signal line 11 is the parasitic capacitance of the switches 10-1 and 10-2 for two columns, which is 1/2 of the four columns. Furthermore, the parasitic capacitance of the switch visible on the common horizontal signal line 11 can be reduced to ½ by blocking (dividing) into two blocks.

  In the example shown in FIG. 2, the sensor cell array (or the first switch) in four columns is divided into two in units of two columns, but it should be noted that this is for simplification of description. When this principle is generalized, when the sensor cell array (or the first switch) is blocked (divided into n) in units of n columns, the parasitic capacitance of the switch visible on the common horizontal signal line 11 is 1 / n.

  Here, the expression of dividing or dividing the sensor cell array (or the first switch) is used here, but if another expression is used, it can also be referred to as division of the common horizontal signal line.

  By blocking or dividing, the parasitic capacitance visible on the common horizontal signal line 11 can be greatly reduced. Thereby, the potential change of the common horizontal signal line 11 when the charge held in the hold capacitor 7 is distributed to the common horizontal signal line 11 can be increased. This means that the read gain from the hold capacitor 7 can be increased and the SN ratio can be improved.

  Further, in this embodiment, each column is arranged between the signal line 19 (for example, 19-1) between the transfer switch 6 (for example, 6-1) and the first switch 8 (for example, 8-1). Only the hold capacitor 7 (for example, 7-1) is arranged. Therefore, the wiring length of the signal line 19 can be shortened. As a result, the parasitic capacitance of the signal line 19 can be reduced, and the identity of the structure between read paths (columns) can be easily ensured.

  On the other hand, based on the conventional configuration shown in FIG. 1, for example, when the common vertical signal line H1 is arranged for eight columns, eight capacitors are arranged for the signal line H1, Since it is necessary to arrange transistors (for example, Tr1, Tr2) between the eight capacitors and the ground line, and to arrange signal lines (for example, φc1, φc2) for controlling them, the signal line H1 The wiring length becomes longer, and the load such as parasitic capacitance increases. For this reason, the load to be driven by the photoelectric conversion elements (for example, S1 and S2) increases. Further, in the conventional configuration shown in FIG. 1, it is difficult to ensure the same structure between read paths (columns) as the number of capacitors commonly connected to the signal line H1 increases.

  A signal appearing on the common horizontal signal line 11 is amplified and output by the capacitive feedback amplifier 20. The capacitive feedback amplifier 20 includes, for example, a differential amplifier 21, a feedback capacitor 22 connected in parallel between the inverting input terminal (−) and the output terminal VOUT, and a reset transistor connected in parallel to the feedback capacitor 22. 23. A reference voltage VREF is applied to the non-inverting input terminal (+) of the difference image amplifier 21.

  Here, instead of the capacitive feedback amplifier 20, for example, a voltage readout amplifier can be adopted, but it is more preferable to employ the capacitive feedback amplifier 20. When the capacitive feedback amplifier is employed, the read gain is determined only by the hold capacitor 7 and the feedback capacitor 22, so that it is possible to eliminate the influence of variations in the parasitic capacitance of the blocked horizontal signal lines 9-1 and 9-2. it can. Here, if the value of the hold capacitor 7 is CT and the value of the feedback capacitor 22 is CF, the output voltage VOUT of the amplifier 20 is expressed by the following equation.

VOUT = (CT / CF) · VREF
On the other hand, when the voltage readout type amplifier is employed, the potential appearing on the common horizontal signal line 11 varies among the blocks due to variations in parasitic capacitance of the blocked horizontal signal lines 9-1 and 9-2. There is also a possibility that the output of the voltage readout amplifier that amplifies the voltage varies between the blocks.

  Next, control of the first switch 8 and the second switch 10 after the output signal of the sensor cell 2 in the row selected by the vertical scanning circuit 4 is transferred to the hold capacitor 6 will be described with reference to FIG.

  In this embodiment, the reset signal HRST for resetting the common horizontal signal line 11 and the capacitive feedback amplifier 20 is supplied to the first switches 8-1, 8-2, 8-3 and 8-4 by the control circuit 14. The first transfer control signals T1-1, T1-2, T1-3, T1-4 to be controlled and the second transfer control signals T2-1, T2-2 to control the second switches T2-1, T2-2 are respectively It is generated by a horizontal scanning circuit (drive circuit) 13. The horizontal scanning circuit 13 is controlled by a control signal HCON generated by the control circuit 14.

  First, the second transfer control signal T2-1 is set to the active level (H level), and the second switch 10-1 for the first block is turned on. Thereafter, the reset transistor 12 is turned on during the H pulse of the reset signal HRST which is a pulse signal having a predetermined cycle. As a result, the common horizontal signal line 11 and the blocked horizontal signal line 9-1 are reset, and the capacitive feedback amplifier 20 is reset.

  Next, the first transfer signal T1-1 is set to the active level (H level) for a predetermined period, and the first switch 8-1 for the first column is turned on. As a result, the charge held in the hold capacitor 7-1 in the first column is distributed to the blocked horizontal signal line 9-1 and the common horizontal signal line 11, and the charge is supplied to the voltage signal VOUT by the capacitive feedback amplifier 20. Is read as

  Next, the reset transistor 12 is turned on during the H pulse of the reset signal HRST. As a result, the common horizontal signal line 11 and the blocked horizontal signal line 9-1 are reset, and the capacitive feedback amplifier 20 is reset.

  Next, the first transfer signal T1-2 is set to the active level (H level) for a predetermined period, and the first switch 8-2 for the second column is turned on. As a result, the charge held in the hold capacitor 7-2 in the second column is distributed to the blocked horizontal signal line 9-1 and the common horizontal signal line 11, and the charge is supplied to the voltage signal VOUT by the capacitive feedback amplifier 20. Is read as

  Next, the second transfer signal T2-1 is set to an inactive level (L level), and the second switch 10-1 for the first block is turned off. Thereby, the read operation for the first block is completed.

  Next, the second transfer signal T2-2 is set to the active level (H level), and the second switch 10-2 for the second block is turned on. Thereafter, the reset transistor 12 is turned on during the H pulse of the reset signal HRST. As a result, the common horizontal signal line 11 and the blocked horizontal signal line 9-1 are reset, and the capacitive feedback amplifier 20 is reset.

  Next, the first transfer signal T1-3 is set to the active level (H level) for a predetermined period, and the first switch 8-3 for the third column is turned on. As a result, the charge held in the hold capacitor 7-3 in the third column is distributed to the blocked horizontal signal line 9-2 and the common horizontal signal line 11, and the charge is supplied to the voltage signal VOUT by the capacitive feedback amplifier 20. Is read as

  Next, the reset transistor 12 is turned on during the H pulse of the reset signal HRST. As a result, the common horizontal signal line 11 and the blocked horizontal signal line 9-1 are reset, and the capacitive feedback amplifier 20 is reset.

  Next, the first transfer signal T1-4 is set to the active level (H level) for a predetermined period, and the first switch 8-4 for the fourth column is turned on. As a result, the charge held in the hold capacitor 7-4 in the fourth column is distributed to the blocked horizontal signal line 9-2 and the common horizontal signal line 11, and the charge is supplied to the voltage signal VOUT by the capacitive feedback amplifier 20. Is read as

  Next, the second transfer signal T2-2 is set to an inactive level (L level), and the second switch 10-1 for the second block is turned off. Thereby, the read operation for the second block is completed.

  The above is the reading operation for one row. After this operation, the control circuit 14 sets the reset signal VRST and the transfer signal TRAN to the active level (H level), thereby resetting the vertical signal line 5 and the hold capacitor 7. Thereafter, the vertical scanning circuit 4 sets the selection signal line 3 of the next row to an active level (H level), and the output signal of the sensor cell 2 of the row is transferred to the hold capacitor 7. Thereafter, the read operation is executed for the row in accordance with the procedure number shown in FIG.

  The solid-state imaging device of this embodiment has an addition function for outputting a signal obtained by adding the output signals of the sensor cells 2 in each row for each block. That is, in this solid-state imaging device, charges held in the hold capacitors 7-1 and 7-2 (or 7-3 and 7-4) sharing the blocked horizontal signal line 9-1 (or 9-2). Is distributed to the blocked horizontal signal line 9-1 (or 9-2), whereby sensor cells 2-x1 and 2-x2 (or 2-x3 and 2-x4) (x is It has an addition function for outputting the sum of output signals (any of 1 to 4) (that is, the sum of pixel values in the row direction in each block).

  FIG. 5 is a diagram illustrating timings of the first transfer control signal and the second transfer control signal for realizing the addition function. When the horizontal scanning circuit 13 receives the instruction of the addition operation by the control signal HCON generated by the control circuit 14, the first transfer control signals T1-1, T1-2, T1-3, T1-4 as shown in FIG. The addition operation is controlled by controlling the second transfer control signals T2-1 and T2-2. That is, the first transfer control signals T1-1 and T1-2 (T1-3 and T1-4) are simultaneously set to the active level, and the first switches 8-1 and 8-2 (8-3 and 8-4) are simultaneously set. By turning it on, an addition operation is realized. Thus, the addition operation can be performed at high speed without providing a special arithmetic unit for addition.

  Here, by dividing this sum by the number of columns of the block (2 in this embodiment), the average value of the pixel values of each row in the block can be obtained. The function of calculating such an average value will be further described in an application example described later.

  FIG. 6 is a diagram showing a schematic configuration of a camera in which the solid-state imaging device 100 shown in FIG. 2 is incorporated. Note that this camera is generally called an electronic camera as a concept opposite to a silver salt camera, and includes a still camera, a movie camera, a camera in which those functions are mixedly mounted, and the like. Further, this camera may be incorporated as a part of an information processing apparatus such as a personal computer or a portable terminal.

  A subject image is formed on the solid-state imaging device 100 by a fixed or interchangeable lens unit 110. The output of the solid-state imaging device 100 is supplied to a processor (image processing unit) 120. The signal supplied to the processor 120 may be an analog signal (for example, the above-described VOUT or a signal obtained by processing the same), or may be a digital signal obtained by A / D converting such an analog signal.

  The processor 120 performs image processing on the signal supplied from the solid-state imaging device 100 and supplies the processed signal to the display device 140 or records it in the storage medium 130. The display device 140 can function as an information providing unit that displays various types of information related to shooting and reproduction, and as a viewfinder.

  This camera typically has an exposure adjustment function, a focus adjustment function, and the like. Since these functions can be designed based on a well-known technique, detailed description is omitted here.

  The processor 120 uses an averaging processing unit 121 for calculating an average value of a predetermined number of pixels by using the above-described addition function (a function of adding pixel values in the row direction in units of blocks) in the solid-state imaging device 100. I have.

  This camera realizes the low resolution mode by using the function of the averaging processing unit 121. This will be described with reference to FIG. FIG. 7A conceptually shows an image captured in the high resolution mode. Also here, for the sake of simplicity, it is assumed that the solid-state imaging device 100 has pixels (sensor cells) in 4 rows and 4 columns in accordance with the example shown in FIG. In the high resolution mode, as shown in FIG. 7A, an image composed of pixels in 4 rows and 4 columns is captured.

  On the other hand, in the low resolution mode, as described with reference to FIG. 5, since the pixel values in the row direction are added in units of blocks, an image as schematically shown in FIG. 100. Here, in FIGS. 7A and 7B, if the same subject is imaged under exactly the same conditions, the pixel 211 has a pixel value obtained by adding the values of the pixel 201 and the pixel 202, and the pixel 212. Has a pixel value obtained by adding the values of the pixel 203 and the pixel 204.

  The averaging processing unit 121 calculates an average value of pixel values of four pixels (four pixels at positions corresponding to the pixels 201 to 204) based on the pixel values of the pixels 211 and 212.

  In place of the above processing, for example, only the values of the pixels 211, 213, 215, and 217 (the sum of two pixels) are read from the solid-state imaging device 100, divided by 2, and the result is the pixel 221. , 222, 223, and 224.

  Such a low resolution mode is useful not only as a mode for capturing a low resolution (low pixel count) image as an image to be recorded on the storage medium 130 but also for, for example, a viewfinder to be supplied to the display device 140. It is also useful for obtaining images.

  As described above, by using the addition function of the solid-state imaging device 100, the averaging process or the resolution reduction process can be executed at high speed with a simple calculation.

  Furthermore, as another embodiment, a method for directly reading out an averaged signal will be described. The above-described embodiment is an example in which the added signal is processed by the average processing block of the signal processing block.

  In this embodiment, for each block having the predetermined number as a unit, the plurality of second switches are turned off, the plurality of first switches are turned on, and the blocked signal lines are The signal charge is averaged between the predetermined number of hold capacitors shared.

  After executing this block averaging process, the horizontal scanning circuit is used to sequentially read out the signals of the hold capacitors holding the averaged signal for each block. In this case, since it is sufficient as information to read a signal from one hold capacity for one block, scanning is skipped substantially (reading every several columns).

  As a result, like the addition, the signal readout time per frame can be shortened by the amount of blocking. Specifically, if 8 columns are shared per block, the signal readout time per frame can be shortened to 1/8.

  In addition, averaging within the sensor has an effect of reducing the processing time of image processing. In addition, in the case of an added output, an image including a lot of low luminance is preferable because the signal gain is increased. Unsuitable.

  On the other hand, in the case of an averaged output, the readout gain is the same as that for normal shooting, and is suitable for an image including a large amount of high luminance that requires a dynamic range.

  So far, for simplification of description, it has been described that all the pixels of the solid-state imaging device 100 are used as effective pixels. However, in the following, as a more practical application example, an area where sensor cells are arranged (sensor An example in which a part of the cell array region) is used as an optical black portion will be described.

  In the example shown in FIG. 8, the sensor cell array region of the solid-state imaging device includes an optical black portion (OB) portion 210 for detecting an optical black level and an effective pixel region 220. Here, it is preferable that the common divisor of the number of columns N1 of the OB unit 210 is a block unit (that is, the number of columns of each block). Further, the number of columns N2 of the effective pixel unit 220 is preferably a multiple of the number of columns of the OB unit 210 (in this case, the common divisor of the number of columns N2 of the effective pixel unit 220 is equal to the block unit).

  With this configuration, since the boundary between the OB unit 210 and the effective pixel unit 220 is not located in the block, image processing in units of blocks is facilitated, and for example, the processing in the processor 120 is simplified.

  Next, a specific configuration example of the horizontal scanning circuit 13 will be described as an example. FIG. 9 is a diagram illustrating a specific configuration example of the horizontal scanning circuit 13. Here, in order to explain a more practical example, a case where one block is composed of 8 columns will be described.

  In this configuration example, the horizontal scanning circuit 13 is configured by connecting one shift register 301 in series for one block (one block of the array of sensor cells 2). A predetermined pulse signal PS is input to the first-stage shift register 301, and a shift operation is started in response thereto. A predetermined pulse signal is output from the OUT terminal and input to the next-stage shift register 301. Each shift register 301 outputs BxSEL (x is 1, 2, 3,...) For selecting the corresponding block. In FIG. 2, BxSEL corresponds to transfer control signals (T2-1, T2-2) for selecting the second switches (10-1, 10-2). Each shift register 301 outputs CxSEL <1: 8> (x is 1, 2, 3,...) For selecting a column in the corresponding block. In FIG. 2, CxSEL <1: 8> corresponds to transfer control signals (for example, T1-1 and T1-2) for selecting the first switches (for example, 8-1 and 8-2).

  FIG. 10 is a diagram illustrating a configuration example of each shift register 301. Each shift register 301 is configured by connecting four sets of 2-bit shift registers 401 in series. The four 2-bit shift registers 401 output C_SEL1 to C_SEL8 corresponding to CxSEL <1: 8>. Each shift register 301 includes a block control circuit 402 that generates B_SEL corresponding to the transfer control signal BxSEL for selecting the corresponding block (corresponding second switch).

  The block control circuit 402 activates B_SEL to H level in synchronization with the activation of the input signal to the first-stage 2-bit shift register 401, and synchronizes B_SEL to L level in synchronization with the output signal of the last-stage 2-bit shift register 401. Deactivate. FIG. 11 is a diagram illustrating a configuration example of each 2-bit shift register 401.

  FIG. 12 is a timing chart showing the operation of the horizontal scanning circuit 13 shown in FIGS.

  The solid-state imaging device 100 is an example in which the blocked horizontal signal lines 9-1 and 9-2 are connected to the common horizontal signal line 11 via the second switches 10-1 and 10-2. This can be considered as one-stage blocking. The present invention can also be applied to two or more blocks.

  FIG. 13 is a diagram illustrating a configuration of a solid-state imaging device in which the present invention is applied to two-stage blocking. In FIG. 13, the photoelectric conversion element 2, the vertical scanning circuit 4, the horizontal scanning circuit 13, the amplifier 20, the control circuit 14, and the like are omitted for the sake of drawing.

  In FIG. 13, the first block horizontal signal lines 9-1, 9-2... And the first switches 8-1, 8-2. The blocks are divided into stages, and a predetermined number (two in this case) of the first blocked horizontal signal lines by the second blocked horizontal signal lines 31-1, 31-2 and the second switches 10-1, 10-2. .., 9-2... Are formed in a second block, and the second blocked horizontal signal line 31-1 is further passed through the third switches 30-1, 30-2. , 31-2... Are connected to the common horizontal signal line 11.

  Further, the block may be divided into three or more stages according to such a technical idea.

  By making the blocks in multiple stages in this way, the effect of reducing the parasitic capacitance visible on the common horizontal signal line 11 can be further enhanced.

  The present invention can be applied not only to the solid-state imaging device as shown in FIG. 2, but also to a solid-state imaging device having a configuration as shown in FIG.

  The solid-state imaging device of FIG. 14 has a clamp circuit (capacitor 61 connected in series to the vertical signal line 5 in parallel with the vertical signal line 5 and a parallel connection between the capacitor 61 and the transfer transistor 6 in front of the transfer transistor 6 of the solid-state imaging device of FIG. This is a configuration in which a switch transistor 62) in which one connected terminal is connected to a predetermined potential is arranged. Further, the configuration of one pixel is as shown in FIG.

In FIG. 15, 51 is a photodiode which is a photoelectric conversion unit, 52 is an amplifying transistor which is an amplifying means for amplifying the gate charge and outputting it to the vertical signal line 5, and 53 is generated by the photodiode. A transfer transistor which is a transfer means for transferring charges to the gate of the amplification transistor, 54 is a reset transistor which is a reset means for resetting the gate of the amplification transistor, and 55 is a pixel which outputs a signal. A selection transistor which is a selection means for
Reference numeral 65 in FIG. 14 denotes a load transistor which is a load unit that constitutes the amplification transistor 52 and the source follower circuit described in FIG.

  Next, the operation of the solid-state imaging device of FIG. 14 will be described. First, a reset signal generated by resetting the gate of the amplifying transistor is clamped by a clamp circuit, and then the transfer transistor 53 is turned on, whereby the charge of the photodiode is transferred to the gate of the amplifying transistor. The photoelectric conversion signal output from the amplification transistor is output to the clamp circuit.

  By the above operation, the signal from which the fixed pattern noise and random noise generated for each pixel is removed from the clamp circuit is held in the capacitor 7.

  Other than the above configuration and operation, the solid-state imaging device of FIG. 2 is the same.

  By disposing the clamp circuit, it is possible to suppress fixed pattern noise and random noise generated for each pixel.

  Furthermore, the present invention can be applied to a circuit configuration as shown in FIG. FIG. 16 is configured to output to different horizontal signal lines for each column in the vertical direction. Here, the portion 70 surrounded by a dotted line has the same configuration. The operation is the same as that of the solid-state imaging device of FIG.

  With the circuit configuration as shown in FIG. 16, even when the number of pixels is large, it is not necessary to slow down the readout speed.

Claims (14)

A solid-state imaging device in which a plurality of sensor cells each having a photoelectric conversion element are arranged,
A plurality of first common signal lines from which signals from the plurality of sensor cells are output;
A plurality of hold capacitors respectively holding signals from the plurality of first common signal lines;
A plurality of transfer switches for transferring signals appearing on the plurality of first common signal lines to the plurality of hold capacitors;
After the plurality of transfer switches are turned on, the signals from the plurality of first common signal lines are held in the plurality of hold capacitors, respectively, and then the plurality of hold capacitors are turned off. A plurality of first switches for respectively transferring the signals of
A plurality of blocking regions connecting between the outputs of the plurality of first switches in a specific number unit;
A second common signal line;
A plurality of second switches for transferring the signals of the plurality of blocked regions to the second common signal line ;
Each of the first switches in the plurality of first switches has a block area in which the first switch is connected among the plurality of block areas corresponding to the block area in the plurality of second switches. A period not connected to the second shared signal line by two switches is not turned on,
A solid-state imaging device.   The solid-state imaging device according to claim 1, further comprising a capacitive feedback amplifier that amplifies a signal appearing on the second common signal line. The capacitive feedback amplifier is
A differential amplifier having an input terminal connected to the second common signal line;
A feedback capacitor connected between the input terminal and the output terminal of the differential amplifier;
The solid-state imaging device according to claim 2, comprising:   4. The scanning circuit according to claim 1, further comprising a scanning circuit that controls the plurality of first switches and the plurality of second switches so that signals of the plurality of sensor cells are read in a specific order. The solid-state imaging device according to any one of the above. The first switch for the sensor cell after the second switch connected to the blocked area for the sensor cell for signal readout is turned on to reset the blocked area and the second common signal line 5. The driving circuit according to claim 1, further comprising: a drive circuit that controls a reset operation and a signal read operation so that the signal of the sensor cell is read by turning on the signal. Solid-state imaging device.   The solid-state imaging device according to claim 1, further comprising a clamp circuit that clamps a signal from the sensor cell between the first switch and the sensor cell. A solid-state imaging device in which a plurality of sensor cells each having a photoelectric conversion element are arranged two-dimensionally in a horizontal direction and a vertical direction,
A first portion that outputs signals of odd-numbered sensor cells in the array of sensor cells; and a second portion that outputs signals of even-numbered sensor cells in the array of sensor cells, and The portion is disposed on one side of the array of the plurality of sensor cells, and the second portion is disposed on the other side of the array of the plurality of sensor cells.
The first part and the second part are respectively
A plurality of first common signal lines from which signals from the plurality of sensor cells are output;
A plurality of hold capacitors respectively holding signals from the plurality of first common signal lines;
A plurality of transfer switches for transferring signals appearing on the plurality of first common signal lines to the plurality of hold capacitors;
After the plurality of transfer switches are turned on, the signals from the plurality of first common signal lines are held in the plurality of hold capacitors, respectively, and then the plurality of hold capacitors are turned off. A plurality of first switches for respectively transferring the signals of
A plurality of blocking regions connecting between the outputs of the plurality of first switches in a specific number unit;
A second common signal line;
A plurality of second switches for transferring the signals of the plurality of blocked regions to the second common signal line ;
Each of the first switches in the plurality of first switches has a block area in which the first switch is connected among the plurality of block areas corresponding to the block area in the plurality of second switches. A period not connected to the second shared signal line by two switches is not turned on,
A solid-state imaging device. Each of the first portion and the second portion further includes a capacitive feedback amplifier that amplifies a signal appearing on the second common signal line.
The solid-state imaging device according to claim 7. The capacitive feedback amplifier is
A differential amplifier having an input terminal connected to the second common signal line;
A feedback capacitor connected between the input terminal and the output terminal of the differential amplifier;
The solid-state imaging device according to claim 8, comprising: The first portion further includes a scanning circuit that controls the plurality of first switches and the plurality of second switches in the first portion so that signals of the sensor cells in the odd-numbered columns are read in a specific order. Prepared,
The second portion further includes a scanning circuit that controls the plurality of first switches and the plurality of second switches in the second portion so that signals of the sensor cells in the even-numbered columns are read in a specific order. Prepare
The solid-state imaging device according to claim 7, wherein the solid-state imaging device is provided. Each of the first part and the second part turns on the second switch connected to the blocked area for the sensor cell from which a signal is to be read, and the second shared communication with the blocked area. A reset circuit and a drive circuit for controlling the signal read operation so as to read the signal of the sensor cell by turning on the first switch for the sensor cell after resetting the signal line;
The solid-state imaging device according to claim 7, wherein the solid-state imaging device is provided. The said 1st part and the said 2nd part are further equipped with the clamp circuit which clamps the signal from the said sensor cell between the said 1st switch and the said sensor cell, respectively. Solid-state imaging device. A solid-state imaging device according to any one of claims 1 to 12 ,
A processor for processing an image captured by the solid-state imaging device;
A camera comprising: A solid-state imaging device according to any one of claims 1 to 12 ,
A processor for processing an image captured by the solid-state imaging device;
An information processing apparatus comprising:

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