JP3179078B2 - Photoelectric conversion device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device comprising a plurality of photoelectric conversion elements arranged in a predetermined direction as one line via a switch transistor having a switch function. The present invention relates to a photoelectric conversion device having a plurality of holding units that respectively hold the signals.

[Prior Art and Problems to be Solved by the Invention] Conventionally, in a photoelectric conversion device such as a line sensor or an area sensor, pixel signals from n horizontal pixels of a photoelectric conversion element in which a plurality of photoelectric conversion cells are arranged are For n switches
It was transferred as an output signal through a MOS transistor. In this case, the parasitic capacitance of the output signal line is almost n times the drain capacitance of one switching MOS transistor.

Therefore, when the number of pixels increases, the signal level decreases due to the capacity division of the signal component in the readout.

In addition, the increase in the number of pixels narrows the pixel pitch,
It has become difficult to provide a plurality of switching MOS transistors and temporary storage capacitors for storing output signals at the pixel pitch.

[Means for Solving the Problems] A photoelectric conversion device of the present invention includes a plurality of photoelectric conversion elements each holding signals from a plurality of photoelectric conversion elements arranged in a predetermined direction as one line via a switch transistor having a switching function. A holding unit, a common output line to which signals from the plurality of holding units are transferred, and a plurality of transfer transistors for transferring signals from the plurality of holding units to the common output line, Each of the plurality of transfer transistors is provided for two or more of the holding units, and after the signal is held in the plurality of holding units, from one transfer transistor to the two or more of the holding units. Are sequentially read out to the common output line, and then the signals from the other two or more holding units are sequentially read out to the common output line from another transfer transistor. And wherein the door.

[Operation] According to the present invention, signals are sequentially read out to a common output line by a transfer transistor provided for each of two or more holding units that respectively hold signals from the photoelectric conversion elements, so that a signal to the common output line is output. This is to prevent a signal level from being reduced due to capacitance division of a signal component in signal reading and obtain a large signal.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the photoelectric conversion device of the present invention.

In the present embodiment, the present invention is applied to a line sensor as shown in the figure. One common signal line is provided for two pixels, and the number of transfer MOS transistors is halved. . Therefore, the parasitic capacitance of the output signal line becomes about 1/2, and the output signal level becomes about twice.

 Hereinafter, the circuit configuration will be described.

In the figure, photoelectric conversion elements S1 to S4 (the number of elements is shown only four for simplicity of description) have a bipolar transistor configuration, and the photoelectrically converted charge is stored in the base region. MOS transistors TR1 to TR4 controlled by a signal φV RF are connected to the base, and the base potential can be set by ON / OFF control of the MOS transistors TR1 to TR4.

As described above, in this embodiment, one common signal line is provided for two pixels of the photoelectric conversion element to perform signal transfer.
Since the transfer operations of the photoelectric conversion elements S1, S2 and the photoelectric conversion elements S3, S4 are the same, only the transfer operation of the photoelectric conversion elements S1, S2 will be described, and the transfer operation of the photoelectric conversion elements S3, S4 will be described. The illustration of the wiring section is omitted.

The emitters of the photoelectric conversion elements S1 and S2 are connected to signal lines L1 and L2. These signal lines L1 and L2 are connected to a common signal line H1 via MOS transistors TS1 and TS2 controlled by signals φT1 and φT2.
And a plurality of capacitors C1 and C2 as storage means are connected to the common signal line H1. Outputs from the photoelectric conversion elements S1 and S2 are stored in capacitors C1 and C2, respectively.

The other terminals of the capacitors C1 and C2 have MOS transistors Tr1 and Tr2 controlled by signals φC1 and φC2, respectively.
Is connected, and the potential can be set to GND. The common signal line H1 is connected to an output signal line SL via a MOS transistor TH1 controlled by a shift register. The signal output to the output signal line SL is amplified and output signal vs.
Is output as The output signal line SL is cleared by the MOS transistor THC controlled by the signal φHC, the signal lines L1 and L2 are refreshed by the MOS transistors TC1 and TC2 controlled by the signal φVC, and the common signal line
H1 is a MOS transistor TCR controlled by a signal φCR.
Refreshed by

FIG. 2 is a timing chart for explaining the operation of the photoelectric conversion device.

In the figure, a period T1 is a period during which the charge of the capacitor C1 is removed, and when the signal φCR and the signal φC1 become a high level, the MOS transistors TCR and T1 become conductive and are accumulated in the common signal line H1 and the capacitor C1. The charged electric charge is removed, and the potentials on both sides of the capacitor C1 become GND.

The next period T1a is a period for transferring the signal charge to the capacitor C1, and the signal φC1 continues to be at the high level. Signal φ
When T1 goes high, the MOS transistor TS1 becomes conductive, and the output signal of the photoelectric conversion element S1 is output to the signal line L1.
And stored in the capacitor C1 through the common signal line H1.

Thereafter, when the signal φC1 and the signal φT1 become low level, the MOS transistor Tr1 and the MOS transistor Ts1 are cut off, the MOS transistor Tr1 connection side of the capacitor C1 becomes a floating state, and the common signal line H1 and the photoelectric conversion element S1 are turned off. Is shut off.

The next period T2 is a period for removing the charge of the capacitor C2,
When the signal φCR and the signal φC2 go high, the MOS
The transistors TCR and Tr2 become conductive, and the common signal line
The charge stored in H1 and capacitor C2 is removed,
Both potentials on both sides of the capacitor C2 become GND. In this case, since one of the capacitors C1 is in a floating state, the signal charge of the photoelectric conversion element S1 stored in the capacitor C1 is held.

The next period T2a is a period for transferring the signal charge to the capacitor C2, and the signal φC2 continues to be at the high level. Signal φ
When T2 goes high, the MOS transistor TS1 becomes conductive and the output signal of the photoelectric conversion element S2 is accumulated in the capacitor C2 through the signal line L2 and the common signal line H1. Also at this time, since one of the capacitors C1 is in a floating state, the signal charges stored in the capacitor C1 remain held.

After that, when the signal φC2 and the signal φT2 become low level, the MOS transistor Tr2 and the MOS transistor TS2 are cut off, the connection side of the MOS transistor Tr2 of the capacitor C2 becomes a floating state, and the common signal line H1 and the emitter of the photoelectric conversion element S2 are connected. Is shut off.

The next period T3 is a period for refreshing the charge remaining in the photoelectric conversion elements S1 and S2, and the signal φVC is set to a high level.
As the level, the MOS transistors TC1 and TC2 are turned on, and the emitters of the photoelectric conversion elements S1 and S2 are set to GND. Thereafter, when the signal φVRF is set to low level, the MOS transistors TR1 and TR2 are turned on, and the base is set to a predetermined potential (complete refresh).

Next, the signal φVC is set to the high level to turn on the MOS transistors TC1 and TC2, and the emitters of the photoelectric conversion elements S1 and S2 are set to GND (transient refresh).

The next period T4 is a period for reading the signal charges stored in the capacitors C1 and C2 and for storing the signal charges in the photoelectric conversion elements S1 and S2.In the period TS1, the signal φC1 and the signal φH1 are set to high level. When the level is set to the level, the MOS transistor Tr1 and the MOS transistor TH1 are set to the high level. As a result, capacitor C1
The MOS transistor connection side is connected to GND, and the capacitor C1
Is read out to the output signal line SL and output as an output vs11.

In the period TS1a, the signal φCR and the signal φHC are set to high level.
When the level is set to the level, the MOS transistor TCR and the MOS transistor THC are turned on, and the common signal line H1 and the output signal line SL are cleared.

Similarly, in the periods TS2 and TS2a, the signal charge accumulated in the capacitor C2 is read out to the output signal line SL, read out as the output vs12, and thereafter, the common signal line H
1 and the output signal line SL are cleared.

FIG. 3 is a circuit diagram showing a second embodiment of the photoelectric conversion device of the present invention.

In this embodiment, the present invention is applied to an area sensor.Three capacitors are connected to one common signal line, the number of transfer MOS transistors is reduced to 1/3, and the parasitic capacitance of the output signal line is reduced. To about 1/3. The functions of the three capacitors have already been disclosed in Japanese Patent Application No. 63-234944, which aims at correcting sensor noise and delaying a sensor signal for a certain period.

 Hereinafter, the circuit configuration will be described.

In the area sensor of the present embodiment, the photoelectric conversion elements constituting the area sensor are arranged in a matrix (n × m). The configuration of the area sensor according to the present embodiment will be described below with reference to FIG. 3, but for simplicity, the photoelectric conversion elements correspond to S11 and S12 in the first row of photoelectric conversion elements S11 to Sn1. Only the configuration and operation are performed.

As shown in FIG. 3, the first row of photoelectric conversion elements S11, S21
Are commonly connected to the signal line L1, and the signal line L1 is connected to the signals φT1 and φT.
2 are connected to the common signal lines H11 and H12 via the MOS transistors T11 and T12 controlled by the control circuit 2. The common signal lines H11 and H12 are cleared by the MOS transistor TC1 controlled by the signal φVVC. The bases of the photoelectric conversion elements S11 and S12 are MOS transistors TS11 and TS controlled by a signal φVR1.
It is possible to set to a predetermined potential by setting 12. The bases of the photoelectric conversion elements S21 and S22 can be set to a predetermined potential by MOS transistors TS21 and TS22 controlled by a signal φVR2.

The common signal line H11 has three capacitors C as storage means.
11a, C12a, and C13a are connected.

The common signal line H12 has three capacitors C as storage means.
11b, C12b, and C13b are connected.

MOS transistors T11a, T12a, T13a controlled by signals φC1, φC2, φC3 are connected to the other terminals of the capacitors C11a, C12a, C13a, respectively, and can be connected to GND, and the capacitors C11b, C12b , C13b are connected to MOS transistors T11b, T12b, T13b controlled by signals φC1, φC2, and φC3, respectively.
Connectable to ND.

The common signal line H11 is connected to the output signal line SL1 via a MOS transistor THa by a shift register, and the common signal line H12 is connected to the output signal line SL2 via a MOS transistor THb controlled by the shift register.

The signals output to the output signal lines SL1 and SL2 are amplified and output from the output out1 or the output out2. Output signal line SL
1 and output signal line SL2 are MOS controlled by signal φHC
Cleared by transistors THC1 and THC2.

FIG. 4 is an explanatory diagram for explaining the operation of the photoelectric conversion device, and FIG. 5 is a timing chart of the photoelectric conversion device.

In this embodiment, of the three capacitors, two capacitors are used for delaying the accumulation of the sensor signal and for a certain period, and one capacitor is used for accumulating the noise signal.

As shown in FIG. 4, first, a period T of the horizontal scanning period fH1 is set.
At t, the capacitors C11a and C11b are connected to the photoelectric conversion elements S11 and S21.
The signal charge is transferred from and stored. The stored signal charges (S11 and S21 in the figure) are temporarily stored for a period Tm (one cycle fH).

Next, during the horizontal scanning period fH2 during the period Tt, noise signals from the photoelectric conversion elements S11 and S21 are supplied to the capacitors C13a and C13b (in FIG.
N11, N21). In the period Tr, this noise signal and the signal charges stored in the capacitors C11a and C11b in the period Tr are read out to the output signal line. By performing a difference process on the two signals that have been read, a signal that does not include a noise component can be obtained.

In the period Tt, signal charges are sent from the photoelectric conversion elements S31 and S41 to the capacitors C12a and C12b and accumulated. The stored signal charges (S31 and S41 in the figure) are temporarily stored for a period Tm (one cycle fH).

Next, in the period Tt of the horizontal scanning period fH3, the noise signals from the photoelectric conversion elements S31 and S41 are supplied to the capacitors C13a and C13b (in FIG.
N31, N41). In the period Tr, the noise signal and the signal charges accumulated in the capacitors C12a and C12b in the period Tr are read out to the output signal line. By performing a difference process on the two signals that have been read, a signal that does not include a noise component can be obtained.

In the period Tt, signal charges are sent from the photoelectric conversion elements S51 and S61 to the capacitors C11a and C11b and accumulated. The stored signal charges (S51 and S61 in the figure) are temporarily stored for a period Tm (one cycle fH).

Thereafter, the same operation is repeated to read out a signal containing no noise component.

Hereinafter, a more detailed description will be given with reference to the timing chart of FIG.

In FIG. 5, during a period TC1, signals φVVC, φT1, φ
T2, φCR, φC1 are set to the high level, MOS transistors TC1, T11, T12, TCRa, TCRb, T11a, T11b are set to the conductive state, and the signal line L1, the common signal lines H11, H12, and the capacitor C11 are set.
Clear a, C11b.

Next, in the period Tt1, the signals φVR1, φT1, and φC1 are set to the high level, the MOS transistors TS11, T11, and T11a are turned on, and the signal from the photoelectric conversion element S11 is transferred and accumulated in the capacitor C11a.

Next, in the period TC1a, the signals φVVC and φT2 are set to the high level, the MOS transistors TC1 and T12 are turned on, and the signal line L1 and the common signal line H12 are cleared.

Next, in the period Tt1a, the signals φVR2, φT2, and φC1 are set to the high level, the MOS transistors TS21, T12, and T11b are turned on, and the signal from the photoelectric conversion element S21 is transferred to the capacitor C11b and accumulated.

Next, in the period Tm1, the signal charges accumulated in the capacitors C11a and C11b in the period TC1 to the period Tt1a maintain a preserved state. In the period Tr1, the signal charges accumulated and stored in the capacitors C12a and C12b before the period TC1 and
The noise charges stored in the capacitors C13a and C13b are read. That is, first, the signal φCR is set to the high level to clear the common signal lines H11, H12, and then the signals φC3, φH1 are set to the high level, and the MOS transistors T13a, T13b, THa, THb
Into the conductive state, and connect the capacitor C13 to the output signal lines SL1 and SL2.
a, Read the noise charge stored in C13b. Next, the signal φ
Clear the common signal lines H11 and H12 by setting CR to high level,
Thereafter, the signals φC2 and φH1 are set to the high level, the MOS transistors T12a, T12b, THa, and THb are turned on, and the output signal line S
The signal charges stored in the capacitors C12a and C12b are read out to L1 and SL2. Hereinafter, similarly, noise charges and signal charges are read from other capacitors (not shown).

The sensors connected to the horizontal scanning lines forming the matrix perform the above-described complete refresh.

Next, in the period TC2, the signals φVR1, φVVC, φT1, φT2,
φCR and φC3 are set to high level, and MOS transistor TS1
1, TC1, T11, T12, TCRa, TCRb, T13a, T13b are turned on to clear the signal line L1, the common signal lines H11, H12, the capacitors C13a, C13b, and perform the above-described transient refresh of the photoelectric conversion element S11. Do.

Next, in the period Tt2, the signals φVR1, φT1, and φC3 are set to the high level, the MOS transistors TS11, T11, and T13a are turned on, and the noise signal from the photoelectric conversion element S11 is transferred and accumulated in the capacitor C13a.

Next, in the period TC2a, the signals φVR2, φVVC, and φT2 are set to the high level, the MOS transistors TS21, TC1, and T12 are turned on, the signal line L1 and the common signal line H12 are cleared, and the above-described transient refresh of the photoelectric conversion element S12 is performed. Perform

Next, in the period Tt2a, the signals φVR2, φT2, and φC3 are set to the high level, the MOS transistors TS21, T12, and T13b are turned on, and the noise signal from the photoelectric conversion element S21 is transferred and accumulated in the capacitor C13b.

Next, in the period TC1 to the period Tt1a, the above period TC1 to the period Tt1a
With the same operation as described above, the signal from the photoelectric conversion element (not shown) is transferred and stored in the capacitors C12a and C12b. In the next period Tm, the stored signal charges are in a storage state.

In the period Tr, the signal charges accumulated and stored in the above-described period TC1 to period Tt1a are combined with the signal charges in the above-described period T1.
Reading is performed with the noise charges accumulated in the period from C2 to Tt2a. This operation is the same as the operation in the above-described period Tr.

[Effects of the Invention] As described in detail above, according to the photoelectric conversion element of the present invention, each of the two holding signals from the photoelectric conversion element
By sequentially reading out signals to the common output line by one transfer transistor provided for one or more holding units, the parasitic capacitance of the common output line can be reduced, so that a large output signal can be obtained. Become. Further, the circuit configuration of the reading system can be simplified.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the photoelectric conversion device of the present invention. FIG. 2 is a timing chart for explaining the operation of the photoelectric conversion device. FIG. 3 is a circuit diagram showing a second embodiment of the photoelectric conversion device of the present invention. FIG. 4 is an explanatory diagram for explaining the operation of the photoelectric conversion device. FIG. 5 is a timing chart of the photoelectric conversion device. S1, S2, S11 to S21: photoelectric conversion element, L1, L2: signal line, φT1,
φT2, φC1, φC2, φC3, φHC, φVC, φCR, φV VC, φVR1, φ
VR2: signal, T11, T12, TS1, TS2, Tr1, Tr2, TH1, THC, THC1, THC
2, TC1, TC2, TCR, TC1, TS11, TS12, TS21, TS22, T11a, T12a, T1
3a, T11b, T12b, T13b, THa, THb: MOS transistors, H11, H1
2, H1: Common signal line, C1, C2, C11a, C12a, C13a, C11b, C12b, C1
3b: capacitor, SL, SL1, SL2: output signal line, vs: output signal, L1: signal line.

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 1/024-1/036 H04N 5/335

Claims (3)

(57) [Claims] 1. A plurality of holding units each holding a signal from a plurality of photoelectric conversion elements arranged in a predetermined direction as one line via a switch transistor having a switching function, and a signal from the plurality of holding units. And a plurality of transfer transistors for transferring signals from the plurality of holding units to the common output line. Each of the plurality of transfer transistors has two or more transfer transistors. One is provided for the holding unit, and after the signal is held in the plurality of holding units, signals from two or more of the holding units are sequentially read out from one transfer transistor to the common output line, Thereafter, the photoelectric conversion device sequentially reads signals from the other two or more holding units from another transfer transistor to the common output line. 2. The photoelectric conversion device according to claim 1, wherein
The photoelectric conversion device, wherein each of the plurality of photoelectric conversion elements includes an amplification transistor that amplifies and outputs a photoelectrically converted signal. 3. The photoelectric conversion device according to claim 2, wherein
A photoelectric conversion device, wherein each of the plurality of photoelectric conversion elements includes a reset transistor for supplying a reset potential to a control electrode region of the amplification transistor.