JP5081303B2 - ディジタル電力制御システム用フィルタ補償係数を最適化する方法およびシステム - Google Patents
ディジタル電力制御システム用フィルタ補償係数を最適化する方法およびシステム Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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Description
本特許出願は、2004年7月12日に出願され、2007年7月24日に米国特許第7,249,267号として発行された米国特許出願第10/889,806号に対する、35U.S.C.§120に基づく一部継続としての優先権を主張する。米国特許出願第10/889,806号は、2004年2月12日に出願された米国仮特許出願第60/544,553号に対する、35U.S.C.§119(c)に基づく優先権を主張し、更に、2003年2月10日に出願された米国特許出願第10/361,667号および2002年12月21に出願された米国特許出願第10/326,222号の、35U.S.C.§120に基づく一部継続としての優先権も主張した。
発明の分野
本発明は、電力供給回路に関し、更に特定すれば、モード切換型電力供給回路のフィルタ補償係数を最適化しプログラミングするディジタル電力制御システムおよび方法に関する。
図1は、本発明の一実施形態によるディジタル制御回路を有するモード切換電源10の一例を図示する。電源10は、バック・コンバータ・トポロジを備えており、入力DC電圧Vinを出力DC電圧Voに変換する。出力DC電圧Voは、抵抗性負荷20(Rload)に印加される。電源10は、MOSFETデバイスによって構成された1対の電力スイッチ12、14を含む。ハイ側の電力スイッチ12のドレイン端子は入力電圧Vinに結合されており、ロー側電力スイッチ14のソース端子は接地に接続されており、ハイ側電力スイッチ12のソース端子およびロー側電力スイッチ14のドレイン端子は一緒に結合されて、位相ノードを定める。出力インダクタ16が、位相ノードと、出力電圧V0を供給する端子との間に直列に結合されており、キャパシタ18が抵抗性負荷Rloadと並列に結合されている。それぞれのドライバ22、24は、電力スイッチ12、14のゲート端子を交互に駆動する。一方、ドライバ22、24は、ディジタル制御回路(以下で説明する)によって制御される。電力スイッチ12、14の開閉によって、概略的に矩形波形を有する中間電圧が位相ノードに供給され、出力インダクタ16およびキャパシタ18によって形成されたフィルタが、この矩形波形を実質的なDC出力電圧Voに変換する。
システム・コントローラ102は、図4において同期/データ・バスとして示されている単一方向または双方向シリアル・バスを通じてディジタル・データを書き込むおよび/または読み出す(同期してまたは非同期でのいずれかで)ことによって、複数のPOLレギュレータと通信する。同期/データ・バスは、非同期でデータを送信することができる二線シリアル・バス(例えば、I2C)、または同期してデータを送信することができる(即ち、クロック信号に同期して)単線シリアル・バスを備えることができる。アレイの中にある任意の特定POLにアドレスするために、各POLは一意のアドレスで特定され、アドレスはPOLにハードワイヤ接続(hardwired)またはその他の方法によって設定することができる。例えば、システム・コントローラ102は、データを同期/データ・バスを通じて伝達し、各POLレギュレータのディジタル・フィルタ伝達関数G(z)の係数をプログラミングする。また、システム・コントローラ102は、障害管理のために、図4においてOK/障害バスとして示されている第2の単一方向または双方向シリアル・バスを通じて複数のPOLレギュレータと通信する。複数のPOLレギュレータを共通のOK/障害バスに接続することによってこれらを一緒に集合化することにより、障害状態の場合、これらのPOLレギュレータが同じ挙動を有することができることになる。また、システム・コントローラ102は、POL制御システム10のプログラミング、設定、および監視のために、ユーザ・インターフェース・バスを通じてユーザ・システムと通信する。最後に、システム・コントローラ102は、フロント・エンド・レギュレータの動作をディスエーブルするために、別個の線を通じてフロント・エンド・レギュレータ104と通信する。
注入されるノイズ信号は疑似白色ノイズであるので、相互相関関数rueは測定される系のインパルス応答に対応する。
k=1・・・N/2に対して、
Claims (19)
- 電力制御システムであって、
少なくとも1つの負荷点(POL)レギュレータであって、電力を負荷に伝えるように構成されている電力変換回路と、フィードバック・ループを通じて前記電力変換回路に結合されたディジタル・コントローラとを有し、前記ディジタル・コントローラは、前記電力変換回路の出力からのフィードバック測定値に応答して、パルス幅変調制御信号を前記電力変換回路に供給するように構成されており、前記ディジタル・コントローラは、更に、複数のフィルタ係数によって定められた伝達関数を有するディジタル・フィルタを含み、前記ディジタル・コントローラが周期的に前記フィードバック測定値の複数のサンプルのうち連続するものを格納する、少なくとも1つの負荷点レギュレータと、
前記少なくとも1つのPOLレギュレータに動作的に接続されたシリアル・データ・バスと、
前記シリアル・データ・バスに接続されており、前記シリアル・データ・バスを通じて前記少なくとも1つのPOLレギュレータと通信するように構成されたシステム・コントローラであって、連続する格納されたサンプルの各々を、前記ディジタル・コントローラから前記シリアル・データ・バスを通じて取り出す、システム・コントローラと、
を備えており、所定数の前記サンプルを取り出した後、前記システム・コントローラは、前記サンプルの少なくとも一部を用いて前記ディジタル・フィルタについて最適化したフィルタ係数を計算し、該最適化したフィルタ係数を前記ディジタル・コントローラに前記シリアル・データ・バスを通じて伝達し、前記ディジタル・コントローラは、その後、前記ディジタル・フィルタ内において前記最適化したフィルタ係数を用い、
前記ディジタル・コントローラは、更に、対称形ノイズ信号を前記パルス幅変調制御信号に周期的に注入するように構成されたノイズ源を含む、電力制御システム。 - 請求項1記載の電力制御システムにおいて、前記対称形ノイズ信号は、更に、疑似ランダム二進シーケンスを含む、電力制御システム。
- 請求項2記載の電力制御システムにおいて、前記所定数のサンプルは、前記疑似ランダム二進シーケンスのシーケンス長に対応する、電力制御システム。
- 請求項1記載の電力制御システムにおいて、前記ディジタル・コントローラは、更に、前記フィードバック測定値の連続したサンプルを格納するように構成されたレジスタを含む、電力制御システム。
- 請求項1記載の電力制御システムにおいて、前記システム・コントローラは、前記ディジタル・コントローラから取り出したサンプルを格納するように構成されたメモリ・アレイを含む、電力制御システム。
- 請求項1記載の電力制御システムにおいて、前記システム・コントローラは、前記ディジタル・コントローラから取り出したサンプルに基づいて、前記フィードバック・ループの開ループ伝達関数を計算するように構成された、電力制御システム。
- 請求項1記載の電力制御システムにおいて、前記システム・コントローラは、前記ディジタル・コントローラから取り出したサンプルに基づいて、前記電力変換回路の伝達関数を計算するように構成された、電力制御システム。
- 請求項6記載の電力制御システムにおいて、前記システム・コントローラは、前記フィードバック・ループの前記開ループ伝達関数に基づいて、前記最適化したフィルタ係数を計算する、電力制御システム。
- 請求項7記載の電力制御システムにおいて、前記システム・コントローラは、前記電力変換回路の前記伝達関数に基づいて、前記最適化したフィルタ係数を計算する、電力制御システム。
- 請求項1記載の電力制御システムにおいて、前記ディジタル・コントローラは、更に、 前記電力変換回路の出力と基準との間の差を表すディジタル誤差信号を供給するアナログ/ディジタル変換器であって、前記ディジタル誤差信号が前記フィードバック測定値を供給する、アナログ/ディジタル変換器と、
前記パルス幅変調制御信号を供給するディジタル・パルス幅変調器と、
を含む、電力制御システム。 - 請求項1記載の電力制御システムにおいて、前記ディジタル・コントローラは、更に、 前記電力変換回路の出力の絶対ディジタル表現を供給するアナログ/ディジタル変換器と、前記ディジタル出力表現とディジタル基準との間の差を表すディジタル誤差信号を発生するディジタル減算器であって、前記ディジタル誤差信号が前記フィードバック測定値を供給する、ディジタル減算器と、
前記パルス幅変調制御信号を供給するディジタル・パルス幅変調器と、
を含む、電力制御システム。 - 請求項1記載の電力制御システムにおいて、前記ディジタル・フィルタは、更に、無限インパルス応答フィルタを含む、電力制御システム。
- 請求項1記載の電力制御システムにおいて、前記電力変換回路は、更に、少なくとも1つの電力スイッチを含む、電力制御システム。
- 共通データ・バスを通じてシステム・コントローラに結合された少なくとも1つの負荷点(POL)レギュレータの制御方法であって、前記少なくとも1つのPOLレギュレータは、負荷に電力を伝えるように構成された電力変換回路と、フィードバック・ループにおいて前記電力変換回路に結合されたディジタル・コントローラとを有し、前記ディジタル・コントローラは、電圧誤差測定値に応答して、パルス幅変調制御信号を前記電力変換回路に供給するように構成されており、前記ディジタル・コントローラは、更に、複数のフィルタ係数によって定められた伝達関数を有するディジタル・フィルタを含み、前記方法は、
対称形ノイズ信号を前記パルス幅変調制御信号に所定の時間期間注入するステップと、 前記ノイズ信号が静定することができる十分な時間の後、前記電圧誤差測定値のサンプルを格納するステップと、
前記サンプルを前記システム・コントローラに前記共通データ・バスを通じて送信するステップと、
前記ノイズ信号の特性に対応する所定の回数、前記の注入するステップ、格納するステップ、および送信するステップを繰り返すステップと、
前記サンプルのうち複数のものに基づいて、前記フィードバック・ループの伝達関数を計算するステップと、
計算した前記フィードバック・ループの伝達関数に基づいて、最適なフィルタ係数を計算するステップと、
前記最適なフィルタ係数を前記少なくとも1つのPOLレギュレータに前記共通データ・バスを通じて送信するステップと、
前記最適なフィルタ係数を用いて、前記ディジタル・フィルタをプログラミングするステップと、
を含む、方法。 - 請求項15記載の方法において、前記注入するステップは、更に、疑似ランダム二進シーケンス信号を前記パルス幅変調制御信号に注入することを含む、方法。
- 請求項16記載の方法において、前記繰り返すステップは、更に、前記疑似ランダム二進シーケンスのシーケンス長に対応する回数、前記の注入するステップ、格納するステップ、および送信するステップを繰り返すことを含む、方法。
- 請求項15記載の方法において、前記伝達関数を計算するステップは、更に、前記サンプルをノイズ信号と相互相関させ、フーリエ変換を用いて、前記相互相関の結果を周波数ドメインに変換することを含む、方法。
- 請求項15記載の方法であって、更に、前記サンプルのうち複数のものに基づいて、前記電力変換回路の伝達関数を計算するステップを含む、方法。
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US11/781,878 | 2007-07-23 | ||
US11/781,878 US7743266B2 (en) | 2002-12-21 | 2007-07-23 | Method and system for optimizing filter compensation coefficients for a digital power control system |
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-
2007
- 2007-07-23 US US11/781,878 patent/US7743266B2/en not_active Expired - Lifetime
-
2008
- 2008-07-16 WO PCT/US2008/070117 patent/WO2009014946A1/en active Search and Examination
- 2008-07-16 AU AU2008279400A patent/AU2008279400B2/en active Active
- 2008-07-16 EP EP08781877.9A patent/EP2183656B1/en active Active
- 2008-07-16 CA CA2694295A patent/CA2694295C/en active Active
- 2008-07-16 KR KR1020107003932A patent/KR101143133B1/ko active IP Right Grant
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- 2008-07-16 BR BRPI0814583-0A2A patent/BRPI0814583A2/pt not_active Application Discontinuation
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Also Published As
Publication number | Publication date |
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JP2010534460A (ja) | 2010-11-04 |
US7743266B2 (en) | 2010-06-22 |
CN101861557B (zh) | 2013-02-13 |
CA2694295A1 (en) | 2009-01-29 |
EP2183656A1 (en) | 2010-05-12 |
CA2694295C (en) | 2013-10-01 |
AU2008279400B2 (en) | 2011-11-03 |
AU2008279400A1 (en) | 2009-01-29 |
BRPI0814583A2 (pt) | 2015-01-20 |
CN101861557A (zh) | 2010-10-13 |
KR20100037157A (ko) | 2010-04-08 |
US20080010474A1 (en) | 2008-01-10 |
KR101143133B1 (ko) | 2012-05-08 |
EP2183656B1 (en) | 2015-04-01 |
EP2183656A4 (en) | 2011-12-14 |
WO2009014946A1 (en) | 2009-01-29 |
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