JP5076674B2 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JP5076674B2
JP5076674B2 JP2007167086A JP2007167086A JP5076674B2 JP 5076674 B2 JP5076674 B2 JP 5076674B2 JP 2007167086 A JP2007167086 A JP 2007167086A JP 2007167086 A JP2007167086 A JP 2007167086A JP 5076674 B2 JP5076674 B2 JP 5076674B2
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JP2009009959A (en
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千穂子 金田
隆浩 山崎
憲彦 高橋
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本発明は半導体装置の製造方法および半導体装置に関し、特に窒素を含むゲート絶縁膜を備える半導体装置の製造方法および半導体装置に関する。   The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a gate insulating film containing nitrogen and the semiconductor device.

ＬＳＩ（Large Scale Integrated-circuit）などの半導体集積回路の高速化、微細化、低消費電力化は、近年、顕著に進展している。半導体集積回路に用いられる素子のＭＯＳトランジスタ（MOSFET：Metal-Oxide Semiconductor Field Effect Transistor）に関しても同様に特性が向上している。   In recent years, semiconductor integrated circuits such as LSI (Large Scale Integrated-circuit) have been remarkably improved in speed, miniaturization, and low power consumption. The characteristics of MOS transistors (MOSFETs: Metal-Oxide Semiconductor Field Effect Transistors) used in semiconductor integrated circuits are also improved.

図５は、ＭＯＳＦＥＴの要部断面模式図である。
図５は、一般的なＭＯＳＦＥＴの、基板１０１上のゲート部１０２を拡大した断面模式図であって、基板１０１上に、酸化シリコン（ＳｉＯ2）が用いられたゲート絶縁膜１０３を介して形成されたゲート電極１０４から構成されるゲート部１０２が形成されている。また、ＭＯＳＦＥＴが微細化されると、図５（Ａ）から図５（Ｂ）に示すように、スケーリング則に従い、ＭＯＳＦＥＴの高さ方向と横方向のサイズを同時に縮小するとともに、素子の特性を正常に保ちながら、絶縁膜容量を向上させるなどの性能の向上がなされてきた。 FIG. 5 is a schematic cross-sectional view of the main part of the MOSFET.
FIG. 5 is a schematic cross-sectional view of a general MOSFET in which the gate portion 102 on the substrate 101 is enlarged, and is formed on the substrate 101 via a gate insulating film 103 using silicon oxide (SiO 2 ). A gate portion 102 composed of the gate electrode 104 thus formed is formed. When the MOSFET is miniaturized, as shown in FIGS. 5A to 5B, according to the scaling law, the height and lateral sizes of the MOSFET are simultaneously reduced, and the device characteristics are reduced. While maintaining normality, performance has been improved, such as improving the insulating film capacity.

しかし、ＭＯＳＦＥＴを微細化し、ゲート絶縁膜１０３が薄膜化されると、ゲート絶縁膜１０３を透過するトンネル電流１０５が発生し、また、ゲート部１０２の製造中に混入した水素（Ｈ2）やウェルの導入ためにドープされたボロン（Ｂ）などの不純物が、ゲート部１０２からチャネル部へ侵入する。この結果、チャネルを流れる電流の制御ができなくなって、リーク電流が増加し、また、ドレイン電流の漏洩や消費電力の増加などが生じる（例えば、特許文献１参照）。 However, when the MOSFET is miniaturized and the gate insulating film 103 is thinned, a tunnel current 105 that passes through the gate insulating film 103 is generated, and hydrogen (H 2 ) and wells mixed during the manufacture of the gate portion 102 are generated. Impurities such as boron (B) doped to introduce hydrogen penetrate from the gate portion 102 into the channel portion. As a result, the current flowing through the channel cannot be controlled, the leakage current increases, the drain current leaks, the power consumption increases, and the like (see, for example, Patent Document 1).

上述のような、ゲート絶縁膜１０３の薄膜化によるＭＯＳＦＥＴの特性低下を防ぐために、ゲート絶縁膜１０３に、ＳｉＯ2よりも高い誘電率の材料の適用が検討された。その１つの例として、ＳｉＯ2で構成されるゲート絶縁膜１０３を、一酸化窒素（ＮＯ）や二酸化窒素（ＮＯ2）などの窒素（Ｎ）を含むガスで窒化して、ゲート絶縁膜１０３上部に酸窒化（ＳｉＯＮ）膜を形成する方法が提案された。このような方法であれば、Ｎの濃度に依存して誘電率を変化させることができるようになる。また、シリコン（Ｓｉ）結晶表面とＮとの結合についての科学的な研究も行われている（例えば、非特許文献１参照）。 In order to prevent the deterioration of the MOSFET characteristics due to the thinning of the gate insulating film 103 as described above, the application of a material having a dielectric constant higher than that of SiO 2 to the gate insulating film 103 has been studied. As one example, the gate insulating film 103 made of SiO 2 is nitrided with a gas containing nitrogen (N) such as nitrogen monoxide (NO) or nitrogen dioxide (NO 2 ) to form an upper portion of the gate insulating film 103. A method of forming an oxynitride (SiON) film has been proposed. With such a method, the dielectric constant can be changed depending on the concentration of N. In addition, scientific research on the bond between the silicon (Si) crystal surface and N has been conducted (for example, see Non-Patent Document 1).

このように、ゲート絶縁膜１０３を窒化した酸窒化膜を適用することで、トンネル電流１０５が流れず、不純物が侵入しない程度にゲート絶縁膜１０３の膜厚を維持でき、高い絶縁膜容量を確保することができる。今後、さらに微細化が進み、ゲート絶縁膜の膜厚が１ｎｍ近くまで薄膜化されれば、従来よりも多量のＮによって窒化することにより、ゲート絶縁膜の誘電率を向上させ、膜厚を維持させることができると予想される。
特開２００６−０１９６１５号公報 モリタ（Y. Morita）、トクモト（H. Tokumoto）、「Origin of the 8/3×8/3 superstructure in STM images of the Si(111)-8×8:N surface」、サーフェスサイエンス（Surface Science）、４４４、１９９９年、Ｌ１０３７−Ｌ１０４２ As described above, by applying the oxynitride film obtained by nitriding the gate insulating film 103, the gate current 105 can be maintained at a thickness so that the tunnel current 105 does not flow and impurities do not enter, and a high insulating film capacity is ensured. can do. In the future, if the miniaturization progresses further and the film thickness of the gate insulating film is reduced to near 1 nm, the dielectric constant of the gate insulating film is improved and the film thickness is maintained by nitriding with a larger amount of N than before. It is expected that
JP 2006-019615 A Morita (Y. Morita), H. Tokumoto (Origin of the 8/3 × 8/3 superstructure in STM images of the Si (111) -8 × 8: N surface), Surface Science 444, 1999, L1037-L1042

しかし、ＳｉＯ2のゲート絶縁膜が窒化されると、Ｎの制御が難しくなり、ゲート絶縁膜に電荷捕獲中心や界面準位が生じ、ＭＯＳＦＥＴの特性が低下するという問題点があった。 However, when the gate insulating film of SiO 2 is nitrided, it becomes difficult to control N, and there is a problem in that charge trap centers and interface states are generated in the gate insulating film and the characteristics of the MOSFET deteriorate.

本発明はこのような点に鑑みてなされたものであり、不純物の侵入やリーク電流の発生を抑制でき、信頼性が向上された半導体装置の製造方法および半導体装置を提供することを目的とする。   The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device that can suppress the intrusion of impurities and the occurrence of a leakage current and have improved reliability. .

本発明では上記課題を解決するために、窒素を含むゲート絶縁膜１５を備える半導体装置の製造方法において、図１に示すように、シリコン（１１１）基板１上にシリコン酸化膜２ａおよびシリコン窒化膜３ａを順に備える絶縁部１１と、シリコン（１１１）基板４上にシリコン窒化膜３ｂを備える絶縁部１２とを、シリコン窒化膜３ａおよびシリコン窒化膜３ｂを張り合わせて成るシリコン窒化膜３を介して、接合し、絶縁部１３を形成する工程と、絶縁部１３のシリコン（１１１）基板１を除去した絶縁部１３ａと、シリコン（１００）基板５上にシリコン酸化膜２ｂを備える絶縁部１４とを、シリコン酸化膜２ａおよびシリコン酸化膜２ｂを張り合わせて成るシリコン酸化膜２を介して、接合し、さらに、シリコン（１１１）基板４を除去して、シリコン（１００）基板５上にゲート絶縁膜１５を形成する工程と、を有することを特徴とする半導体装置の製造方法が提供される。   In the present invention, in order to solve the above problem, in a method of manufacturing a semiconductor device including a gate insulating film 15 containing nitrogen, as shown in FIG. 1, a silicon oxide film 2a and a silicon nitride film are formed on a silicon (111) substrate 1. The insulating part 11 having 3a in order and the insulating part 12 having the silicon nitride film 3b on the silicon (111) substrate 4 are bonded via the silicon nitride film 3 formed by bonding the silicon nitride film 3a and the silicon nitride film 3b. Bonding and forming an insulating part 13; an insulating part 13a from which the silicon (111) substrate 1 of the insulating part 13 is removed; and an insulating part 14 having a silicon oxide film 2b on the silicon (100) substrate 5; The silicon oxide film 2a and the silicon oxide film 2b are bonded to each other through the silicon oxide film 2 and the silicon (111) substrate 4 is bonded. And removed by, a method of manufacturing a semiconductor device, characterized in that it comprises a step of forming a gate insulating film 15 on a silicon (100) substrate 5 on, is provided.

このような半導体装置の製造方法によれば、シリコン（１１１）基板上にシリコン酸化膜およびシリコン窒化膜を順に備える絶縁部と、シリコン（１１１）基板上にシリコン窒化膜を備える絶縁部とを、シリコン窒化膜およびシリコン窒化膜を張り合わせて成るシリコン窒化膜を介して、接合し、絶縁部が形成され、絶縁部のシリコン（１１１）基板を除去した絶縁部と、シリコン（１００）基板上にシリコン酸化膜を備える絶縁部とを、シリコン酸化膜およびシリコン酸化膜を張り合わせて成るシリコン酸化膜を介して、接合し、さらに、シリコン（１１１）基板を除去して、シリコン（１００）基板上にゲート絶縁膜が形成されるようになる。   According to such a method for manufacturing a semiconductor device, an insulating portion including a silicon oxide film and a silicon nitride film in this order on a silicon (111) substrate, and an insulating portion including a silicon nitride film on the silicon (111) substrate, The silicon nitride film and the silicon nitride film formed by bonding the silicon nitride films are joined to form an insulating portion, and the insulating portion is formed by removing the silicon (111) substrate from the insulating portion, and the silicon on the silicon (100) substrate. The insulating portion including the oxide film is joined to the silicon oxide film and the silicon oxide film formed by bonding the silicon oxide films, and the silicon (111) substrate is removed to form a gate on the silicon (100) substrate. An insulating film is formed.

また、本発明では上記課題を解決するために、窒素を含むゲート絶縁膜を備える半導体装置において、第１のシリコン（１１１）基板上に第１のシリコン酸化膜および膜厚が１原子層の第１のシリコン窒化膜を順に備える第１の絶縁部と、第２のシリコン（１１１）基板上に膜厚が１原子層の第２のシリコン窒化膜を備える第２の絶縁部とを接合した第３の絶縁部の、前記第１のシリコン窒化膜および前記第２のシリコン窒化膜を張り合わせて成る第３のシリコン窒化膜と、前記第３の絶縁部の前記第１のシリコン（１１１）基板を除去した第４の絶縁部と、シリコン（１００）基板上に第２のシリコン酸化膜を備える第５の絶縁部とを、前記第１のシリコン酸化膜および前記第２のシリコン酸化膜を張り合わせ、前記第２のシリコン（１１１）基板を除去して成る、前記シリコン（１００）基板上の第３のシリコン酸化膜と、を有することを特徴とする半導体装置が提供される。   According to the present invention, in order to solve the above problems, in a semiconductor device including a gate insulating film containing nitrogen, a first silicon oxide film and a first atomic layer having a thickness of one atomic layer are formed on a first silicon (111) substrate. A first insulating portion provided with one silicon nitride film in order and a second insulating portion provided with a second silicon nitride film having a thickness of one atomic layer on a second silicon (111) substrate; A third silicon nitride film formed by laminating the first silicon nitride film and the second silicon nitride film in the third insulating portion, and the first silicon (111) substrate in the third insulating portion. The removed fourth insulating portion and the fifth insulating portion including the second silicon oxide film on the silicon (100) substrate are bonded to the first silicon oxide film and the second silicon oxide film, The second silicon (11 ) Formed by removing the substrate, and a third silicon oxide film of the silicon (100) substrate, a semiconductor device characterized by having provided.

このような半導体装置によれば、シリコン（１１１）基板上にシリコン酸化膜および膜厚が１原子層のシリコン窒化膜を順に備える絶縁部と、シリコン（１１１）基板上に膜厚が１原子層のシリコン窒化膜を備える絶縁部とを接合した絶縁部の、シリコン窒化膜およびシリコン窒化膜を張り合わせて成るシリコン窒化膜と、絶縁部のシリコン（１１１）基板を除去した絶縁部と、シリコン（１００）基板上にシリコン酸化膜を備える絶縁部とを、シリコン酸化膜およびシリコン酸化膜を張り合わせ、シリコン（１１１）基板を除去して成る、シリコン（１００）基板上のシリコン酸化膜と、で構成されるゲート絶縁膜が形成されるようになる。   According to such a semiconductor device, the insulating portion including the silicon oxide film and the silicon nitride film having a thickness of one atomic layer on the silicon (111) substrate in order, and the atomic layer having a thickness of one atomic layer on the silicon (111) substrate. The silicon nitride film formed by bonding the silicon nitride film and the silicon nitride film, the insulating part obtained by removing the silicon (111) substrate in the insulating part, and silicon (100 And a silicon oxide film on the silicon (100) substrate formed by laminating the silicon oxide film and the silicon oxide film and removing the silicon (111) substrate. A gate insulating film is formed.

本発明では、シリコン（１１１）基板上にシリコン酸化膜およびシリコン窒化膜を順に備える絶縁部と、シリコン（１１１）基板上にシリコン窒化膜を備える絶縁部とを、シリコン窒化膜およびシリコン窒化膜を張り合わせて成るシリコン窒化膜を介して、接合し、絶縁部を形成し、絶縁部のシリコン（１１１）基板を除去した絶縁部と、シリコン（１００）基板上にシリコン酸化膜を備える絶縁部とを、シリコン酸化膜およびシリコン酸化膜を張り合わせて成るシリコン酸化膜を介して、接合し、さらに、シリコン（１１１）基板を除去して、シリコン（１００）基板上にゲート絶縁膜を形成するようにした。これにより、リーク電流を抑制させて、信頼性を向上することができる。   In the present invention, an insulating portion including a silicon oxide film and a silicon nitride film on a silicon (111) substrate in order, and an insulating portion including a silicon nitride film on the silicon (111) substrate are replaced with a silicon nitride film and a silicon nitride film. An insulating portion formed by bonding and forming an insulating portion through the bonded silicon nitride film and removing the silicon (111) substrate of the insulating portion, and an insulating portion including a silicon oxide film on the silicon (100) substrate. The silicon oxide film and the silicon oxide film formed by bonding the silicon oxide films are bonded to each other, and the silicon (111) substrate is removed to form a gate insulating film on the silicon (100) substrate. . Thereby, leakage current can be suppressed and reliability can be improved.

以下、本発明の実施の形態を、図面を参照して詳細に説明する。但し、本発明の技術的範囲はこれらの実施の形態に限定されない。
本実施の概要について図面を参照して説明し、その後に、本発明の概要に基づいた実施の形態について、同様に図面を参照して説明する。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments.
An outline of the present embodiment will be described with reference to the drawings, and then an embodiment based on the outline of the present invention will be described with reference to the drawings.

では、本発明の概要について図１を用いて以下に説明する。
図１は、本発明の概要を示した、半導体装置の製造工程の要部断面模式図である。図１は、本発明の半導体装置の、特に、ゲート部の製造方法を時系列的に４つの製造工程（図１（Ａ）〜図１（Ｄ））に分けて、各工程を模式的に示している。以下、各製造工程に沿って説明する。 The outline of the present invention will be described below with reference to FIG.
FIG. 1 is a schematic cross-sectional view of an essential part of a semiconductor device manufacturing process showing an outline of the present invention. FIG. 1 schematically shows a method of manufacturing a semiconductor device of the present invention, in particular, a gate part divided into four manufacturing steps (FIGS. 1A to 1D) in time series. Show. Hereinafter, it demonstrates along each manufacturing process.

まず、Ｓｉ（１１１）基板１上に、１原子層のシリコン窒化（ＳｉＮ）膜を成膜する。なお、非特許文献１などによれば、１原子層程度のＳｉＮを、Ｓｉ（１１１）の表面に付き回り良く成膜できることが知られており、本発明ではこの知見を利用している。そして、ＳｉＮ膜が上部に成膜されたＳｉ（１１１）基板１を酸素分子（Ｏ2）雰囲気中でアニールして、ＳｉＮ膜とＳｉ（１１１）基板１との界面に、ＳｉＯ2膜２ａが生成される。なお、ＳｉＯ2膜２ａの上部のＳｉＮ膜をＳｉＮ膜３ａとし、Ｓｉ（１１１）基板１／ＳｉＯ2膜２ａ／ＳｉＮ膜３ａの３つを合わせて絶縁部１１とする。 First, a one-layer silicon nitride (SiN) film is formed on the Si (111) substrate 1. According to Non-Patent Document 1 and the like, it is known that SiN of about one atomic layer can be well deposited on the surface of Si (111), and this knowledge is used in the present invention. Then, the Si (111) substrate 1 having the SiN film formed thereon is annealed in an oxygen molecule (O 2 ) atmosphere, and the SiO 2 film 2a is formed at the interface between the SiN film and the Si (111) substrate 1. Generated. The SiN film above the SiO 2 film 2a is the SiN film 3a, and the Si (111) substrate 1 / SiO 2 film 2a / SiN film 3a are combined to form the insulating portion 11.

同様にして、Ｓｉ（１１１）基板４上に、１原子層のＳｉＮ膜３ｂを成膜する。なお、Ｓｉ（１１１）基板４／ＳｉＮ膜３ｂの２つを合わせて絶縁部１２とする。
このようにして形成した絶縁部１１，１２を、ＳｉＮ膜３ａ，３ｂを張り合わせることで接合させる。なお、図１（Ａ）には、接合させている様子を示している。 Similarly, a one atomic layer SiN film 3 b is formed on the Si (111) substrate 4. Note that the two parts of the Si (111) substrate 4 / SiN film 3b are combined to form the insulating portion 12.
The insulating parts 11 and 12 formed in this way are bonded together by bonding the SiN films 3a and 3b. Note that FIG. 1A shows a state of bonding.

接合させた絶縁部１１，１２をアニールすると、張り合わされたＳｉＮ膜３ａ，３ｂは結合してＳｉＮ膜３となる。なお、ＳｉＮ膜３を生成させた、Ｓｉ（１１１）基板１／ＳｉＯ2膜２ａ／ＳｉＮ膜３／Ｓｉ（１１１）基板４の４つを合わせて絶縁部１３として、図１（Ｂ）に示している。 When the bonded insulating portions 11 and 12 are annealed, the bonded SiN films 3 a and 3 b are combined to form the SiN film 3. In addition, the Si (111) substrate 1 / SiO 2 film 2a / SiN film 3 / Si (111) substrate 4 on which the SiN film 3 is formed are combined to form an insulating portion 13 as shown in FIG. ing.

一方、Ｓｉ（１００）基板５上に、ＳｉＯ2膜２ｂを成膜する。なお、Ｓｉ（１００）基板５／ＳｉＯ2膜２ｂの２つを合わせて絶縁部１４とする。
また、絶縁部１３のＳｉ（１１１）基板１を除去した、ＳｉＯ2膜２ａ／ＳｉＮ膜３／Ｓｉ（１１１）基板４の３つを合わせて絶縁部１３ａとする。 On the other hand, the SiO 2 film 2 b is formed on the Si (100) substrate 5. The Si (100) substrate 5 / SiO 2 film 2b are combined to form the insulating portion 14.
Further, the three parts of the SiO 2 film 2a / SiN film 3 / Si (111) substrate 4 from which the Si (111) substrate 1 of the insulating part 13 has been removed are combined to form an insulating part 13a.

そして、このようにして形成した絶縁部１３ａ，１４をＳｉＯ2膜２ａ，２ｂを張り合わせることで接合させる。なお、図１（Ｃ）には、接合させている様子を示している。
接合させた絶縁部１３ａ，１４をアニールすると、張り合わされたＳｉＯ2膜２ａ，２ｂは結合してＳｉＯ2膜２となる。そして、Ｓｉ（１１１）基板４を除去すると、図１（Ｄ）に示すように、Ｓｉ（１００）基板５上に、ＳｉＯ2膜２およびＳｉＮ膜３から構成されるゲート絶縁膜１５が成膜される。 Then, the insulating portions 13a and 14 formed in this way are bonded together by bonding the SiO 2 films 2a and 2b. Note that FIG. 1C illustrates a state of bonding.
When the joined insulating portions 13a and 14 are annealed, the bonded SiO 2 films 2a and 2b are combined to form the SiO 2 film 2. Then, when the Si (111) substrate 4 is removed, a gate insulating film 15 composed of the SiO 2 film 2 and the SiN film 3 is formed on the Si (100) substrate 5 as shown in FIG. Is done.

以後の工程については図示してはいないが、このようにして得られたゲート絶縁膜１５上に、引き続き、ゲート電極を形成して、エッチングやソース、ドレインなどの導入などを行って、ＭＯＳＦＥＴを作製することができる。   Although the subsequent steps are not shown, a gate electrode is subsequently formed on the gate insulating film 15 obtained in this way, and etching, source, drain, etc. are introduced, and the MOSFET is formed. Can be produced.

以上のように、Ｓｉ（１１１）基板１上にＳｉＯ2膜２ａおよびＳｉＮ膜３ａを備えた絶縁部１１と、Ｓｉ（１１１）基板４上にＳｉＮ膜３ｂを成膜した絶縁部１２とを、ＳｉＮ膜３ａ，３ｂを張り合わせて成るＳｉＮ膜３を介して、接合し、絶縁部１３を形成した。そして、絶縁部１３のＳｉ（１１１）基板１を除去した絶縁部１３ａと、Ｓｉ（１００）基板５上にＳｉＯ2膜２ｂを成膜した絶縁部１４とを、ＳｉＯ2膜２ａ，２ｂを張り合わせて成るＳｉＯ2膜２を介して、接合し、さらに、Ｓｉ（１１１）基板４を除去して、Ｓｉ（１００）基板５上に、ＳｉＯ2膜２およびＳｉＮ膜３から構成されるゲート絶縁膜１５を形成することができた。 As described above, the insulating part 11 having the SiO 2 film 2a and the SiN film 3a on the Si (111) substrate 1 and the insulating part 12 having the SiN film 3b formed on the Si (111) substrate 4 are obtained. The SiN films 3a and 3b were bonded to each other through the SiN film 3 to form an insulating portion 13. Then, an insulating portion 13a which is Si (111) removing the substrate 1 of the insulating portion 13, and an insulating portion 14 which is a SiO 2 film 2b to Si (100) substrate 5 on, laminated SiO 2 film 2a, 2b through the SiO 2 film 2 formed of Te, bonded, further, by removing the Si (111) substrate 4, the Si (100) substrate 5 on the gate insulating film composed of SiO 2 film 2 and the SiN film 3 15 could be formed.

これにより、従来は、ゲート絶縁膜中のＮの分布や量の制御が困難であったために特性劣化などが生じていたが、本発明では、図１で示した製造方法によって、緻密性および平坦性が高く、均質なＳｉＮ膜３をＳｉＯ2膜２上に形成することができ、ＳｉＯ2膜２およびＳｉＮ膜３をゲート絶縁膜１５とすることで、不純物の侵入を防いで、電荷捕獲中心、界面準位が防止され、また、誘電率も向上させることができ、ホットキャリア耐性を向上させ、リーク電流を抑制させることが可能となり、信頼性を向上させることができる。 As a result, conventionally, it has been difficult to control the distribution and amount of N in the gate insulating film, resulting in deterioration of characteristics. However, in the present invention, the manufacturing method shown in FIG. sexual high, uniform SiN film 3 can be formed on the SiO 2 film 2, by the SiO 2 film 2 and the SiN film 3 as a gate insulating film 15, to prevent intrusion of impurities, charge trapping centers In addition, the interface state can be prevented, the dielectric constant can be improved, the hot carrier resistance can be improved, the leakage current can be suppressed, and the reliability can be improved.

次に、本発明の概要に基づいた本発明の実施の形態について図２から図４を用いて以下に説明する。
本発明の実施の形態では、上記概要を踏まえて、半導体装置の製造方法について触れる。 Next, an embodiment of the present invention based on the outline of the present invention will be described below with reference to FIGS.
In the embodiment of the present invention, a method for manufacturing a semiconductor device will be described based on the above outline.

図２〜図４は、本発明の実施の形態における半導体装置の製造工程の要部断面模式図である。なお、本実施の形態は半導体装置の製造方法の１例に過ぎず、本発明の課題を解決できる効果が得られれば、製造方法やその順序、または使用する材料などが異なっていても構わない。   2 to 4 are schematic cross-sectional views of the relevant part of the manufacturing process of the semiconductor device according to the embodiment of the present invention. Note that this embodiment is merely an example of a method for manufacturing a semiconductor device, and a manufacturing method, its order, or a material to be used may be different as long as an effect capable of solving the problems of the present invention is obtained. .

まず、Ｓｉ（１１１）基板２１を１気圧の窒素分子（Ｎ2）ガス中で、１０６０℃で３００秒間アニールする。その結果、Ｓｉ（１１１）基板２１上に、１分子層の均質なＳｉＮ膜を成膜できる。そして、ＳｉＮ膜が上部に成膜されたＳｉ（１１１）基板２１を０．１気圧のＯ2ガス雰囲気中で０．５分間アニールして、ＳｉＮ膜とＳｉ（１１１）基板１との界面に、膜厚が０．５ｎｍのＳｉＯ2膜２２ａが生成される。なお、ＳｉＯ2膜２２ａの上部のＳｉＮ膜をＳｉＮ膜２３ａとし、Ｓｉ（１１１）基板２１／ＳｉＯ2膜２２ａ／ＳｉＮ膜２３ａの３つを合わせて絶縁部３１とする。 First, the Si (111) substrate 21 is annealed at 1060 ° C. for 300 seconds in a nitrogen molecular (N 2 ) gas at 1 atm. As a result, a uniform SiN film having a single molecular layer can be formed on the Si (111) substrate 21. Then, the Si (111) substrate 21 having the SiN film formed thereon is annealed in an O 2 gas atmosphere at 0.1 atm for 0.5 minutes, so that the interface between the SiN film and the Si (111) substrate 1 is obtained. A SiO 2 film 22a having a thickness of 0.5 nm is generated. The SiN film above the SiO 2 film 22a is the SiN film 23a, and the Si (111) substrate 21 / SiO 2 film 22a / SiN film 23a are combined to form the insulating portion 31.

同様にして、シリコン（Ｓｉ）（１１１）基板２４上に、１分子層のＳｉＮ膜２３ｂを成膜する。なお、Ｓｉ（１１１）基板２４／ＳｉＮ膜２３ｂの２つを合わせて絶縁部３２とする。   Similarly, a monomolecular SiN film 23 b is formed on a silicon (Si) (111) substrate 24. The Si (111) substrate 24 / SiN film 23b are combined to form the insulating portion 32.

このようにして形成した絶縁部３１，３２を、ＳｉＮ膜２３ａ，２３ｂを張り合わせて接合させる。ＳｉＮ膜２３ａ，２３ｂの張り合わせの際には、ＳｉＮ膜２３ａ，２３ｂ間に不純物が入らないように注意する。なお、図２（Ａ）には張り合わせた様子を示している。   The insulating parts 31 and 32 formed in this way are bonded together by bonding the SiN films 23a and 23b. At the time of bonding the SiN films 23a and 23b, care is taken so that impurities do not enter between the SiN films 23a and 23b. Note that FIG. 2A shows a state where they are bonded together.

そして、接合させた絶縁部３１，３２を、アルゴン（Ａｒ）ガスまたは真空中で、８００℃で３分間のアニールを行って、張り合わされたＳｉＮ膜２３ａ，２３ｂを結合させてＳｉＮ膜２３となる。なお、ＳｉＮ膜２３を生成した、Ｓｉ（１１１）基板２１／ＳｉＯ2膜２２ａ／ＳｉＮ膜２３／Ｓｉ（１１１）基板２４の４つを合わせて絶縁部３３として、図２（Ｂ）に示している。 Then, the bonded insulating portions 31 and 32 are annealed at 800 ° C. for 3 minutes in argon (Ar) gas or vacuum, and the bonded SiN films 23 a and 23 b are bonded to form the SiN film 23. . 2B, the Si (111) substrate 21 / SiO 2 film 22a / SiN film 23 / Si (111) substrate 24, which formed the SiN film 23, are combined into the insulating portion 33 as shown in FIG. Yes.

一方、Ｓｉ（１００）基板２５を０．１気圧のＯ2ガス雰囲気中で、７００℃で０．５分間アニールする。そして、Ｓｉ（１００）基板２５上に、膜厚１ｎｍ以下のＳｉＯ2膜２２ｂを成膜する。なお、Ｓｉ（１００）基板２５／ＳｉＯ2膜２２ｂの２つを合わせて絶縁部３４とする。 On the other hand, the Si (100) substrate 25 is annealed at 700 ° C. for 0.5 minutes in an O 2 gas atmosphere of 0.1 atm. Then, a SiO 2 film 22b having a thickness of 1 nm or less is formed on the Si (100) substrate 25. The Si (100) substrate 25 / SiO 2 film 22b are combined to form the insulating portion 34.

また、フッ酸と硝酸との混合液を用いてスプレーエッチングによって絶縁部３３のＳｉ（１１１）基板２１を除去した、ＳｉＯ2膜２２ａ／ＳｉＮ膜２３／Ｓｉ（１１１）基板２４の３つを合わせて絶縁部３３ａとする。 In addition, the SiO 2 film 22a / SiN film 23 / Si (111) substrate 24, in which the Si (111) substrate 21 of the insulating portion 33 is removed by spray etching using a mixed solution of hydrofluoric acid and nitric acid, are combined. Insulating portion 33a.

このようにして形成した絶縁部３３ａ，３４を、ＳｉＯ2膜２２ａ，２２ｂを張り合わせて接合させる。ＳｉＯ2膜２２ａ，２２ｂの張り合わせの際には、ＳｉＯ2膜２２ａ，２２ｂ間に不純物が入らないように注意する。なお、図３（Ａ）には張り合わせた様子を示している。 The insulating portions 33a and 34 thus formed are bonded together by bonding the SiO 2 films 22a and 22b. During bonding of the SiO 2 film 22a, 22b is careful SiO 2 film 22a, an impurity between 22b does not enter. Note that FIG. 3A shows a state of bonding.

そして、接合させた絶縁部３３ａ，３４を、Ａｒガスまたは真空中で、８００℃で３分間のアニールを行って、張り合わされたＳｉＯ2膜２２ａ，２２ｂは結合してＳｉＯ2膜２２となる。なお、ＳｉＯ2膜２２を生成した、Ｓｉ（１００）基板２５／ＳｉＯ2膜２２／ＳｉＮ膜２３／Ｓｉ（１１１）基板２４の４つを合わせて絶縁部３５として、図３（Ｂ）に示している。 The bonded insulating portions 33a and 34 are annealed at 800 ° C. for 3 minutes in Ar gas or vacuum, and the bonded SiO 2 films 22a and 22b are combined to form the SiO 2 film 22. Incidentally, to produce a SiO 2 film 22, as Si (100) substrate 25 / SiO 2 film 22 / SiN film 23 / Si (111) insulating portion 35 4 The combined substrate 24, shown in FIG. 3 (B) ing.

次に、フッ酸と硝酸との混合液を用いてスプレーエッチングによって絶縁部３５のＳｉ（１１１）基板２４を除去する。
Ｓｉ（１１１）基板２４が除去された後、ＳｉＯ2膜２２とＳｉＮ膜２３とから構成されるゲート絶縁膜上に、図４（Ａ）に示すように、Ｐｏｌｙ−Ｓｉ電極２６をＬＰＣＶＤ（Low Pressure Chemical Vapor Deposition：減圧化学的気相成長）法によって形成する。なお、Ｐｏｌｙ−Ｓｉ電極２６の代わりに、ＳｉＮ膜２３上に、例えば、ニッケル（Ｎｉ）、白金（Ｐｔ）、タングステン（Ｗ）またはエルビウム（Ｅｒ）などの金属薄膜を堆積させて、５００℃の加熱を行ってシリサイド化するようにしても良い。 Next, the Si (111) substrate 24 of the insulating portion 35 is removed by spray etching using a mixed solution of hydrofluoric acid and nitric acid.
After the Si (111) substrate 24 is removed, a Poly-Si electrode 26 is formed on the gate insulating film composed of the SiO 2 film 22 and the SiN film 23 by LPCVD (Low CVD) as shown in FIG. It is formed by the Pressure Chemical Vapor Deposition method. Instead of the Poly-Si electrode 26, for example, a metal thin film such as nickel (Ni), platinum (Pt), tungsten (W) or erbium (Er) is deposited on the SiN film 23 at 500 ° C. Heating may be used for silicidation.

最後に、エッチングやイオンのドーピング、熱拡散処理などを行って、図４（Ｂ）に示すような、ＭＯＳＦＥＴを形成することができる。
以上のように、Ｓｉ（１１１）基板２１上にＳｉＯ2膜２２ａおよびＳｉＮ膜２３ａを備えた絶縁部３１と、Ｓｉ（１１１）基板２４上にＳｉＮ膜２３ｂを成膜した絶縁部３２とを、ＳｉＮ膜２３ａ，２３ｂを張り合わせて成るＳｉＮ膜２３を介して、接合し、絶縁部３３を形成した。そして、絶縁部３３のＳｉ（１１１）基板２１を除去した絶縁部３３ａと、Ｓｉ（１００）基板２５上にＳｉＯ2膜２２ｂを成膜した絶縁部３４とを、ＳｉＯ2膜２２ａ，２２ｂを張り合わせて成るＳｉＯ2膜２２を介して、接合し、さらに、Ｓｉ（１１１）基板２４を除去して、Ｓｉ（１００）基板２５上に、ＳｉＯ2膜２２およびＳｉＮ膜２３から構成されるゲート絶縁膜を備えることで、ホットキャリア耐性を向上させ、リーク電流を抑制させることが可能となり、信頼性が向上したＭＯＳＦＥＴを形成することができた。 Finally, etching, ion doping, thermal diffusion treatment, and the like can be performed to form a MOSFET as shown in FIG.
As described above, the insulating part 31 provided with the SiO 2 film 22a and the SiN film 23a on the Si (111) substrate 21, and the insulating part 32 formed with the SiN film 23b on the Si (111) substrate 24. The SiN films 23a and 23b are bonded together to form an insulating portion 33. Then, an insulating portion 33a obtained by removing the Si (111) substrate 21 of the insulating portion 33, and an insulating portion 34 which is a SiO 2 film 22b in Si (100) substrate 25 on, laminated SiO 2 film 22a, and 22b through the SiO 2 film 22 of Te, bonded, further, by removing the Si (111) substrate 24, the Si (100) substrate 25 on, the gate insulating film composed of SiO 2 film 22 and the SiN film 23 As a result, it was possible to improve hot carrier resistance, suppress leakage current, and form a MOSFET with improved reliability.

以上によって、緻密性および平坦性が高く、均質なＳｉＮ膜をＳｉＯ2膜上に形成することができ、ＳｉＯ2膜およびＳｉＮ膜をゲート絶縁膜とすることで、不純物の侵入を防いで、電荷捕獲中心、界面準位が防止され、また、誘電率も向上させることができ、ホットキャリア耐性を向上させ、リーク電流を抑制させることが可能となり、信頼性を向上させることができる。 By the above, highly dense and flatness, it is possible to form a homogeneous SiN film on the SiO 2 film, by the SiO 2 film and the SiN film and the gate insulating film, to prevent intrusion of impurities, charge Capture centers and interface states can be prevented, the dielectric constant can be improved, hot carrier resistance can be improved, leakage current can be suppressed, and reliability can be improved.

（付記１） 窒素を含むゲート絶縁膜を備える半導体装置の製造方法において、
第１のシリコン（１１１）基板上に第１のシリコン酸化膜および第１のシリコン窒化膜を順に備える第１の絶縁部と、第２のシリコン（１１１）基板上に第２のシリコン窒化膜を備える第２の絶縁部とを、前記第１のシリコン窒化膜および前記第２のシリコン窒化膜を張り合わせて成る第３のシリコン窒化膜を介して、接合し、第３の絶縁部を形成する工程と、
前記第３の絶縁部の前記第１のシリコン（１１１）基板を除去した第４の絶縁部と、シリコン（１００）基板上に第２のシリコン酸化膜を備える第５の絶縁部とを、前記第１のシリコン酸化膜および前記第２のシリコン酸化膜を張り合わせて成る第３のシリコン酸化膜を介して、接合し、さらに、前記第２のシリコン（１１１）基板を除去して、前記シリコン（１００）基板上に前記ゲート絶縁膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 (Supplementary Note 1) In a method for manufacturing a semiconductor device including a gate insulating film containing nitrogen,
A first insulating part comprising a first silicon oxide film and a first silicon nitride film in this order on a first silicon (111) substrate, and a second silicon nitride film on a second silicon (111) substrate A step of forming a third insulating portion by bonding a second insulating portion provided to the second insulating portion via a third silicon nitride film formed by bonding the first silicon nitride film and the second silicon nitride film; When,
A fourth insulating portion obtained by removing the first silicon (111) substrate of the third insulating portion; and a fifth insulating portion including a second silicon oxide film on the silicon (100) substrate. The first silicon oxide film and the second silicon oxide film are bonded to each other via a third silicon oxide film. Further, the second silicon (111) substrate is removed, and the silicon ( 100) forming the gate insulating film on the substrate;
A method for manufacturing a semiconductor device, comprising:

（付記２） 前記第１のシリコン窒化膜および前記第２のシリコン窒化膜は膜厚がそれぞれ１原子層であることを特徴とする付記１記載の半導体装置の製造方法。
（付記３） 前記第１のシリコン（１１１）基板上に前記第１のシリコン窒化膜を形成し、酸素分子でアニールして、前記第１のシリコン（１１１）基板と前記第１のシリコン窒化膜との界面に前記第１のシリコン酸化膜を形成して、前記第１の絶縁部を形成することを特徴とする付記１または２に記載の半導体装置の製造方法。 (Supplementary note 2) The method of manufacturing a semiconductor device according to supplementary note 1, wherein the first silicon nitride film and the second silicon nitride film each have a thickness of one atomic layer.
(Supplementary Note 3) The first silicon nitride film is formed on the first silicon (111) substrate, annealed with oxygen molecules, and the first silicon (111) substrate and the first silicon nitride film are annealed. 3. The method of manufacturing a semiconductor device according to appendix 1 or 2, wherein the first insulating portion is formed by forming the first silicon oxide film at an interface with the semiconductor device.

（付記４） 前記第１のシリコン（１１１）基板と前記第２のシリコン（１１１）基板との除去をスプレーエッチングによって行うことを特徴とする付記１乃至３のいずれか１項記載の半導体装置の製造方法。   (Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein the removal of the first silicon (111) substrate and the second silicon (111) substrate is performed by spray etching. Production method.

（付記５） 前記ゲート絶縁膜形成後、前記ゲート絶縁膜上にポリシリコンまたは金属薄膜にてゲート電極を形成することを特徴とする付記１乃至４のいずれか１項記載の半導体装置の製造方法。   (Additional remark 5) After forming the said gate insulating film, a gate electrode is formed on the said gate insulating film with a polysilicon or a metal thin film, The manufacturing method of the semiconductor device of any one of Additional remark 1 thru | or 4 characterized by the above-mentioned .

（付記６） 前記金属薄膜は、ニッケル、白金、タングステンまたはエルビウムであることを特徴とする付記５記載の半導体装置の製造方法。
（付記７） 窒素を含むゲート絶縁膜を備える半導体装置において、
第１のシリコン（１１１）基板上に第１のシリコン酸化膜および膜厚が１原子層の第１のシリコン窒化膜を順に備える第１の絶縁部と、第２のシリコン（１１１）基板上に膜厚が１原子層の第２のシリコン窒化膜を備える第２の絶縁部とを接合した第３の絶縁部の、前記第１のシリコン窒化膜および前記第２のシリコン窒化膜を張り合わせて成る第３のシリコン窒化膜と、
前記第３の絶縁部の前記第１のシリコン（１１１）基板を除去した第４の絶縁部と、シリコン（１００）基板上に第２のシリコン酸化膜を備える第５の絶縁部とを、前記第１のシリコン酸化膜および前記第２のシリコン酸化膜を張り合わせ、前記第２のシリコン（１１１）基板を除去して成る、前記シリコン（１００）基板上の第３のシリコン酸化膜と、
を有することを特徴とする半導体装置。 (Additional remark 6) The said metal thin film is nickel, platinum, tungsten, or erbium, The manufacturing method of the semiconductor device of Additional remark 5 characterized by the above-mentioned.
(Supplementary Note 7) In a semiconductor device including a gate insulating film containing nitrogen,
A first insulating portion comprising a first silicon oxide film and a first silicon nitride film having a thickness of one atomic layer on a first silicon (111) substrate, and a second silicon (111) substrate; The first silicon nitride film and the second silicon nitride film are bonded to each other in a third insulating portion joined to a second insulating portion including a second silicon nitride film having a thickness of one atomic layer. A third silicon nitride film;
A fourth insulating portion obtained by removing the first silicon (111) substrate of the third insulating portion; and a fifth insulating portion including a second silicon oxide film on the silicon (100) substrate. A third silicon oxide film on the silicon (100) substrate formed by bonding the first silicon oxide film and the second silicon oxide film and removing the second silicon (111) substrate;
A semiconductor device comprising:

本発明の概要を示した、半導体装置の製造工程の要部断面模式図である。It is the principal part cross-sectional schematic diagram of the manufacturing process of a semiconductor device which showed the outline | summary of this invention. 本発明の実施の形態における半導体装置の製造工程の要部断面模式図（その１）である。FIG. 3 is a schematic cross-sectional view (No. 1) of relevant parts of the semiconductor device manufacturing process in the embodiment of the present invention; 本発明の実施の形態における半導体装置の製造工程の要部断面模式図（その２）である。FIG. 10 is a schematic cross-sectional view (No. 2) of relevant parts of the semiconductor device manufacturing process in the embodiment of the present invention; 本発明の実施の形態における半導体装置の製造工程の要部断面模式図（その３）である。FIG. 10 is a schematic cross-sectional view (No. 3) of relevant parts of the semiconductor device manufacturing process in the embodiment of the present invention; ＭＯＳＦＥＴの要部断面模式図である。It is a principal part cross-sectional schematic diagram of MOSFET.

符号の説明Explanation of symbols

１，４ Ｓｉ（１１１）基板
２，２ａ，２ｂ ＳｉＯ2膜
３，３ａ，３ｂ ＳｉＮ膜
５ Ｓｉ（１００）基板
１１，１２，１３，１４ 絶縁部 1, 4 Si (111) substrate 2, 2a, 2b SiO 2 film 3, 3a, 3b SiN film 5 Si (100) substrate 11, 12, 13, 14 Insulating part

Claims (5)

窒素を含むゲート絶縁膜を備える半導体装置の製造方法において、
第１のシリコン（１１１）基板上に第１のシリコン酸化膜および第１のシリコン窒化膜を順に備える第１の絶縁部と、第２のシリコン（１１１）基板上に第２のシリコン窒化膜を備える第２の絶縁部とを、前記第１のシリコン窒化膜および前記第２のシリコン窒化膜を張り合わせて成る第３のシリコン窒化膜を介して、接合し、第３の絶縁部を形成する工程と、
前記第３の絶縁部の前記第１のシリコン（１１１）基板を除去した第４の絶縁部と、シリコン（１００）基板上に第２のシリコン酸化膜を備える第５の絶縁部とを、前記第１のシリコン酸化膜および前記第２のシリコン酸化膜を張り合わせて成る第３のシリコン酸化膜を介して、接合し、さらに、前記第２のシリコン（１１１）基板を除去して、前記シリコン（１００）基板上に前記ゲート絶縁膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 In a method for manufacturing a semiconductor device including a gate insulating film containing nitrogen,
A first insulating part comprising a first silicon oxide film and a first silicon nitride film in this order on a first silicon (111) substrate, and a second silicon nitride film on a second silicon (111) substrate A step of forming a third insulating portion by bonding a second insulating portion provided to the second insulating portion via a third silicon nitride film formed by bonding the first silicon nitride film and the second silicon nitride film; When,
A fourth insulating portion obtained by removing the first silicon (111) substrate of the third insulating portion; and a fifth insulating portion including a second silicon oxide film on the silicon (100) substrate. The first silicon oxide film and the second silicon oxide film are bonded to each other via a third silicon oxide film. Further, the second silicon (111) substrate is removed, and the silicon ( 100) forming the gate insulating film on the substrate;
A method for manufacturing a semiconductor device, comprising: 前記第１のシリコン窒化膜および前記第２のシリコン窒化膜は膜厚がそれぞれ１原子層であることを特徴とする請求項１記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein each of the first silicon nitride film and the second silicon nitride film has a thickness of one atomic layer. 前記第１のシリコン（１１１）基板上に前記第１のシリコン窒化膜を形成し、酸素分子でアニールして、前記第１のシリコン（１１１）基板と前記第１のシリコン窒化膜との界面に前記第１のシリコン酸化膜を形成して、前記第１の絶縁部を形成することを特徴とする請求項１または２に記載の半導体装置の製造方法。   The first silicon nitride film is formed on the first silicon (111) substrate, annealed with oxygen molecules, and formed at the interface between the first silicon (111) substrate and the first silicon nitride film. The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating portion is formed by forming the first silicon oxide film. 前記ゲート絶縁膜形成後、前記ゲート絶縁膜上にポリシリコンまたは金属薄膜にてゲート電極を形成することを特徴とする請求項１乃至３のいずれか１項記載の半導体装置の製造方法。   4. The method of manufacturing a semiconductor device according to claim 1, wherein after forming the gate insulating film, a gate electrode is formed on the gate insulating film with polysilicon or a metal thin film. 窒素を含むゲート絶縁膜を備える半導体装置において、
第１のシリコン（１１１）基板上に第１のシリコン酸化膜および膜厚が１原子層の第１のシリコン窒化膜を順に備える第１の絶縁部と、第２のシリコン（１１１）基板上に膜厚が１原子層の第２のシリコン窒化膜を備える第２の絶縁部とを接合した第３の絶縁部の、前記第１のシリコン窒化膜および前記第２のシリコン窒化膜を張り合わせて成る第３のシリコン窒化膜と、
前記第３の絶縁部の前記第１のシリコン（１１１）基板を除去した第４の絶縁部と、シリコン（１００）基板上に第２のシリコン酸化膜を備える第５の絶縁部とを、前記第１のシリコン酸化膜および前記第２のシリコン酸化膜を張り合わせ、前記第２のシリコン（１１１）基板を除去して成る、前記シリコン（１００）基板上の第３のシリコン酸化膜と、
を有することを特徴とする半導体装置。 In a semiconductor device including a gate insulating film containing nitrogen,
A first insulating portion comprising a first silicon oxide film and a first silicon nitride film having a thickness of one atomic layer on a first silicon (111) substrate, and a second silicon (111) substrate; The first silicon nitride film and the second silicon nitride film are bonded to each other in a third insulating portion joined to a second insulating portion including a second silicon nitride film having a thickness of one atomic layer. A third silicon nitride film;
A fourth insulating portion obtained by removing the first silicon (111) substrate of the third insulating portion; and a fifth insulating portion including a second silicon oxide film on the silicon (100) substrate. A third silicon oxide film on the silicon (100) substrate formed by bonding the first silicon oxide film and the second silicon oxide film and removing the second silicon (111) substrate;
A semiconductor device comprising:
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