JPH05259012A - Semiconductor substrate and manufacture thereof - Google Patents

Semiconductor substrate and manufacture thereof

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Publication number
JPH05259012A
JPH05259012A JP5121292A JP5121292A JPH05259012A JP H05259012 A JPH05259012 A JP H05259012A JP 5121292 A JP5121292 A JP 5121292A JP 5121292 A JP5121292 A JP 5121292A JP H05259012 A JPH05259012 A JP H05259012A
Authority
JP
Japan
Prior art keywords
substrate
single crystal
crystal silicon
oxide film
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5121292A
Other languages
Japanese (ja)
Inventor
Toru Aoyama
亨 青山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5121292A priority Critical patent/JPH05259012A/en
Publication of JPH05259012A publication Critical patent/JPH05259012A/en
Withdrawn legal-status Critical Current

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  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To laminate two substrates without generation of voids even when rough-surfaced single crystal silicon substrates are used by a method wherein an insulting film is constructed into a laminated structure consisting of a silicon oxide film and a silicon nitride film in the manufacture of a semiconductor substrate having a single crytal layer which is formed on a supporting substrate through an insulating film. CONSTITUTION:A single crystal silicon substrate 1, having a silicon oxide film 2 of 1mum in thickness, is prepared. Oxygen ions 3 of the dosage of 1X10<16>/cm<2> are implanted into the silicon oxide film 2 using the accelerated energy of 30 KeV before lamination of the above-mentioned material. Then, a commercially available second single crystal silicon substrate 4 of 1nm in surface roughness, is laminated with the substrate 1 as the supporting substrate. The lamination of the two substrates is conducted as follows: the oxygen ion implanted silicon oxide film 2 and the mirror surface of the second single crystal silicon substrate 4 are laminated, and a heat treatment is conducted at 950 deg.C for two hours. A SOI substrate is obtained by polishing the first single crystal silicon substrate 1 after lamination.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体基板およびその製
造方法に関し、特に絶縁膜に被われた単結晶シリコン基
板に他の単結晶シリコン基板を貼合せた後、片面から研
磨して単結晶シリコン基板を薄くすることによって絶縁
膜上に単結晶シリコン層を形成する半導体基板およびそ
の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method for manufacturing the same, and in particular, a single crystal silicon substrate covered with an insulating film is bonded to another single crystal silicon substrate and then polished from one side to obtain single crystal silicon. The present invention relates to a semiconductor substrate in which a single crystal silicon layer is formed on an insulating film by thinning the substrate and a manufacturing method thereof.

【0002】[0002]

【従来の技術】トランジスタの微細化に伴って個々の素
子の間隔が狭くなってきており、完全な素子分離が注目
されている。SOI(Silicon On Insu
lator)基板は、例えば支持基板としてのシリコン
基板上の絶縁膜上に単結晶シリコン層が存在するもので
あり、この単結晶シリコン層に素子を形成することによ
り素子領域を下のシリコン基板を電気的に完全に分離で
きるため、ラッチアップや放射線のソフトエラーの対策
として期待されている。SOI基板の作製方法の1つに
単結晶シリコン基板の貼合わせ法がある。以下、従来の
貼合せ技術を図3を用いて説明する。
2. Description of the Related Art With the miniaturization of transistors, the distance between individual elements is becoming narrower, and complete element isolation is receiving attention. SOI (Silicon On Insu)
A substrate) is a substrate in which a single crystal silicon layer is present on an insulating film on a silicon substrate serving as a support substrate. By forming an element on the single crystal silicon layer, the silicon substrate below the element region is electrically connected. It is expected to be used as a countermeasure against latch-up and radiation soft error because it can be completely separated. One of the methods for manufacturing an SOI substrate is a bonding method for a single crystal silicon substrate. The conventional bonding technique will be described below with reference to FIG.

【0003】まず図3(a)に示すように、表面にシリ
コン酸化膜2を有する第1の単結晶シリコン基板2を用
意する。次に図3(b)に示すように、支持基板として
の第2の単結晶シリコン基板4に第1の単結晶シリコン
基板1のシリコン酸化膜2を重ね合わせ、約2時間の熱
処理をして貼合せる。
First, as shown in FIG. 3A, a first single crystal silicon substrate 2 having a silicon oxide film 2 on its surface is prepared. Next, as shown in FIG. 3B, the silicon oxide film 2 of the first single crystal silicon substrate 1 is overlaid on the second single crystal silicon substrate 4 as a supporting substrate, and heat treatment is performed for about 2 hours. Laminate.

【0004】熱処理には、1100℃以上の温度を必要
とし、熱処理温度が低いと僅かな引っ張り応力で剥がれ
をおこしたり、ボイドと呼ばれる空孔が貼合わせ面5に
生ずる。1100℃での貼合せでは、引っ張り応力60
0kg/cm2 以上まで耐えられるが、900℃での貼
合せ強度は200kg/cm2 以下となってくる。ま
た、800℃以下での貼合わせでは、ボイドが生じるこ
とがT アベ(Abe)等によりプロスイーディング
オブ フォース インターナショナル シンポジウム
オン シリコンオン インシュレータ テクノロジイ
アンド デバイセス(Proceedings of
4th international Symposi
um on “Silicon−on−Insulat
or Technology and Device
s”)P61−71(1990年)に報告されている。
The heat treatment requires a temperature of 1100 ° C. or higher, and when the heat treatment temperature is low, peeling occurs due to a slight tensile stress, and voids called voids are formed on the bonding surface 5. When laminating at 1100 ° C, the tensile stress is 60
It can withstand up to 0 kg / cm 2 or more, but the bonding strength at 900 ° C. becomes 200 kg / cm 2 or less. In addition, when laminating at 800 ° C or lower, voids may occur
Of Force International Symposium
On Silicon On Insulator Technology
And Devices (Proceedings of
4th international Symposi
um on “Silicon-on-Insult
or Technology and Device
s ") P61-71 (1990).

【0005】貼合せ後はどちらの面からでもよいが、片
面より研磨して、図3(c)に示すように、シリコン酸
化膜3上に単結晶シリコン層1Aを形成して、SOI基
板を完成させる。
After the bonding, either side may be used, but polishing is performed from one side to form a single crystal silicon layer 1A on the silicon oxide film 3 as shown in FIG. Finalize.

【0006】[0006]

【発明が解決しようとする課題】上述した従来の単結晶
シリコン基板の貼合せ方法では、貼合せ界面でのボイド
の発生という問題がある。熱処理温度を800℃以下に
するとボイドを生ずるということは前述したが、従来法
における1100℃での貼合せる基板の表面状態によっ
てはボイドを生じる。ボイドの発生には、貼合せ温度以
外に貼合せる基板の表面状態が大きく関係しており、そ
の中の1つに表面粗さがある。従来例でボイドを発生さ
せないための表面粗さの条件は、0.5nm以下になっ
ていなくてはならない。この値は、鏡面を有する普通の
シリコン基板の表面粗さが約1nmであることを考慮す
ると、かなり厳しい要求のものになっている。したがっ
て、従来法を用いたSOI基板は、従来の普通のシリコ
ン基板では作製できないためコスト高になってしまうと
いう問題点がある。
The above-described conventional method for laminating a single crystal silicon substrate has a problem that voids are generated at the laminating interface. It has been described above that a void is generated when the heat treatment temperature is 800 ° C. or lower, but the void is generated depending on the surface state of the substrate to be bonded at 1100 ° C. in the conventional method. The occurrence of voids is greatly related to the surface condition of the substrates to be bonded other than the bonding temperature, and one of them is the surface roughness. The condition of the surface roughness for preventing the generation of voids in the conventional example must be 0.5 nm or less. Considering that the surface roughness of a normal silicon substrate having a mirror surface is about 1 nm, this value is quite a severe requirement. Therefore, the SOI substrate using the conventional method has a problem that the cost becomes high because it cannot be manufactured with the conventional ordinary silicon substrate.

【0007】また、SOI基板は単結晶シリコン基板の
間にシリコン酸化膜を挟む構造をとっているため、潜在
的に内部に応力を持っている。そのため、通常の単結晶
シリコン基板に対する条件で1100℃の熱処理を行う
と、SOI基板にスリップ等の結晶欠陥が入り、素子領
域の結晶劣化を引き起こす。しかし、従来法では、熱処
理温度を1100℃より下げるとボイドの発生や張り合
せ強度の低下を伴ってしまうという問題点もある。
Further, since the SOI substrate has a structure in which a silicon oxide film is sandwiched between single crystal silicon substrates, there is potential internal stress. Therefore, when heat treatment is performed at 1100 ° C. under the conditions for a normal single crystal silicon substrate, crystal defects such as slips are introduced into the SOI substrate, causing crystal deterioration in the element region. However, the conventional method has a problem that when the heat treatment temperature is lowered below 1100 ° C., voids are generated and the bonding strength is lowered.

【0008】[0008]

【課題を解決するための手段】第1の発明の半導体基板
は、支持基板上に絶縁膜を介して設けられた単結晶シリ
コン層を有する半導体基板において、前記絶縁膜はシリ
コン酸化膜とシリコン窒化膜からなる積層構造を有する
ものである。
A semiconductor substrate according to a first aspect of the present invention is a semiconductor substrate having a single crystal silicon layer provided on a supporting substrate via an insulating film, wherein the insulating film is a silicon oxide film and a silicon nitride film. It has a laminated structure composed of films.

【0009】第2の発明の半導体基板の製造方法は、表
面が絶縁膜で覆われた第1の単結晶シリコン基板の表面
上に第2の単結晶シリコン基板を貼合せた後、片面から
研磨して前記第1または第2の単結晶シリコン基板を薄
くする半導体基板の製造方法において、前記第2の単結
晶シリコン基板の張合せを行う前に前記絶縁膜に酸素イ
オンまたは水酸基イオンを注入するものである。
In the method of manufacturing a semiconductor substrate according to the second invention, the second single crystal silicon substrate is bonded onto the surface of the first single crystal silicon substrate whose surface is covered with an insulating film, and then polished from one side. In the method for manufacturing a semiconductor substrate in which the first or second single crystal silicon substrate is thinned, oxygen ions or hydroxyl ions are implanted into the insulating film before bonding the second single crystal silicon substrate. It is a thing.

【0010】酸素イオンもしくは水酸基イオンを熱処理
前に絶縁膜中に注入することによって、単結晶シリコン
基板中のシリコン原子と注入した酸素イオンを貼合せ界
面で結合させて酸化シリコンを形成させる。それによ
り、従来よりも低温の熱酸化温度領域で強固な貼合せを
実現すると同時に、シリコン酸化膜形成が進行すること
によってボイドの発生が抑制される。さらに、シリコン
窒化膜を絶縁膜に用いることで、熱処理時に絶縁膜より
下方のシリコン基板中に酸素が拡散するのを防ぐことが
できるため、貼合せ面に酸素を集中させて結合を促進さ
せることができる。
By implanting oxygen ions or hydroxyl ions into the insulating film before heat treatment, the silicon atoms in the single crystal silicon substrate and the implanted oxygen ions are bonded at the bonding interface to form silicon oxide. As a result, firm bonding is achieved in a thermal oxidation temperature region that is lower than in the past, and at the same time, the generation of voids is suppressed due to the progress of silicon oxide film formation. Furthermore, by using a silicon nitride film for the insulating film, oxygen can be prevented from diffusing into the silicon substrate below the insulating film during heat treatment, so that oxygen can be concentrated on the bonding surface to promote bonding. You can

【0011】[0011]

【実施例】次に本発明について図面を参照して説明す
る。図1(a)〜(c)は本発明の第1の実施例を説明
するための断面図である。
The present invention will be described below with reference to the drawings. 1A to 1C are sectional views for explaining a first embodiment of the present invention.

【0012】まず図1(a)に示すように、素子作成基
板として第1の単結晶シリコン基板1上に1μm厚のシ
リコン酸化膜2を有するものを用意し、貼合せ前に酸素
イオン3を1x1016/cm2 のドーズ量,30keV
の加速エネルギーの条件でシリコン酸化膜2に注入し
た。この注入エネルギーでの打ち込み深さは約60nm
であり、酸素イオンは貼合せ面5の近傍に存在する。
First, as shown in FIG. 1A, a device having a silicon oxide film 2 with a thickness of 1 μm on a first single crystal silicon substrate 1 is prepared as an element formation substrate, and oxygen ions 3 are attached before bonding. 1 × 10 16 / cm 2 dose amount, 30 keV
Was implanted into the silicon oxide film 2 under the conditions of acceleration energy. The implantation depth with this implantation energy is about 60 nm
And oxygen ions exist near the bonding surface 5.

【0013】次に図1(b)に示すように、支持基板と
して、市販の表面粗さが1nmである第2の単結晶シリ
コン基板4を用いた。両基板の貼合せは、酸素イオン注
入をしたシリコン酸化膜2と第2の単結晶シリコン基板
4の鏡面とを重ね合わせて、950℃で2時間の熱処理
をすることで行った。
Next, as shown in FIG. 1B, a commercially available second single crystal silicon substrate 4 having a surface roughness of 1 nm was used as a supporting substrate. The two substrates were bonded together by superposing the oxygen ion-implanted silicon oxide film 2 and the mirror surface of the second single-crystal silicon substrate 4 on each other and performing heat treatment at 950 ° C. for 2 hours.

【0014】次に図1(c)に示すように、貼合わせ後
に第1の単結晶シリコン基板1を研磨することで、厚さ
2μmの単結晶シリコン層1Aを形成し、SOI基板を
得た。
Next, as shown in FIG. 1 (c), the first single crystal silicon substrate 1 is polished after the bonding to form a single crystal silicon layer 1A having a thickness of 2 μm, and an SOI substrate is obtained. ..

【0015】本第1の実施例における基板の貼合せは、
熱処理温度を950℃に低くしたことにより、スリップ
等の結晶欠陥は観察されなかった。さらに貼合せ面5は
引っ張り強度で従来と同様に600kg/cm2 以上の
応力に耐えることができた。また、従来例では表面粗さ
は約1nmである市販の単結晶シリコン基板を用いて貼
合せを行う場合には、表面粗さを0.5nm以下に加工
しなくてはボイドの発生を抑えることができなかった
が、本第1の実施例では表面粗さは1nmのままでも、
貼合わせ面5にボイドの発生はみられなかった。
The bonding of the substrates in the first embodiment is
By lowering the heat treatment temperature to 950 ° C., crystal defects such as slip were not observed. Further, the bonding surface 5 has a tensile strength and can withstand a stress of 600 kg / cm 2 or more as in the conventional case. Further, in the conventional example, when bonding is performed using a commercially available single crystal silicon substrate having a surface roughness of about 1 nm, it is necessary to process the surface roughness to 0.5 nm or less to suppress the generation of voids. However, in the first embodiment, even if the surface roughness remains 1 nm,
No void was found on the bonding surface 5.

【0016】第1の実施例では熱処理前に酸素イオンを
注入して、第2の単結晶シリコン基板4のシリコン原子
を酸化させて貼合わせを行うため、支持基板としての第
2の単結晶シリコン基板4の表面粗さを加工することな
しにボイドのない貼合わせが実現した。したがって、本
第1の実施例により市販の単結晶シリコン基板を用い
て、かつ従来よりも低温の熱処理でSOI基板を得るこ
とができた。
In the first embodiment, oxygen ions are implanted before the heat treatment to oxidize the silicon atoms of the second single crystal silicon substrate 4 to carry out the bonding, so that the second single crystal silicon as the supporting substrate is used. Void-free bonding was realized without processing the surface roughness of the substrate 4. Therefore, according to the first embodiment, the SOI substrate can be obtained by using the commercially available single crystal silicon substrate and performing the heat treatment at a lower temperature than the conventional one.

【0017】図2(a)〜(c)は本発明の第2の実施
例を説明するための断面図である。
FIGS. 2A to 2C are sectional views for explaining the second embodiment of the present invention.

【0018】まず図2(a)に示すように、素子作成基
板として表面にシリコン酸化膜2A,シリコン窒化膜
6,シリコン酸化膜2Bの3層構造の絶縁膜を有する第
1の単結晶シリコン基板11を用い、貼合せの前に、水
酸基イオン7を1x1016/cm2 のドーズ量で絶縁膜
に注入した。シリコン酸化膜2Bの膜厚は1μmであ
り、酸素イオンがシリコン酸化膜2Bより下の層に抜け
ないように第1の実施例と同様に加速エネルギーを30
keVとした。
First, as shown in FIG. 2A, a first single crystal silicon substrate having a three-layer insulating film of a silicon oxide film 2A, a silicon nitride film 6, and a silicon oxide film 2B on the surface as an element formation substrate. 11, the hydroxyl ion 7 was injected into the insulating film at a dose of 1 × 10 16 / cm 2 before bonding. The thickness of the silicon oxide film 2B is 1 μm, and the acceleration energy is set to 30 in the same manner as in the first embodiment so that oxygen ions do not escape to the layer below the silicon oxide film 2B.
It was set to keV.

【0019】次に図2(b)に示すように、支持基板と
して表面粗さが約1nmである市販の第2の単結晶シリ
コン基板14を用いた。両基板の貼合せは、シリコン酸
化膜2Bと第2の単結晶シリコン基板14の鏡面とを重
ね合わせて、950℃で1時間の熱処理をすることで行
った。
Next, as shown in FIG. 2B, a commercially available second single crystal silicon substrate 14 having a surface roughness of about 1 nm was used as a supporting substrate. The bonding of the two substrates was performed by superimposing the silicon oxide film 2B and the mirror surface of the second single crystal silicon substrate 14 on each other and performing heat treatment at 950 ° C. for 1 hour.

【0020】次に図2(c)に示すように、貼合せた後
に第1の単結晶シリコン基板11側から研磨して、厚さ
2μmの単結晶シリコン層11Aを形成し、SOI基板
を得た。
Next, as shown in FIG. 2 (c), after bonding, polishing is performed from the first single crystal silicon substrate 11 side to form a single crystal silicon layer 11A having a thickness of 2 μm to obtain an SOI substrate. It was

【0021】この第2の実施例で形成したSOI基板の
貼合わせ面5Aは、第1の実施例と同じく950℃の熱
処理で、ボイドの発生が抑えられ、引っ張り強度でも6
00kg/cm2 以上の応力に耐えられることが確認さ
れた。また、低温化によりスリップ等の結晶欠陥も観察
されなかった。本第2の実施例では絶縁膜にシリコン窒
化膜6を挟むことで、熱処理中に水酸基イオンがシリコ
ン酸化膜2A中に拡散することを防いだ。それにより、
水酸基素イオンは第2の単結晶シリコン基板14中にの
み拡散して貼合わせ面5A近傍のシリコン原子の酸化を
促進した為、第1の実施例よりも短い時間で貼合せが可
能となった。このように第2の実施例でも、市販の単結
晶シリコン基板を用いても、ボイドのない基板の貼合せ
が実現できた。
The bonding surface 5A of the SOI substrate formed in the second embodiment is subjected to the heat treatment at 950 ° C. as in the first embodiment to prevent the generation of voids and has a tensile strength of 6%.
It was confirmed that it could withstand a stress of 00 kg / cm 2 or more. Further, no crystal defects such as slips were observed due to the low temperature. In the second embodiment, the silicon nitride film 6 is sandwiched between the insulating films to prevent the hydroxyl ions from diffusing into the silicon oxide film 2A during the heat treatment. Thereby,
Since the hydroxyl group ions diffused only into the second single crystal silicon substrate 14 and promoted the oxidation of silicon atoms in the vicinity of the bonding surface 5A, bonding was possible in a shorter time than in the first embodiment. .. As described above, the void-free substrates can be bonded even in the second embodiment and the commercially available single crystal silicon substrate.

【0022】[0022]

【発明の効果】以上説明したように本発明によれば、約
1nmの表面粗さをもつ単結晶シリコン基板を用いて
も、ボイドを発生させることなしに基板の貼合せが可能
となった。これにより、市販の単結晶シリコン基板を用
いての貼合せによるSOI基板の製造が可能になった。
また、熱処理温度を低くできるため、素子領域の結晶の
劣化が抑えられた。
As described above, according to the present invention, even if a single crystal silicon substrate having a surface roughness of about 1 nm is used, it is possible to bond the substrates without generating voids. As a result, it became possible to manufacture an SOI substrate by laminating a commercially available single crystal silicon substrate.
Further, since the heat treatment temperature can be lowered, the deterioration of the crystal in the element region was suppressed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を説明するための断面
図。
FIG. 1 is a sectional view for explaining a first embodiment of the present invention.

【図2】本発明の第2の実施例を説明するための断面
図。
FIG. 2 is a sectional view for explaining a second embodiment of the present invention.

【図3】従来の半導体基板の製造方法を説明するための
断面図。
FIG. 3 is a sectional view for explaining a conventional method for manufacturing a semiconductor substrate.

【符号の説明】 1,11 第1の単結晶シリコン基板 1A,11A 単結晶シリコン層 2,2A,2B シリコン酸化膜 3 酸素イオン 4,14 第2の単結晶シリコン基板 5 貼合せ面 6 シリコン窒化膜 7 水酸基イオン[Explanation of reference numerals] 1,11 First single crystal silicon substrate 1A, 11A Single crystal silicon layer 2,2A, 2B Silicon oxide film 3 Oxygen ion 4,14 Second single crystal silicon substrate 5 Bonding surface 6 Silicon nitride Membrane 7 Hydroxyl ion

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 支持基板上に絶縁膜を介して設けられた
単結晶シリコン層を有する半導体基板において、前記絶
縁膜はシリコン酸化膜とシリコン窒化膜からなる積層構
造を有することを特徴とする半導体基板。
1. A semiconductor substrate having a single crystal silicon layer provided on a supporting substrate via an insulating film, wherein the insulating film has a laminated structure of a silicon oxide film and a silicon nitride film. substrate.
【請求項2】 表面が絶縁膜で覆われた第1の単結晶シ
リコン基板の表面上に第2の単結晶シリコン基板を貼合
せた後、片面から研磨して前記第1または第2の単結晶
シリコン基板を薄くする半導体基板の製造方法におい
て、前記第2の単結晶シリコン基板の張合せを行う前に
前記絶縁膜に酸素イオンまたは水酸基イオンを注入する
ことを特徴とする半導体基板の製造方法。
2. A first single crystal silicon substrate having a surface covered with an insulating film, a second single crystal silicon substrate bonded to the surface of the first single crystal silicon substrate, and then polished from one surface to obtain the first or second single crystal silicon substrate. A method of manufacturing a semiconductor substrate having a thin crystalline silicon substrate, wherein oxygen ions or hydroxyl ions are implanted into the insulating film before the second single crystal silicon substrate is bonded. ..
【請求項3】 絶縁膜がシリコン酸化膜である請求項2
記載の半導体基板の製造方法。
3. The insulating film is a silicon oxide film.
A method for manufacturing the semiconductor substrate described.
【請求項4】 絶縁膜がシリコン酸化膜とシリコン窒化
膜の積層膜である請求項2記載の半導体基板の製造方
法。
4. The method of manufacturing a semiconductor substrate according to claim 2, wherein the insulating film is a laminated film of a silicon oxide film and a silicon nitride film.
JP5121292A 1992-03-10 1992-03-10 Semiconductor substrate and manufacture thereof Withdrawn JPH05259012A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5121292A JPH05259012A (en) 1992-03-10 1992-03-10 Semiconductor substrate and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5121292A JPH05259012A (en) 1992-03-10 1992-03-10 Semiconductor substrate and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05259012A true JPH05259012A (en) 1993-10-08

Family

ID=12880613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5121292A Withdrawn JPH05259012A (en) 1992-03-10 1992-03-10 Semiconductor substrate and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH05259012A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007305662A (en) * 2006-05-09 2007-11-22 Sumco Corp Method of manufacturing semiconductor substrate
KR100796831B1 (en) * 2005-01-31 2008-01-22 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 Process for transfer of a thin layer formed in a substrate with vacancy clusters
JP2009009959A (en) * 2007-06-26 2009-01-15 Fujitsu Ltd Semiconductor device manufacturing method and semiconductor device
JP2009508329A (en) * 2005-09-08 2009-02-26 エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ Method for manufacturing semiconductor-on-insulator heterostructure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100796831B1 (en) * 2005-01-31 2008-01-22 에스. 오. 이. 떼끄 씰리꽁 오 냉쉴라또흐 떼끄놀로지 Process for transfer of a thin layer formed in a substrate with vacancy clusters
JP2009508329A (en) * 2005-09-08 2009-02-26 エス.オー.アイ.テック、シリコン、オン、インシュレター、テクノロジーズ Method for manufacturing semiconductor-on-insulator heterostructure
JP2007305662A (en) * 2006-05-09 2007-11-22 Sumco Corp Method of manufacturing semiconductor substrate
JP2009009959A (en) * 2007-06-26 2009-01-15 Fujitsu Ltd Semiconductor device manufacturing method and semiconductor device

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