JP5075716B2 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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JP5075716B2
JP5075716B2 JP2008096376A JP2008096376A JP5075716B2 JP 5075716 B2 JP5075716 B2 JP 5075716B2 JP 2008096376 A JP2008096376 A JP 2008096376A JP 2008096376 A JP2008096376 A JP 2008096376A JP 5075716 B2 JP5075716 B2 JP 5075716B2
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初日出 五十嵐
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Renesas Electronics Corp
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Description

本発明は、半導体集積回路装置に係り、特に、静電保護回路を備える増幅器を含む半導体集積回路装置に係る。   The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including an amplifier including an electrostatic protection circuit.

水晶振動子、セラミック振動子などの固体振動子を用いた発振回路は、様々な電子機器に広く使用されている。発振回路は、帰還路にバイアス抵抗と共に固体振動子を並列に接続した反転増幅器あるいは差動増幅器によって構成されることが多い。   Oscillation circuits using solid-state vibrators such as crystal vibrators and ceramic vibrators are widely used in various electronic devices. The oscillation circuit is often constituted by an inverting amplifier or a differential amplifier in which a solid oscillator is connected in parallel with a bias resistor in a feedback path.

例えば、特許文献1には、差動増幅器の逆相出力から同相入力に水晶振動子を介して帰還するコルピッツ型水晶発振回路が記載されている。この回路は、差動増幅器の逆相入力にNRZ受信データ変化点検出パルス信号を入力し、差動増幅器の同相出力からNRZ受信データ変化点検出パルス信号に位相同期したタイミング信号を抽出する水晶同期発振器によるタイミング抽出回路として機能する。   For example, Patent Document 1 describes a Colpitts-type crystal oscillation circuit that feeds back from a reverse-phase output of a differential amplifier to an in-phase input via a crystal resonator. This circuit inputs the NRZ reception data change point detection pulse signal to the negative phase input of the differential amplifier, and extracts the timing signal that is phase-synchronized with the NRZ reception data change point detection pulse signal from the in-phase output of the differential amplifier. It functions as a timing extraction circuit using an oscillator.

また、特許文献2には、反転増幅器の入出力端子にそれぞれ保護回路を備え、さらに反転増幅器の入力端子と保護回路間に容量素子を備える発振回路が開示されている。この回路は、容量素子によって保護回路から入力端子側に流入あるいは流出するリーク電流を防止している。   Patent Document 2 discloses an oscillation circuit that includes a protection circuit at each input / output terminal of an inverting amplifier, and further includes a capacitor between the input terminal of the inverting amplifier and the protection circuit. This circuit prevents a leak current flowing into or out of the input terminal from the protection circuit by the capacitive element.

特開昭60−165850号公報JP 60-165850 A 米国特許第6320473号明細書US Pat. No. 6,320,473

以下の分析は本発明において与えられる。   The following analysis is given in the present invention.

固体振動子を用いた発振回路を半導体集積回路装置に実装する場合、半導体集積回路装置に外部端子を設け、固体振動子は、この外部端子に接続される。半導体集積回路装置において、外部端子は、外部に露出することから、外部の影響を受け、特に静電気による影響は、時として半導体集積回路装置に損傷を与えることもある。したがって、静電気が外部端子に印加された場合に半導体集積回路装置の損傷を防止するように、半導体集積回路装置の内部において外部端子に接続される静電保護回路を備えることが一般的である。   When an oscillation circuit using a solid vibrator is mounted on a semiconductor integrated circuit device, an external terminal is provided in the semiconductor integrated circuit device, and the solid vibrator is connected to the external terminal. In the semiconductor integrated circuit device, the external terminal is exposed to the outside, and thus is affected by the outside. Especially, the influence due to static electricity sometimes damages the semiconductor integrated circuit device. Therefore, it is common to provide an electrostatic protection circuit connected to the external terminal inside the semiconductor integrated circuit device so as to prevent damage to the semiconductor integrated circuit device when static electricity is applied to the external terminal.

ところで、近年、半導体集積回路装置のファインパターン化に伴って半導体集積回路装置の電源などの低電圧化が進み、デバイスのしきい値が低下している。このため入出力保護回路におけるリーク電流が増大し、リーク電流の値が数μAになることも稀ではなくなってきている。   By the way, in recent years, with the fine patterning of semiconductor integrated circuit devices, the power supply voltage of semiconductor integrated circuit devices has been reduced, and the threshold value of devices has been lowered. For this reason, the leakage current in the input / output protection circuit is increased, and it is not rare that the value of the leakage current becomes several μA.

一方、反転増幅器あるいは差動増幅器の入出力間に固体振動子と並列に接続されるバイアス抵抗の値は、非常に高く、通常数百Ωから場合によっては1MΩを超えることもある。したがって、特に高温においてリーク電流が増大すると、増幅器の入力端におけるバイアス点がずれてしまい、発振波形が歪み、時には発振が停止してしまうことも起こり得る。   On the other hand, the value of the bias resistor connected in parallel with the solid-state vibrator between the input and output of the inverting amplifier or the differential amplifier is very high, and is usually from several hundred Ω to 1 MΩ in some cases. Therefore, especially when the leakage current increases at a high temperature, the bias point at the input end of the amplifier shifts, the oscillation waveform is distorted, and sometimes the oscillation stops.

ところで、特許文献2に記載の発振回路では、入力端子と保護回路間に備えた容量素子によってリーク電流を阻止するようにしている。しかしながら、発振回路を半導体集積回路装置に構成する場合、容量素子は占有面積が大きいため、容量素子を半導体集積回路装置内に実装しようとすると半導体集積回路装置が大型化してしまう虞があった。   By the way, in the oscillation circuit described in Patent Document 2, leakage current is blocked by a capacitive element provided between the input terminal and the protection circuit. However, when the oscillation circuit is configured in a semiconductor integrated circuit device, the capacitive element occupies a large area. Therefore, when the capacitive element is mounted in the semiconductor integrated circuit device, the semiconductor integrated circuit device may be increased in size.

本発明者は、このようなリーク電流遮断用の容量素子を削減しても、安定的に発振する構成を創案するに至った。   The inventor of the present invention has come up with a configuration that stably oscillates even when the number of leakage current blocking capacitance elements is reduced.

本発明の1つのアスペクト(側面)に係る半導体集積回路装置は、外部回路の一端を接続可能とする第1の外部端子と、外部回路の他端を接続可能とする第2の外部端子と、第1の抵抗素子と、第2の抵抗素子と、反転入力端子を第1の外部端子および第1の抵抗素子の一端に接続し、出力端子を第2の外部端子および第1の抵抗素子の他端に接続し、非反転入力端子を第2の抵抗素子を介してバイアス供給源に接続する差動増幅器と、反転入力端子に接続される第1の静電保護回路と、非反転入力端子に接続される第2の静電保護回路と、を備え、差動増幅器は、反転出力端子をさらに備え、反転出力端子から内部回路に出力信号を出力するように構成し、バイアス供給源を反転出力端子とする。
本発明の他のアスペクト(側面)に係る半導体集積回路装置は、外部回路の一端を接続可能とする第1の外部端子と、外部回路の他端を接続可能とする第2の外部端子と、第1の抵抗素子と、第2の抵抗素子と、反転入力端子を第1の外部端子および第1の抵抗素子の一端に接続し、出力端子を第2の外部端子および第1の抵抗素子の他端に接続し、非反転入力端子を第2の抵抗素子を介してバイアス供給源に接続する差動増幅器と、反転入力端子に接続される第1の静電保護回路と、非反転入力端子に接続される第2の静電保護回路と、を備え、バイアス供給源を第1の抵抗素子の所定の分割点とする。
A semiconductor integrated circuit device according to one aspect (side surface) of the present invention includes a first external terminal capable of connecting one end of an external circuit, a second external terminal capable of connecting the other end of the external circuit, The first resistance element, the second resistance element, the inverting input terminal are connected to the first external terminal and one end of the first resistance element, and the output terminal is connected to the second external terminal and the first resistance element. A differential amplifier connected to the other end and connecting a non-inverting input terminal to a bias supply source via a second resistance element, a first electrostatic protection circuit connected to the inverting input terminal, and a non-inverting input terminal A differential electrostatic amplifier further comprising an inverting output terminal, configured to output an output signal from the inverting output terminal to the internal circuit, and inverting the bias supply source It shall be the output terminal.
A semiconductor integrated circuit device according to another aspect (side surface) of the present invention includes a first external terminal capable of connecting one end of an external circuit, a second external terminal capable of connecting the other end of the external circuit, The first resistance element, the second resistance element, the inverting input terminal are connected to the first external terminal and one end of the first resistance element, and the output terminal is connected to the second external terminal and the first resistance element. A differential amplifier connected to the other end and connecting a non-inverting input terminal to a bias supply source via a second resistance element, a first electrostatic protection circuit connected to the inverting input terminal, and a non-inverting input terminal A second electrostatic protection circuit connected to the first resistance element, and the bias supply source is a predetermined division point of the first resistance element.

本発明によれば、静電保護回路におけるリーク電流が増大した場合に反転入力端子および非反転入力端子のバイアス電圧が共に同一方向に変動して、差動増幅器の出力における直流電圧の変動を抑えることができる。したがって、広い温度範囲において安定的に発振する回路規模の小さい発振回路が構成される。   According to the present invention, when the leakage current in the electrostatic protection circuit increases, the bias voltages of the inverting input terminal and the non-inverting input terminal both fluctuate in the same direction, and the fluctuation of the DC voltage at the output of the differential amplifier is suppressed. be able to. Therefore, an oscillation circuit having a small circuit scale that stably oscillates in a wide temperature range is configured.

本発明の実施形態に係る半導体集積回路装置は、外部回路の一端を接続可能とする第1の外部端子と、外部回路の他端を接続可能とする第2の外部端子と、第1の抵抗素子と、第2の抵抗素子と、反転入力端子を第1の外部端子および第1の抵抗素子の一端に接続し、出力端子を第2の外部端子および第1の抵抗素子の他端に接続し、非反転入力端子を第2の抵抗素子を介してバイアス供給源に接続する差動増幅器と、反転入力端子に接続される第1の静電保護回路と、非反転入力端子に接続される第2の静電保護回路と、を備える。   A semiconductor integrated circuit device according to an embodiment of the present invention includes a first external terminal capable of connecting one end of an external circuit, a second external terminal capable of connecting the other end of the external circuit, and a first resistor. The element, the second resistance element, and the inverting input terminal are connected to the first external terminal and one end of the first resistance element, and the output terminal is connected to the second external terminal and the other end of the first resistance element. And a differential amplifier that connects the non-inverting input terminal to the bias supply source via the second resistance element, a first electrostatic protection circuit that is connected to the inverting input terminal, and a non-inverting input terminal. A second electrostatic protection circuit.

本発明の実施形態に係る半導体集積回路装置において、差動増幅器は、反転出力端子をさらに備え、反転出力端子から内部回路に出力信号を出力するように構成してもよい。   In the semiconductor integrated circuit device according to the embodiment of the present invention, the differential amplifier may further include an inverting output terminal and output an output signal from the inverting output terminal to the internal circuit.

本発明の実施形態に係る半導体集積回路装置において、バイアス供給源を反転出力端子とするようにしてもよい。   In the semiconductor integrated circuit device according to the embodiment of the present invention, the bias supply source may be an inverting output terminal.

本発明の実施形態に係る半導体集積回路装置において、バイアス供給源を第1の抵抗素子の所定の分割点とするようにしてもよい。   In the semiconductor integrated circuit device according to the embodiment of the present invention, the bias supply source may be a predetermined division point of the first resistance element.

本発明の実施形態に係る半導体集積回路装置において、出力端子に接続される第3の静電保護回路をさらに備えるようにしてもよい。   The semiconductor integrated circuit device according to the embodiment of the present invention may further include a third electrostatic protection circuit connected to the output terminal.

本発明の実施形態に係る半導体集積回路装置において、外部回路は、固体振動子を含む回路であって、発振回路として機能させることが好ましい。   In the semiconductor integrated circuit device according to the embodiment of the present invention, the external circuit is a circuit including a solid-state vibrator and preferably functions as an oscillation circuit.

以下、実施例に即し、図面を参照して詳しく説明する。   Hereinafter, it will be described in detail with reference to the drawings in accordance with embodiments.

図1は、本発明の第1の実施例に係る半導体集積回路装置の回路図である。図1において、半導体集積回路装置10は、差動増幅器OP、抵抗素子R1、R2、外部端子P1、P2、静電保護回路11a、11b、11cを備える。差動増幅器OPは、反転入力端子(−)を外部端子P1、抵抗素子R1の一端および静電保護回路11bに接続し、出力端子を外部端子P2、抵抗素子R1の他端および静電保護回路11cに接続し、非反転入力端子(+)を静電保護回路11aに接続すると共に抵抗素子R2を介して反転出力端子に接続する。この場合、抵抗素子R1、R2の抵抗値を等しくすることが好ましい。静電保護回路11a、11b、11cは、例えば直列接続された逆方向の2個のダイオードを電源、接地間に接続し、2個のダイオードの接続点を差動増幅器OPの非反転入力端子(+)、反転入力端子(−)、出力端子にそれぞれ接続する構成とされる。   FIG. 1 is a circuit diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention. In FIG. 1, a semiconductor integrated circuit device 10 includes a differential amplifier OP, resistance elements R1 and R2, external terminals P1 and P2, and electrostatic protection circuits 11a, 11b, and 11c. In the differential amplifier OP, the inverting input terminal (−) is connected to the external terminal P1, one end of the resistor element R1, and the electrostatic protection circuit 11b, and the output terminal is connected to the external terminal P2, the other end of the resistor element R1, and the electrostatic protection circuit. 11c, and the non-inverting input terminal (+) is connected to the electrostatic protection circuit 11a and to the inverting output terminal via the resistance element R2. In this case, it is preferable to make the resistance values of the resistance elements R1 and R2 equal. The electrostatic protection circuits 11a, 11b, and 11c, for example, connect two diodes connected in series in the reverse direction between the power source and the ground, and connect the connection point of the two diodes to the non-inverting input terminal ( +), An inverting input terminal (−), and an output terminal.

また、半導体集積回路装置10は、外部において、外部端子P1、P2間に水晶振動子XTLの両端を接続し、外部端子P1に一端が接地された容量素子C1の他端を接続し、外部端子P2に一端が接地された容量素子C2の他端を接続し、発振回路を構成する。さらに、発振回路による出力OUTは、差動増幅器OPの反転出力端子から図示されない半導体集積回路装置10の内部回路に与えられる。この反転出力端子は、半導体集積回路装置の外部には接続されない。なお、容量素子C1、C2は、必要に応じて半導体集積回路装置内部に実装してもよい。   Further, the semiconductor integrated circuit device 10 externally connects both ends of the crystal resonator XTL between the external terminals P1 and P2, and connects the other end of the capacitive element C1 whose one end is grounded to the external terminal P1. The other end of the capacitive element C2 whose one end is grounded is connected to P2 to constitute an oscillation circuit. Further, the output OUT from the oscillation circuit is given to the internal circuit of the semiconductor integrated circuit device 10 (not shown) from the inverting output terminal of the differential amplifier OP. This inverted output terminal is not connected to the outside of the semiconductor integrated circuit device. Capacitance elements C1 and C2 may be mounted inside the semiconductor integrated circuit device as necessary.

このような構成の半導体集積回路装置10において、静電保護回路にリーク電流が生じたとする。ここで電源側から静電保護回路11bを介して抵抗素子R1に流れるリーク電流をI1とし、電源側から静電保護回路11aを介して抵抗素子R2に流れるリーク電流をI2とする。静電保護回路11a、11bは、半導体集積回路装置10内にあって同一プロセスで製造されるので、等価であって、リーク電流I1、I2の値は等しい。また、差動増幅器OPの出力端子および反転出力端子の直流電位は等しい。したがって、抵抗素子R1、R2の抵抗値を等しくすることで差動増幅器OPの反転入力端子(−)および非反転入力端子(+)のリーク電流による電位変動が等しくなる。すなわち、温度上昇等でリーク電流I1、I2が増大した場合であっても、反転入力端子(−)および非反転入力端子(+)における電位の上昇が等しく、差動増幅器OPの出力端子および反転出力端子の直流電位の変動を防ぐことができる。このため、半導体集積回路装置10は、広い温度範囲に亘って安定した発振動作を行うことが可能である。なお、リーク電流は、静電保護回路11cにも流れるが、差動増幅器OPの出力端子におけるインピーダンスは低いので、静電保護回路11cに流れるリーク電流によって出力端子の電位が変動することはない。   In the semiconductor integrated circuit device 10 having such a configuration, it is assumed that a leakage current is generated in the electrostatic protection circuit. Here, a leakage current flowing from the power supply side to the resistance element R1 via the electrostatic protection circuit 11b is I1, and a leakage current flowing from the power supply side to the resistance element R2 via the electrostatic protection circuit 11a is I2. Since the electrostatic protection circuits 11a and 11b are in the semiconductor integrated circuit device 10 and manufactured by the same process, they are equivalent and have the same leakage currents I1 and I2. Further, the DC potentials of the output terminal and the inverted output terminal of the differential amplifier OP are equal. Therefore, by making the resistance values of the resistance elements R1 and R2 equal, the potential fluctuations due to the leakage currents of the inverting input terminal (−) and the non-inverting input terminal (+) of the differential amplifier OP become equal. That is, even when the leakage currents I1 and I2 increase due to a temperature rise or the like, the potential increases at the inverting input terminal (−) and the non-inverting input terminal (+) are equal, and the output terminal and the inverting terminal of the differential amplifier OP are inverted. It is possible to prevent fluctuations in the DC potential of the output terminal. For this reason, the semiconductor integrated circuit device 10 can perform a stable oscillation operation over a wide temperature range. The leakage current also flows through the electrostatic protection circuit 11c. However, since the impedance at the output terminal of the differential amplifier OP is low, the potential at the output terminal does not fluctuate due to the leakage current flowing through the electrostatic protection circuit 11c.

以上の説明では、リーク電流が電源側から流れ込むものとして説明した。一方、リーク電流が接地側に流れ出す場合であっても、反転入力端子(−)および非反転入力端子(+)の電位下降が等しく、同様に差動増幅器OPの出力端子および反転出力端子の直流電位の変動を防ぐことができる。   In the above description, the leak current has been described as flowing from the power source side. On the other hand, even when a leak current flows out to the ground side, the potential drops at the inverting input terminal (−) and the non-inverting input terminal (+) are equal, and similarly, the DC power of the output terminal and the inverting output terminal of the differential amplifier OP. The fluctuation of the position can be prevented.

また、差動増幅器OPの反転出力端子は、半導体集積回路装置10の外部に端子として直接出力されていない。したがって、環境ノイズの多い所で使用したとしても内部回路にノイズの影響を極めて少なくすることができる。無論、外部端子P1から入力されうるノイズは、差動増幅器OPによって増幅される。しかし、差動増幅器OPの周波数上限がシングルエンドの回路で構成される一般の発振回路に比べて1から2桁低く、ノイズに対する感度は鈍く、ノイズの影響は少ない。   Further, the inverting output terminal of the differential amplifier OP is not directly output as a terminal outside the semiconductor integrated circuit device 10. Therefore, even if it is used in a place with a lot of environmental noise, the influence of noise on the internal circuit can be extremely reduced. Of course, noise that can be input from the external terminal P1 is amplified by the differential amplifier OP. However, the upper limit of the frequency of the differential amplifier OP is 1 to 2 orders of magnitude lower than that of a general oscillation circuit constituted by a single-ended circuit.

図2は、本発明の第2の実施例に係る半導体集積回路装置の回路図である。図2において、図1と同一の符号は同一物を表し、その説明を省略する。図2の半導体集積回路装置10aは、図1の抵抗素子R1を2つの直列接続される抵抗素子R3、R4に分割すると共に、抵抗素子R1に相当する抵抗素子R5を差動増幅器OPの非反転入力端子(+)と抵抗素子R3、R4の接続点との間に接続する。この場合、抵抗素子R3、R5の抵抗値を等しくすることが好ましい。   FIG. 2 is a circuit diagram of a semiconductor integrated circuit device according to the second embodiment of the present invention. 2, the same reference numerals as those in FIG. 1 represent the same items, and the description thereof is omitted. The semiconductor integrated circuit device 10a of FIG. 2 divides the resistance element R1 of FIG. 1 into two series-connected resistance elements R3 and R4, and the resistance element R5 corresponding to the resistance element R1 is a non-inversion of the differential amplifier OP. It connects between an input terminal (+) and the connection point of resistive element R3, R4. In this case, it is preferable to make the resistance values of the resistance elements R3 and R5 equal.

このような構成の半導体集積回路装置10aにおいて、第1の実施例と同様に静電保護回路にリーク電流が生じたとする。ここで電源側から静電保護回路11bを介して抵抗素子R3に流れるリーク電流と、電源側から静電保護回路11aを介して抵抗素子R5に流れるリーク電流との値は等しい。したがって、抵抗素子R3、R5の抵抗値を等しくすることで差動増幅器OPの反転入力端子(−)および非反転入力端子(+)におけるリーク電流による電位変動が等しくなる。したがって、第1の実施例と同様に半導体集積回路装置10aは、安定した発振動作を行うことが可能である。   In the semiconductor integrated circuit device 10a having such a configuration, it is assumed that a leakage current is generated in the electrostatic protection circuit as in the first embodiment. Here, the value of the leakage current flowing from the power supply side to the resistance element R3 via the electrostatic protection circuit 11b is equal to the value of the leakage current flowing from the power supply side to the resistance element R5 via the electrostatic protection circuit 11a. Therefore, by making the resistance values of the resistance elements R3 and R5 equal, the potential fluctuations due to the leakage current at the inverting input terminal (−) and the non-inverting input terminal (+) of the differential amplifier OP become equal. Therefore, similarly to the first embodiment, the semiconductor integrated circuit device 10a can perform a stable oscillation operation.

図3は、本発明の第3の実施例に係る半導体集積回路装置の回路図である。図3において、図1と同一の符号は同一物を表し、その説明を省略する。図3の半導体集積回路装置10bは、差動増幅器OPの替わりに反転出力端子を省いた差動増幅器OPaを備え、出力端子を出力OUTとして半導体集積回路装置10aの内部回路に接続する。また、抵抗素子R1に相当する抵抗素子R6を差動増幅器OPaの非反転入力端子(+)とバイアス供給源Vbとの間に接続する。この場合、抵抗素子R1、R6の抵抗値を等しく、かつバイアス供給源Vbの電位と差動増幅器OPaの出力端子の直流電位(振幅中心電位)とを等しくすることが好ましい。   FIG. 3 is a circuit diagram of a semiconductor integrated circuit device according to the third embodiment of the present invention. 3, the same reference numerals as those in FIG. 1 represent the same items, and the description thereof is omitted. A semiconductor integrated circuit device 10b of FIG. 3 includes a differential amplifier OPa in which an inverting output terminal is omitted instead of the differential amplifier OP, and an output terminal is connected to an internal circuit of the semiconductor integrated circuit device 10a as an output OUT. A resistance element R6 corresponding to the resistance element R1 is connected between the non-inverting input terminal (+) of the differential amplifier OPa and the bias supply source Vb. In this case, it is preferable that the resistance values of the resistance elements R1 and R6 are equal, and the potential of the bias supply source Vb is equal to the DC potential (amplitude center potential) of the output terminal of the differential amplifier OPa.

このような構成の半導体集積回路装置10bにおいて、第1の実施例と同様に静電保護回路にリーク電流が生じたとする。ここで電源側から静電保護回路11bを介して抵抗素子R1に流れるリーク電流と、電源側から静電保護回路11aを介して抵抗素子R6に流れるリーク電流との値は等しい。したがって、抵抗素子R1、R6の抵抗値を等しく、かつバイアス供給源Vbの電位と差動増幅器OPaの出力端子の直流電位(振幅中心電位)とを等しくすることで、差動増幅器OPaの反転入力端子(−)および非反転入力端子(+)におけるリーク電流による電位変動が等しくなる。したがって、第1の実施例と同様に半導体集積回路装置10bは、安定した発振動作を行うことが可能である。   In the semiconductor integrated circuit device 10b having such a configuration, it is assumed that a leakage current is generated in the electrostatic protection circuit as in the first embodiment. Here, the value of the leakage current flowing from the power supply side to the resistance element R1 via the electrostatic protection circuit 11b is equal to the value of the leakage current flowing from the power supply side to the resistance element R6 via the electrostatic protection circuit 11a. Therefore, the resistance values of the resistance elements R1 and R6 are made equal, and the potential of the bias supply source Vb is made equal to the direct current potential (amplitude center potential) of the output terminal of the differential amplifier OPa, whereby the inverting input of the differential amplifier OPa. The potential fluctuations due to the leakage current at the terminal (−) and the non-inverting input terminal (+) become equal. Therefore, like the first embodiment, the semiconductor integrated circuit device 10b can perform a stable oscillation operation.

図4は、本発明の第4の実施例に係る半導体集積回路装置の回路図である。図4において、図3と同一の符号は同一物を表し、その説明を省略する。図4の半導体集積回路装置10cは、電源と差動増幅器OPaの非反転入力端子(+)との間に抵抗素子R7を備え、差動増幅器OPaの非反転入力端子(+)と接地との間に抵抗素子R8を備える。この場合、抵抗素子R1の抵抗値と、抵抗素子R7、R8の並列接続の抵抗値を等しく、かつ抵抗素子R7、R8の接続点の電位と差動増幅器OPaの出力端子の直流電位(振幅中心電位)とを等しくすることが好ましい。   FIG. 4 is a circuit diagram of a semiconductor integrated circuit device according to the fourth embodiment of the present invention. 4, the same reference numerals as those in FIG. 3 represent the same items, and the description thereof is omitted. The semiconductor integrated circuit device 10c of FIG. 4 includes a resistance element R7 between the power supply and the non-inverting input terminal (+) of the differential amplifier OPa, and the non-inverting input terminal (+) of the differential amplifier OPa and the ground. A resistance element R8 is provided between them. In this case, the resistance value of the resistance element R1 is equal to the resistance value of the parallel connection of the resistance elements R7 and R8, and the potential at the connection point of the resistance elements R7 and R8 and the DC potential (amplitude center) of the output terminal of the differential amplifier OPa. It is preferable that the potential is equal.

このような構成の半導体集積回路装置10cにおいて、第1の実施例と同様に静電保護回路にリーク電流が生じたとする。ここで電源側から静電保護回路11bを介して抵抗素子R1に流れるリーク電流と、電源側から静電保護回路11aを介して抵抗素子R7、R8に流れるリーク電流との値は等しい。したがって、抵抗素子R1の抵抗値と、抵抗素子R7、R8の並列接続の抵抗値を等しく、かつ抵抗素子R7、R8の接続点の電位と差動増幅器OPaの出力端子の直流電位とを等しくすることで、差動増幅器OPaの反転入力端子(−)および非反転入力端子(+)におけるリーク電流による電位変動が等しくなる。したがって、第3の実施例と同様に半導体集積回路装置10cは、安定した発振動作を行うことが可能である。   In the semiconductor integrated circuit device 10c having such a configuration, it is assumed that a leakage current is generated in the electrostatic protection circuit as in the first embodiment. Here, the value of the leakage current flowing from the power supply side to the resistance element R1 via the electrostatic protection circuit 11b is equal to the value of the leakage current flowing from the power supply side to the resistance elements R7 and R8 via the electrostatic protection circuit 11a. Therefore, the resistance value of the resistance element R1 is equal to the resistance value of the parallel connection of the resistance elements R7 and R8, and the potential at the connection point of the resistance elements R7 and R8 is equal to the DC potential of the output terminal of the differential amplifier OPa. As a result, potential fluctuations due to leakage currents at the inverting input terminal (−) and the non-inverting input terminal (+) of the differential amplifier OPa become equal. Therefore, as in the third embodiment, the semiconductor integrated circuit device 10c can perform a stable oscillation operation.

なお、上記の第3および第4の実施例において、反転出力端子を省いた差動増幅器OPaを用いた例を示した。しかし、これに限定されることなく、反転出力端子を備える差動増幅器OPを用い、非反転入力端子(+)へのバイアスの供給を第3および第4の実施例のように構成してもよいことは言うまでもない。   In the above third and fourth embodiments, the example using the differential amplifier OPa in which the inverting output terminal is omitted is shown. However, the present invention is not limited to this, and the differential amplifier OP having an inverting output terminal may be used to supply the bias to the non-inverting input terminal (+) as in the third and fourth embodiments. Needless to say, it is good.

なお、以上の説明において、反転入力端子に接続される静電保護回路と非反転入力端子に接続される静電保護回路とは、同じものとして説明した。しかしながら、非反転入力端子は外部端子に接続されない端子であるので、外部端子に付ける静電保護回路と同様のリーク特性を持つ回路を非反転入力端子に接続する事も可能である。静電保護回路は、静電エネルギーを消費する目的があるので回路サイズが大きく作られている。静電保護回路と同様のリーク特性を持つ回路を用いれば、その分回路サイズを縮小することで集積度の向上に寄与することができる。   In the above description, the electrostatic protection circuit connected to the inverting input terminal and the electrostatic protection circuit connected to the non-inverting input terminal are described as being the same. However, since the non-inverting input terminal is a terminal that is not connected to the external terminal, a circuit having leakage characteristics similar to the electrostatic protection circuit attached to the external terminal can be connected to the non-inverting input terminal. Since the electrostatic protection circuit has a purpose of consuming electrostatic energy, the circuit size is made large. If a circuit having leakage characteristics similar to that of the electrostatic protection circuit is used, the circuit size can be reduced correspondingly, thereby contributing to improvement in the degree of integration.

なお、前述の特許文献等の各開示を、本書に引用をもって繰り込むものとする。本発明の全開示(請求の範囲を含む)の枠内において、さらにその基本的技術思想に基づいて、実施形態ないし実施例の変更・調整が可能である。また、本発明の請求の範囲の枠内において種々の開示要素の多様な組み合わせないし選択が可能である。すなわち、本発明は、請求の範囲を含む全開示、技術的思想にしたがって当業者であればなし得るであろう各種変形、修正を含むことは勿論である。   It should be noted that the disclosures of the aforementioned patent documents and the like are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

本発明の第1の実施例に係る半導体集積回路装置の回路図である。1 is a circuit diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention. 本発明の第2の実施例に係る半導体集積回路装置の回路図である。FIG. 6 is a circuit diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention. 本発明の第3の実施例に係る半導体集積回路装置の回路図である。FIG. 6 is a circuit diagram of a semiconductor integrated circuit device according to a third example of the present invention. 本発明の第4の実施例に係る半導体集積回路装置の回路図である。FIG. 6 is a circuit diagram of a semiconductor integrated circuit device according to a fourth example of the present invention.

符号の説明Explanation of symbols

10、10a、10b、10c 半導体集積回路装置
11a、11b、11c 静電保護回路
C1、C2 容量素子
I1、I2 リーク電流
OP、OPa 差動増幅器
OUT 出力
P1、P2 外部端子
R1〜R8 抵抗素子
Vb バイアス供給源
XTL 水晶振動子
10, 10a, 10b, 10c Semiconductor integrated circuit devices 11a, 11b, 11c Electrostatic protection circuit C1, C2 Capacitance elements I1, I2 Leakage current OP, OPa Differential amplifier OUT Outputs P1, P2 External terminals R1-R8 Resistance element Vb Bias Supply source XTL Quartz crystal

Claims (7)

外部回路の一端を接続可能とする第1の外部端子と、
前記外部回路の他端を接続可能とする第2の外部端子と、
第1の抵抗素子と、
第2の抵抗素子と、
反転入力端子を前記第1の外部端子および前記第1の抵抗素子の一端に接続し、出力端子を前記第2の外部端子および前記第1の抵抗素子の他端に接続し、非反転入力端子を前記第2の抵抗素子を介してバイアス供給源に接続する差動増幅器と、
前記反転入力端子に接続される第1の静電保護回路と、
前記非反転入力端子に接続される第2の静電保護回路と、
を備え
前記差動増幅器は、反転出力端子をさらに備え、
前記反転出力端子から内部回路に出力信号を出力するように構成し、
前記バイアス供給源を前記反転出力端子とすることを特徴とする半導体集積回路装置。
A first external terminal capable of connecting one end of an external circuit;
A second external terminal enabling connection of the other end of the external circuit;
A first resistance element;
A second resistance element;
An inverting input terminal is connected to the first external terminal and one end of the first resistance element, an output terminal is connected to the second external terminal and the other end of the first resistance element, and a non-inverting input terminal A differential amplifier that connects to a bias source via the second resistive element;
A first electrostatic protection circuit connected to the inverting input terminal;
A second electrostatic protection circuit connected to the non-inverting input terminal;
Equipped with a,
The differential amplifier further includes an inverting output terminal,
It is configured to output an output signal from the inverting output terminal to an internal circuit,
The semiconductor integrated circuit device according to claim to Rukoto and the inverting output terminal of the bias source.
外部回路の一端を接続可能とする第1の外部端子と、
前記外部回路の他端を接続可能とする第2の外部端子と、
第1の抵抗素子と、
第2の抵抗素子と、
反転入力端子を前記第1の外部端子および前記第1の抵抗素子の一端に接続し、出力端子を前記第2の外部端子および前記第1の抵抗素子の他端に接続し、非反転入力端子を前記第2の抵抗素子を介してバイアス供給源に接続する差動増幅器と、
前記反転入力端子に接続される第1の静電保護回路と、
前記非反転入力端子に接続される第2の静電保護回路と、
を備え
前記バイアス供給源を前記第1の抵抗素子の所定の分割点とすることを特徴とする半導体集積回路装置。
A first external terminal capable of connecting one end of an external circuit;
A second external terminal enabling connection of the other end of the external circuit;
A first resistance element;
A second resistance element;
An inverting input terminal is connected to the first external terminal and one end of the first resistance element, an output terminal is connected to the second external terminal and the other end of the first resistance element, and a non-inverting input terminal A differential amplifier that connects to a bias source via the second resistive element;
A first electrostatic protection circuit connected to the inverting input terminal;
A second electrostatic protection circuit connected to the non-inverting input terminal;
Equipped with a,
The semiconductor integrated circuit device according to claim to Rukoto a predetermined division point of the bias supply said first resistor element.
前記差動増幅器は、反転出力端子をさらに備え、
前記反転出力端子から内部回路に出力信号を出力するように構成することを特徴とする請求項記載の半導体集積回路装置。
The differential amplifier further includes an inverting output terminal,
3. The semiconductor integrated circuit device according to claim 2 , wherein an output signal is output from the inverting output terminal to an internal circuit.
前記第1の抵抗素子は、前記所定の分割点によって第3及び第4の抵抗素子に分割され、  The first resistance element is divided into third and fourth resistance elements by the predetermined dividing point;
前記反転入力端子は、前記第3の抵抗素子の一端に接続され、  The inverting input terminal is connected to one end of the third resistance element,
前記出力端子は、前記第4の抵抗素子の一端に接続され、  The output terminal is connected to one end of the fourth resistance element,
前記第2の抵抗素子は、前記第3の抵抗素子の他端および前記第4の抵抗素子の他端に接続され、  The second resistance element is connected to the other end of the third resistance element and the other end of the fourth resistance element,
前記第2の抵抗素子の抵抗値は、前記第3の抵抗素子の抵抗値に等しいことを特徴とする請求項2または3に記載の半導体集積回路装置。  4. The semiconductor integrated circuit device according to claim 2, wherein a resistance value of the second resistance element is equal to a resistance value of the third resistance element.
前記出力端子に接続される第3の静電保護回路をさらに備えることを特徴とする請求項1乃至4のいずれか一記載の半導体集積回路装置。   5. The semiconductor integrated circuit device according to claim 1, further comprising a third electrostatic protection circuit connected to the output terminal. 前記外部回路は、固体振動子を含む回路であって、発振回路として機能することを特徴とする請求項1乃至5のいずれか一記載の半導体集積回路装置。   6. The semiconductor integrated circuit device according to claim 1, wherein the external circuit is a circuit including a solid vibrator and functions as an oscillation circuit. 前記第1の外部端子に接続される第1の容量素子と、  A first capacitive element connected to the first external terminal;
前記第2の外部端子に接続される第2の容量素子と、  A second capacitive element connected to the second external terminal;
をさらに備えることを特徴とする請求項1乃至6のいずれか一記載の半導体集積回路装置。  The semiconductor integrated circuit device according to claim 1, further comprising:
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