JP5061793B2 - ELECTRIC CIRCUIT, ELECTRIC CIRCUIT DRIVING METHOD, DISPLAY DEVICE, AND ELECTRONIC DEVICE. - Google Patents

Description

  The present invention relates to a technique for controlling a threshold voltage of a transistor.

A thin film transistor has lower electron mobility than a transistor using a single crystal semiconductor layer. In Patent Document 1, a voltage applied to a back gate of each of P-channel and N-channel thin film transistors is controlled in order to operate an inverter circuit composed of P-channel and N-channel thin film transistors at high speed. A configuration is disclosed.
Japanese Patent Application Laid-Open No. 9-11879

  However, since the back gate voltage of each thin film transistor is individually controlled by the P-channel type and the N-channel type under the configuration of Patent Document 1, an inverter circuit and peripheral elements (for example, connected to each back gate) There is a problem that the configuration of the wiring is complicated. In view of the above circumstances, an object of the present invention is to solve the problem of speeding up the operation of an inverter circuit with a simple configuration.

  In order to solve the above problems, an electric circuit according to the present invention includes a P-channel first transistor and an N-channel second transistor connected in series between a first power supply line and a second power supply line. A first capacitor interposed between the first signal supply point (for example, signal supply point P1 in FIG. 1) and the channel contact region of the first transistor, and the first signal supply point and the channel contact region of the second transistor And an inverter circuit including a second capacitor interposed therebetween, transitioning to a low level before the input signal to the inverter circuit falls from a high level and transitioning to a high level before the input signal rises from a low level The first threshold control signal (for example, the threshold control signal SA in FIG. 1) is supplied to the first signal supply point. According to the above configuration, the potentials of the channel contact regions of both the first transistor and the second transistor (and further, each of the first transistor and the second transistor are controlled by the first threshold control signal supplied to the first signal supply point. Since the threshold voltage is set, the configuration of the electric circuit is simplified compared to the configuration in which individual signals are supplied to control the potentials of the channel contact regions of the first transistor and the second transistor. . In addition, since the first threshold control signal transitions to the low level before the input signal falls from the high level and transitions to the high level before the input signal rises from the low level, a change in the level of the input signal is output. It is possible to reduce the delay until the signal is reflected and to increase the speed of change of the output signal (to shorten the time until the output signal reaches the high level or the low level). In addition, the specific example of the above aspect is later mentioned as 1st Embodiment.

  An electric circuit according to a preferred aspect of the present invention is a signal generation circuit that generates a first threshold control signal from an input signal or output signal of an inverter circuit (for example, the signal generation circuit 42 in FIG. 8 or the signal generation circuit 44 in FIG. 10). It comprises. According to the above aspect, the configuration of the electric circuit and the peripheral circuit is simplified as compared with the configuration in which the threshold control signal is generated regardless of the input signal and the output signal. Further, there is an advantage that it is easy to ensure synchronization between the input signal or output signal and the threshold control signal. In addition, the specific example of the above aspect is later mentioned as 2nd Embodiment.

  An electric circuit according to a preferred aspect of the present invention includes an inverter circuit, a P-channel third transistor interposed between the first power supply line and the first transistor, and between the second power supply line and the second transistor. An N-channel fourth transistor interposed between the second transistor, a third capacitor interposed between the second signal supply point (for example, signal supply point P2 in FIG. 12) and the channel contact region of the third transistor, and a third signal supply A clocked inverter circuit including a point (for example, a signal supply point P3 in FIG. 12) and a fourth capacitor interposed between the channel contact region of the fourth transistor, and the gate of the third transistor has a first control signal. (For example, the control signal C in FIG. 12) is supplied, and the second control signal having a waveform obtained by inverting the first control signal (for example, the control signal XC in FIG. 12) is supplied to the gate of the fourth transistor. A second threshold control signal that transitions to a low level before the first control signal falls from a high level and that transitions to a high level before the first control signal rises from a low level (for example, the threshold control signal SB in FIG. 12). Is supplied to the second signal supply point, transitions to a high level before the second control signal rises from the low level, and shifts to a low level before the second control signal falls from the high level. A signal (for example, the threshold control signal XSB in FIG. 12) is supplied to the third signal supply point. According to the above aspect, the operation of the third transistor is speeded up by supplying the second threshold control signal to the second signal supply point, and the fourth transistor is supplied by supplying the third threshold control signal to the third signal supply point. Therefore, the clocked inverter circuit can be quickly controlled between the operating state and the high impedance state. A specific example of this embodiment will be described later as a third embodiment.

  An electrical circuit according to a preferred aspect of the present invention includes a first signal generation circuit that generates a second threshold control signal from one of the first control signal and the second control signal, and the other of the first control signal and the second control signal. And a second signal generation circuit for generating a third threshold control signal. According to the above configuration, the configuration of the electric circuit and the peripheral circuit is simplified as compared with the configuration in which the second threshold control signal and the third threshold control signal are generated regardless of the first control signal and the second control signal. Is done. A specific example of this embodiment will be described later as a fourth embodiment.

  The electric circuit according to the present invention includes a first clocked inverter circuit (for example, clocked inverter circuit R1 in FIG. 17) including a first inverter circuit, a second inverter circuit, and an output section of the first clocked inverter circuit. A second clocked inverter circuit (for example, clocked inverter circuit R2 in FIG. 17) connected to the output section, an input section is connected to the output section of the first clocked inverter circuit, and an output section is the second clocked inverter. A third inverter circuit (for example, the inverter circuit Q3 in FIG. 17) connected to the input of the circuit, and each of the first inverter circuit, the second inverter circuit, and the third inverter circuit includes a first power supply line and A P-channel first transistor and an N-channel second transistor connected in series with the second power supply line; An inverter circuit including a first capacitor interposed between the supply point and the channel contact region of the first transistor, and a second capacitor interposed between the first signal supply point and the channel contact region of the second transistor. A first threshold value control signal that transitions to a low level before the input signal falls from the high level and also transitions to a high level before the input signal rises from the low level is supplied to the first signal supply point of the inverter circuit Is done. According to the above configuration, the potentials of the channel contact regions of the first transistor and the second transistor are controlled by supplying the first threshold control signal to the first signal supply point of each inverter circuit. The configuration of the electric circuit is simplified as compared with the case where individual signals are supplied to supply the potentials of the channel contact regions of the transistors and the second transistors.

  In a preferred aspect of the present invention, each of the first clocked inverter circuit and the second clocked inverter circuit includes a P-channel third transistor interposed between the first power supply line and the first transistor, An N-channel fourth transistor interposed between the power supply line and the second transistor, a third capacitor interposed between the second signal supply point and the channel contact region of the third transistor, and a third signal supply point And a fourth capacitor interposed between the first transistor and the channel contact region of the fourth transistor, and a first control is provided to each gate of the third transistor of the first clocked inverter circuit and the fourth transistor of the second clocked inverter circuit. And a fourth transistor of the first clocked inverter circuit and a third transistor of the second clocked inverter circuit. A second control signal having a waveform obtained by inverting the first control signal is supplied to each gate. The first control signal transitions to a low level before falling from the high level, and the first control signal rises from the low level. The second threshold control signal that has previously transitioned to the high level is supplied to the second signal supply point of the first clocked inverter circuit and the third signal supply point of the second clocked inverter circuit, and the second control signal is at the low level. The third threshold control signal that transitions to the high level before rising from the second level and transitions to the low level before the second control signal falls from the high level is the third signal supply point of the first clocked inverter circuit and the second It is supplied to the second signal supply point of the clocked inverter circuit. According to the above aspect, the common second threshold control signal is supplied to the second signal supply point of the first clocked inverter circuit and the third signal supply point of the second clocked inverter circuit, and the first clocked inverter circuit A common third threshold value control signal is supplied to the third signal supply point and the second signal supply point of the second clocked inverter circuit. Therefore, the configuration of the electric circuit and the peripheral circuit is different from the configuration in which separate signals are supplied to the second signal supply point and the third signal supply point of each of the first clocked inverter circuit and the second clocked inverter circuit. There is an advantage that it is simplified. A specific example of this aspect will be described later as a fifth embodiment.

  A display device according to a preferred aspect of the present invention includes a shift register circuit in which a plurality of electric circuits (latch circuits) exemplified above are connected in cascade, and a plurality of driving signals (for example, based on output signals of the respective electric circuits). A driving circuit (for example, the scanning line driving circuit 74 and the data line driving circuit 76 in FIG. 20) that sequentially outputs the scanning signals Y1 to Ym and the data signals X1 to Xn in FIG. 20 and each driving signal generated by the driving circuit. And a plurality of pixels driven accordingly. According to the above configuration, since the operation of each inverter circuit is speeded up, high quality display is possible. The display device of the present invention is suitably employed in various electronic devices such as personal computers and mobile phones.

  The present invention is also specified as a method of driving an electric circuit. For example, one driving method includes a P-channel type first transistor and an N-channel type second transistor connected in series between a first power supply line and a second power supply line, a first signal supply point, An electric circuit including an inverter circuit including a first capacitor interposed between the channel contact region of one transistor and a second capacitor interposed between the first signal supply point and the channel contact region of the second transistor. A first threshold control signal is a driving method, wherein the first threshold value control signal changes to a low level before the input signal to the inverter circuit falls from the high level and changes to the high level before the input signal rises from the low level. Supply to the signal supply point.

  A driving method according to another aspect of the present invention includes a first clocked inverter circuit including a first inverter circuit, a second inverter circuit, and an output unit connected to the output unit of the first clocked inverter circuit. A second clocked inverter circuit, and a third inverter circuit having an input portion connected to the output portion of the first clocked inverter circuit and an output portion connected to the input portion of the second clocked inverter circuit. Each of the first inverter circuit, the second inverter circuit, and the third inverter circuit includes a P-channel type first transistor and an N-channel type transistor connected in series between the first power supply line and the second power supply line. A second transistor; a first capacitor interposed between the first signal supply point and the channel contact region of the first transistor; a first signal supply point and a second transistor; A method for driving an electric circuit including a second capacitor interposed between the first and second inverter circuits, wherein each of the first inverter circuit, the second inverter circuit, and the third inverter circuit is input to the inverter circuit. A first threshold control signal that transitions to a low level before the signal falls from the high level and transitions to a high level before the input signal rises from the low level is supplied to the first signal supply point of the inverter circuit.

  A preferred embodiment of the present invention will be described with reference to the drawings. In addition, in each following form, the same code | symbol is attached | subjected to the element with an equivalent effect | action and function.

<A: First Embodiment>
FIG. 1 is a circuit diagram showing a configuration of an electric circuit 100 according to the first embodiment of the present invention. The electric circuit 100 includes an inverter circuit Q including a P-channel transistor TR1 and an N-channel transistor TR2. The transistors TR1 and TR2 are MOS (Metal Oxide Semiconductor) type thin film transistors.

  Transistors TR1 and TR2 are connected in series between a power supply line L1 supplied with a power supply potential VDD and a power supply line L2 supplied with a ground potential GND. More specifically, the source S of the transistor TR1 is connected to the power supply line L1, and the source S of the transistor TR2 is connected to the power supply line L2. The drains D of the transistors TR1 and TR2 are electrically connected to the output section (output terminal) POUT.

  The gate G of the transistor TR1 and the gate G of the transistor TR2 are electrically connected to the input unit (input terminal) PIN. An input signal SIN is supplied from the control circuit 30 to the input section PIN. In the above configuration, the output signal SOUT having a waveform obtained by inverting the input signal SIN is output from the output unit POUT. That is, when the input signal SIN is at a high level (power supply potential VDD), the transistor TR2 is turned on to output a low level (ground potential GND) output signal SOUT to the output unit POUT. When SIN is at a low level (ground potential GND), the transistor TR1 is turned on to output a high level (power supply potential VDD) output signal SOUT to the output section POUT.

  FIG. 2 is a plan view showing the structure of the P-channel transistor TR1. The structure of the N-channel transistor TR2 is the same as that illustrated in FIG. 2 except that the conductivity type (polarity) of each element is reversed. Therefore, illustration and description of the configuration of the transistor TR2 are omitted.

  The transistor TR1 has a semiconductor layer 12 (for example, a polysilicon film body) formed on the surface of an insulating substrate. A gate electrode 13 (gate G in FIG. 1) is formed so as to face the semiconductor layer 12 with a gate insulating film (not shown) covering the semiconductor layer 12 interposed therebetween. A source region 12 s, a drain region 12 d, and a channel contact region A are formed in the semiconductor layer 12 after forming the gate electrode 13. The source region 12s and the drain region 12d are regions into which P-type impurities are introduced. The channel contact region A is a region into which an N-type impurity having a conductivity type opposite to that of the channel of the transistor TR1 is introduced.

  An interlayer insulating layer (not shown) is formed so as to cover the semiconductor layer 12 and the gate electrode 13. A plurality of through holes (H1, H2, H3) are formed in the interlayer insulating layer. A source electrode 14 (source S in FIG. 1) is connected to the source region 12s of the semiconductor layer 12 through a through hole H1, and a drain electrode 15 (drain D in FIG. 1) is connected to the drain region 12d through a through hole H2. Is connected. An electrode (hereinafter referred to as “threshold control electrode”) 16 is connected to the channel contact region A of the semiconductor layer 12 through a through hole H 3.

  As shown in FIG. 1, the inverter circuit Q has a signal supply point P1. A signal (hereinafter referred to as “threshold control signal”) SA for controlling the threshold voltage VTH_P of the transistor TR1 and the threshold voltage VTH_N of the transistor TR2 is supplied from the control circuit 30 to the signal supply point P1.

  As shown in FIGS. 1 and 2, a capacitor C1 is interposed between the channel contact region A (threshold control electrode 16) of the transistor TR1 and the signal supply point P1. Similarly, a capacitor C2 is interposed between the channel contact region A (threshold control electrode 16) of the transistor TR2 and the signal supply point P1. That is, the channel contact regions A of the transistors TR1 and TR2 are capacitively coupled to the common signal supply point P1.

  Between the source S of the transistor TR1 and the channel contact region A, a diode d1 composed of a PN junction therebetween is accompanied (parasitic). Therefore, the fluctuation of the potential of the channel contact region A of the transistor TR1 is limited to a range not lower than the potential obtained by subtracting the threshold voltage of the diode d1 from the threshold potential VDD. A diode d2 is also attached between the source S of the transistor TR2 and the channel contact region A. Therefore, the fluctuation of the potential of the channel contact region A of the transistor TR2 is restricted to a range that does not exceed the potential obtained by adding the threshold voltage of the diode d2 to the ground potential GND. A configuration in which the diodes d1 and d2 are formed independently of the transistors TR1 and TR2 is also employed.

  Next, for each of the transistors TR1 and TR2, the gate voltage VG applied to the gate G, the drain current ID flowing between the source S and the drain D, and the voltage of the channel contact region A (hereinafter referred to as “body potential”) VB The relationship will be described. FIG. 3 is a graph showing the relationship between the gate voltage VG (horizontal axis) and the drain current ID (vertical axis) in the P-channel transistor TR1 for each body potential VB1 of the transistor TR1. Similarly, FIG. 4 is a graph showing the relationship between the gate voltage VG and the drain current ID in the N-channel transistor TR2 for each body potential VB2 of the transistor TR2.

  As shown in FIGS. 3 and 4, each of the threshold voltage VTH_P of the transistor TR1 and the threshold voltage VTH_N of the transistor TR2 decreases as the body potential VB (VB1, VB2) increases (increases as the body potential VB decreases). To do). Therefore, the P-channel transistor TR1 is more likely to be turned on as the body potential VB1 of its own channel contact region A is lower, and the N-channel transistor TR2 has a higher body potential VB2 of its own channel contact region A. It is easier to transition to the on state.

  FIG. 5 is a timing chart showing the operation of the inverter circuit Q. The input signal SIN periodically changes from one of the high level and the low level to the other. The threshold control signal SA sequentially changes from one of the high level and the low level to the other in the same cycle as the input signal SIN. As shown in FIG. 5, the threshold control signal SA transitions to the low level at a time before the time point ta1 at which the input signal SIN starts to fall from the high level, and from the time point tb1 at which the input signal SIN starts to rise from the low level. Transitions to a high level at the time before.

  As illustrated in FIG. 1, the channel contact region A of each of the transistors TR1 and TR2 is capacitively coupled to the signal supply point P1 to which the threshold control signal SA is supplied. Therefore, the body potential VB1 of the transistor TR1 and the body potential VB2 of the transistor TR2 change in conjunction with the threshold control signal SA as described below.

  When threshold control signal SA falls to a low level, body potential VB1 and body potential VB2 fall. Since the transistor d1 is accompanied by the diode d1, the body potential VB1 converges to a potential V1L which is lower than the power supply potential VDD by the threshold voltage as shown in FIG. Further, the body potential VB2 of the transistor TR2 changes from the immediately preceding potential V2H to a potential V2L that is lower by the amount of change in the voltage of the threshold control signal SA. That is, as shown in FIG. 5, during the period TL starting from the time s1 before the input signal SIN falls, the body potential VB1 maintains the potential V1L and the body potential VB2 maintains the potential V2L. The period TL includes a period TA from a time point ta1 at which the input signal SIN starts to fall to a time point ta2 at which the output signal SOUT completely reaches the high level (power supply potential VDD).

^
On the other hand, when the threshold control signal SA rises to a high level, the body potential VB1 and the body potential VB2 rise. The body potential VB1 of the transistor TR1 changes from the previous potential V1L to a potential V1H that is higher by the amount of change in the threshold control signal SA. Since the transistor TR2 is accompanied by the diode d2, the body potential VB2 converges to a potential V2H that is higher than the ground potential GND by the threshold voltage of the diode d2. That is, as shown in FIG. 5, in the period TH starting from the time s2 before the input signal SIN rises, the body potential VB1 maintains the potential V1H and the body potential VB2 maintains the potential V2H. The period TH includes a period TB from time tb1 at which the input signal SIN starts to rise to time tb2 at which the output signal SOUT completely reaches the low level (ground potential GND).

  As described above, the body potential VB1 and the body potential VB2 are set to low levels (V1L, V2L) within the period TA, so that the threshold voltage VTH_P of the transistor TR1 is set as described above with reference to FIGS. The threshold voltage VTH_N of the transistor TR2 changes to the positive polarity side as compared with the case where the body potential VB1 and the body potential VB2 are zero (ground potential GND). Therefore, the P-channel transistor TR1 is likely to transition to the on state with respect to the decrease in the voltage of the input signal SIN. Now, the threshold voltage (hereinafter referred to as “reference threshold voltage”) VC of the inverter circuit Q when the body potential VB1 and the body potential VB2 are zero (ground potential GND) is used as the center voltage (VDD / 2) of the amplitude of the input signal SIN. Then, the substantial threshold voltage of the inverter circuit Q when the threshold control signal SA is changed to the low level is controlled to a voltage VH higher than the reference threshold voltage VC. That is, at the time point u1 when the input signal SIN drops from the high level to the voltage VH, the transistor TR1 is turned on and the output signal SOUT starts to rise from the low level.

  On the other hand, in the period TB, the body potential VB1 and the body potential VB2 are set high, so that the threshold voltage VTH_P of the transistor TR1 and the threshold voltage VTH_N of the transistor TR2 change to the negative polarity side. The transistor TR2 is likely to transition to the on state with respect to the increase in the voltage of the input signal SIN. That is, the substantial threshold voltage of the inverter circuit Q is controlled to a voltage VL that is lower than the reference threshold voltage VC. Accordingly, at the time point u2 when the input signal SIN rises from the low level to the voltage VL, the transistor TR2 is turned on and the output signal SOUT starts to fall from the high level.

  As described above, in this embodiment, since the common threshold value control signal SA is supplied to the signal supply point P1 where the channel contact regions A of the transistors TR1 and TR2 are capacitively coupled, the transistors TR1 and TR2 There is an advantage that the configuration of the inverter circuit Q is simplified as compared with a configuration in which each threshold voltage is controlled by an individual signal. Further, as described in detail below, there is an effect that the operation of the inverter circuit Q is speeded up.

  FIG. 6 is a timing chart showing the relationship between the input signal SIN and the output signal SOUT when no voltage is applied to the channel contact regions A of the transistors TR1 and TR2 (hereinafter referred to as “comparative 1”). In contrast 1, the transistor TR1 does not transition to the ON state until the time point v1 when the input signal SIN decreases from the high level and reaches the reference threshold voltage VC. Similarly, the transistor TR2 does not transition to the ON state until the time point v2 when the input signal SIN rises from the low level and reaches the reference threshold voltage VC. As illustrated in FIG. 5, according to the present embodiment, the time point u1 when the input signal SIN reaches the voltage VH (the time point before the time point v1 in FIG. 6) and the time point u2 when the input signal SIN reaches the voltage VL ( The voltage of the output signal SOUT starts to change at a time point before the time point v2 in FIG. That is, according to this embodiment, it is possible to reduce the delay until the change in the input signal SIN is reflected in the output signal SOUT.

  As shown in FIG. 3, since the drain current ID of the transistor TR1 increases as the body potential VB1 decreases, the body potential VB1 is set to the potential V1L in the period TA. The amount of drain current ID flowing through the transistor TR1 during the voltage drop (the driving capability of the transistor TR1) increases as compared with the comparative 1. As described above, the drive capability of the transistor TR1 is increased, so that the time Δ1 from when the voltage of the output signal SOUT starts to rise until it reaches the high level is shortened as compared with the proportional 1 (the output signal SOUT is quickly changed). To change). Similarly, during the period TB, the body potential VB2 is set to the potential V2H, so that the driving capability of the transistor TR2 increases (the drain current ID of the transistor TR2 increases), so that the voltage of the output signal SOUT starts to decrease. The time Δ2 to reach the level is shortened compared with the proportional 1. As described above, according to the present embodiment, since the delay at the time when the output signal SOUT starts to change is reduced and the speed of change of the output signal SOUT is increased, the inverter circuit Q can be operated at high speed.

  Next, FIG. 7 shows a configuration in which the channel contact region A of the transistor TR1 is connected to the power supply line L2 (ground potential GND) and the channel contact region A of the transistor TR2 is connected to the power supply line L1 (power supply potential VDD). 2 is a timing chart showing the relationship between the input signal SIN and the output signal SOUT in “proportional 2”. In contrast 2, since the drive capability (current amount of drain current ID) of both transistor TR1 and transistor TR2 increases, the time from when the voltage of output signal SOUT starts to change until it reaches high level or low level ( Δ1, Δ2) is shorter than the proportional 1 as in the present embodiment. However, in order to equalize the rise and fall delays of the output signal SOUT with respect to the input signal SIN under the configuration of the proportional 2, the threshold voltage VTH_P of the transistor TR1 and the threshold voltage VTH_N of the transistor TR2 are set to the same voltage (reference It is necessary to set the threshold voltage VC). That is, the delay amount until the change of the input signal SIN is reflected in the output signal SOUT is equal to the proportional 1. Therefore, according to this embodiment, there is an advantage that the delay of the output signal SOUT with respect to the input signal SIN is suppressed as compared with the proportional 2. In contrast 2, when the input signal SIN is in the vicinity of the reference threshold voltage VC, a through current flows from the power supply line L1 to the power supply line L2 via the transistor TR1 and the transistor TR2. In this embodiment, the threshold voltage VTH_P of the transistor TR1 and the threshold voltage VTH_N of the transistor TR2 are set to different voltage values. Therefore, the through current flowing through the transistors TR1 and TR2 is reduced, and the power consumption in the inverter circuit Q is reduced. There is an advantage that it can be reduced more than the comparative 2.

<B: Second Embodiment>
In the first embodiment, the configuration in which the threshold control signal SA is supplied from the control circuit 30 is exemplified. The threshold control signal SA in the second embodiment of the present invention is generated from the output signal SOUT and the input signal SIN of the inverter circuit Q.

(1) First aspect
The electric circuit 101 illustrated in FIG. 8 has a configuration in which a signal generation circuit 42 is added to the inverter circuit Q of the first embodiment. The signal generation circuit 42 generates a threshold control signal SA from the output signal SOUT. The relationship between the output signal SOUT and the threshold control signal SA is the same as in the first embodiment. The signal generation circuit 42 of this embodiment is a circuit (delay circuit) that generates the threshold control signal SA by delaying the output signal SOUT. For example, a signal generation circuit 42 having a configuration in which a resistor 421 and a capacitor 423 are connected as shown in part (A) of FIG. 9, or two inverter circuits 425 are connected in series as shown in part (B) of FIG. The signal generation circuit 42 is preferably employed.

(2) Second aspect
The electric circuit 102 illustrated in FIG. 10 has a configuration in which a signal generation circuit 44 is added to the inverter circuit Q of the first embodiment. The signal generation circuit 44 generates a threshold control signal SA from the input signal SIN. The signal generation circuit 44 of this embodiment includes a delay circuit 441 and an inverter circuit 443. The delay circuit 441 generates the signal S0 by delaying the input signal SIN. The signal S0 is a signal delayed in phase by 90 ° with respect to the input signal SIN as shown in FIG. The inverter circuit 443 generates the threshold generation signal SA by inverting the level of the signal S0 and supplies it to the signal supply point P1. Accordingly, as shown in FIG. 11, the threshold generation signal SA is a signal having a waveform whose phase is advanced by 90 ° with respect to the input signal SIN. It is also preferable to generate the threshold control signal SA by supplying the signal S0 generated separately from the input signal SIN from the control circuit 30 to the inverter circuit 443.

<C: Third Embodiment>
FIG. 12 is a circuit diagram showing a configuration of the electric circuit 103 according to the third embodiment of the present invention. The electric circuit 103 includes a clocked inverter circuit R in which a P-channel transistor TR3 and an N-channel transistor TR4 are added to the inverter circuit Q similar to that of the first embodiment. The transistor TR3 is interposed between the source S of the transistor TR1 and the power supply line L1, and the transistor TR4 is interposed between the source S of the transistor TR2 and the power supply line L2. Each of the transistor TR3 and the transistor TR4 is a MOS type thin film transistor including the channel contact region A (threshold control terminal) similarly to the transistors TR1 and TR2.

  A control signal C is supplied from the control circuit 30 to the gate G of the transistor TR3. A control signal XC having a waveform obtained by inverting the level of the control signal C is supplied from the control circuit 30 to the gate G of the transistor TR4. As shown in FIG. 13, the control signal C and the control signal XC are clock signals that periodically change from one of a high level and a low level to the other. As in the relationship of the control signal XC with respect to the control signal C, “X” is added below to the head of the sign of the signal obtained by inverting the level of the specific signal.

  As shown in FIG. 12, a capacitor C3 is interposed between the signal supply point P2 and the channel contact region A (threshold control electrode 16) of the transistor TR3. A threshold control signal SB is supplied from the control circuit 30 to the signal supply point P2. A capacitor C4 is interposed between the signal supply point P3 and the channel contact region A (threshold control electrode 16) of the transistor TR4. A threshold value control signal XSB having a waveform obtained by inverting the level of the threshold value control signal SB is supplied from the control circuit 30 to the signal supply point P3. The relationship between the control signal C and the threshold control signal SB and the relationship between the control signal XC and the threshold control signal XSB are the same as the relationship between the input signal SIN and the threshold control signal SA in the first embodiment. That is, as shown in FIG. 13, the threshold control signal SB transitions to a low level before the control signal C falls and transitions to a high level before the control signal C rises. Further, the threshold control signal XSB changes to a low level before the control signal XC falls and also changes to a high level before the control signal XC rises. Similar to the transistors TR1 and TR2, a diode d3 is attached between the source S of the transistor TR3 and the channel contact region A, and a diode d4 is attached between the source S of the transistor TR4 and the channel contact region A. .

  Since the signal supply point P2 and the channel contact region A of the transistor TR3 are capacitively coupled via the capacitor C3, when the threshold control signal SB transitions to the low level, the body potential VB3 of the transistor TR3 changes together with the threshold control signal SB. The potential is set to V1L. Therefore, as shown in FIG. 13, the transistor TR3 is quickly turned on when the control signal C decreases and reaches the voltage VH. Since the signal supply point P3 and the channel contact region A of the transistor TR4 are capacitively coupled via the capacitor C4, the body potential VB4 of the transistor TR4 is set to the potential V2H when the threshold control signal XSB transitions to the high level. Therefore, as shown in FIG. 13, the transistor TR4 is quickly turned on when the control signal XC rises and reaches the voltage VL. That is, the clocked inverter circuit R is controlled to a state (hereinafter referred to as “operation state”) that operates as an inverter circuit in the same manner as the first embodiment.

  On the other hand, when the threshold control signal SB transitions to the high level, the body potential VB3 of the transistor TR3 changes to the potential V1H. Therefore, when the control signal C rises and reaches the voltage VL, the transistor TR3 is turned off. Further, when the threshold control signal XSB transitions to the low level, the body potential VB4 of the transistor TR4 changes to the potential V2L. Therefore, when the control signal XC decreases and reaches the voltage VH, the transistor TR4 is turned off. That is, as shown in FIG. 13, the output part POUT of the clocked inverter circuit R is in a high impedance state (Hi-Z).

  As described above, in this embodiment, before the control signal C or the control signal XC reaches the reference threshold voltage VC, the transistors TR3 and TR4 are quickly controlled to be turned on or off. Therefore, there is an advantage that the operating state and the high impedance state of the clocked inverter circuit R can be switched quickly compared with the configuration in which no voltage is applied to the channel contact region A of the transistor TR3 or the transistor TR4.

<D: Fourth Embodiment>
In the third embodiment, the configuration in which the threshold control signal SB and the threshold control signal XSB are supplied from the control circuit 30 is exemplified. In the fourth embodiment of the present invention, the threshold control signal SB and the threshold control signal XSB are generated from the control signal C and the control signal XC.

(1) First aspect
The electric circuit according to the first aspect includes the clocked inverter circuit R of the third embodiment and the signal generation circuit 62A and the signal generation circuit 62B of FIG. The signal generation circuit 62A generates the threshold control signal SB by delaying and inverting the control signal C. Similarly, the signal generation circuit 62B generates the threshold control signal XSB by delaying and inverting the control signal XC. As the signal generation circuit 62A and the signal generation circuit 62B, for example, an inverter circuit is preferably employed.

(2) Second aspect
The electric circuit according to the second aspect includes the clocked inverter circuit R of the third embodiment and the signal generation circuit 64A and the signal generation circuit 64B of FIG. The signal generation circuit 64A generates the threshold control signal SB by delaying the control signal XC. Similarly, the signal generation circuit 64B generates the threshold control signal XSB by delaying the control signal C. As the signal generation circuit 64A and the signal generation circuit 64B, for example, a circuit in which a resistor 641 and a capacitor 643 are connected as shown in part (A) of FIG. 16, or two inverters as shown in part (B) of FIG. A circuit in which the circuit 645 is connected in series is preferably employed.

<E: Fifth Embodiment>
FIG. 17 is a circuit diagram showing a configuration of an electric circuit 104 according to the fifth embodiment of the present invention. The electric circuit 104 is a latch circuit in which two clocked inverter circuits R (R1, R2) similar to the third embodiment and an inverter circuit Q3 similar to the first embodiment are combined. The inverter circuit Q1 included in the clocked inverter circuit R1 and the inverter circuit Q2 included in the clocked inverter circuit R2 have the same configuration as the inverter circuit Q3. In FIG. 17, the diodes d1 to d4 associated with the transistors TR1 to TR4 are not shown for convenience.

  The output part POUT of the clocked inverter circuit R1 is connected to the output part POUT of the clocked inverter circuit R2 and the input part PIN of the inverter circuit Q3. The output part POUT of the inverter circuit Q3 is connected to the input part PIN of the clocked inverter circuit R2. A threshold control signal SA is supplied from the control circuit 30 to the signal supply point P1 of the clocked inverter circuit R1. A threshold control signal SA obtained by delaying the output signal SOUT output from its output unit POUT by the signal generation circuit 42 of FIG. 8 is supplied to the signal supply point P1 of each of the clocked inverter circuit R2 and the inverter circuit Q3. Is done. Therefore, the operation of the inverter circuit Q (Q1, Q2, Q3) can be speeded up as in the first embodiment.

  A control signal C is commonly supplied to the gates G of the P-channel type transistor TR3 of the clocked inverter circuit R1 and the N-channel type transistor TR4 of the clocked inverter circuit R2. A control signal XC is commonly supplied to the gates G of the N-channel type transistor TR4 of the clocked inverter circuit R1 and the P-channel type transistor TR3 of the clocked inverter circuit R2. The waveforms of the control signal C and the control signal XC are the same as in the third embodiment.

  In the above configuration, when the control signal C transits to a low level and the control signal XC transits to a high level, the clocked inverter circuit R1 is controlled to the operating state and the clocked inverter circuit R2 enters a high impedance state. Therefore, an output signal SOUT corresponding to the input signal SIN input to the clocked inverter circuit R1 is output from the inverter circuit Q3. On the other hand, when the control signal C transits to a high level and the control signal XC transits to a low level, the clocked inverter circuit R1 is controlled to a high impedance state and the clocked inverter circuit R2 enters an operating state. Therefore, the input signal SIN when the control signal C transits to the high level is output as the output signal SOUT and is held (latched) by the inverter circuit Q3 and the clocked inverter circuit R2.

  The threshold control signal SB is commonly supplied to the signal supply point P2 of the clocked inverter circuit R1 and the signal supply point P3 of the clocked inverter circuit R2. The threshold control signal XSB is commonly supplied to the signal supply point P3 of the clocked inverter circuit R1 and the signal supply point P2 of the clocked inverter circuit R2. The relationship between the control signal C and the threshold control signal SB and the relationship between the control signal XC and the threshold control signal XSB are the same as in the third embodiment. Therefore, similarly to the third embodiment, the clocked inverter circuit R1 and the clocked inverter circuit R2 can be operated at high speed.

  In the clocked inverter circuit R1 and the clocked inverter circuit R2, the common control signals (C, XC) and threshold control signals (SB, XSB) are supplied to the transistors TR3 and TR4, respectively. There is an advantage that the configuration of the electric circuit 104 is simplified as compared with the configuration in which separate signals are supplied to the circuit R1 and the clocked inverter circuit R2. In addition, the signal generation circuit 44 of the second embodiment is added to the inverter circuit Q (Q1, Q2, Q3) of the present embodiment, or the signal generation circuit of the fourth embodiment is added to the clocked inverter circuit R (R1, R2). A configuration in which (62A, 62B, 64A, 64B) is added is also preferably employed.

<F: Sixth Embodiment>
FIG. 18 is a circuit diagram showing a configuration of an electric circuit 105 according to the sixth embodiment of the present invention. The electric circuit 105 is a shift register circuit in which a plurality of latch circuits LT (LT1, LT2, LT3,...) Are connected in cascade. Each of the plurality of latch circuits LT, like the electric circuit 104 of the fifth embodiment, includes two clocked inverter circuits R (R1, R2) of the third embodiment and the inverter circuit Q3 of the first embodiment. Connected to each other. In FIG. 18, only the latch circuits LT1 to LT4 from the first stage to the fourth stage are shown for convenience. From the fifth stage onward, the same configuration as the first to fourth stages is repeated. In FIG. 18, the diodes d1 to d4 associated with the transistors TR1 to TR4 are not shown for convenience.

  The control circuit 30 (not shown in FIG. 18) generates four types of clock signals (φ1, φ2, Xφ1, Xφ2) having the same cycle illustrated in FIG. 19 and supplies them to the latch circuits LT of each stage. The clock signal Xφ1 is a signal having a waveform obtained by inverting the level of the clock signal φ1, and the clock signal Xφ2 is a signal having a waveform obtained by inverting the level of the clock signal φ2. The clock signal φ2 is a signal delayed in phase by 90 ° with respect to the clock signal φ1. Therefore, the phase of the clock signal Xφ1 is delayed by 90 ° with respect to the clock signal φ2, and the phase of the clock signal Xφ2 is delayed by 90 ° with respect to the clock signal Xφ1.

  As shown in FIG. 18, the clock signals delayed in phase by 90 ° are supplied to the gate G of the transistor TR3 of the clocked inverter circuit R1 in each latch circuit LT in the order of arrangement of the latch circuits LT. That is, the clock signal φ1 is supplied to the gate G of the transistor TR3 of the clocked inverter circuit R1 in the latch circuit LT1, and the clock signal φ2 is supplied to the gate G of the transistor TR3 of the clocked inverter circuit R1 in the latch circuit LT2 in the next stage. Supplied. Further, the clock signal Xφ1 is supplied to the gate G of the transistor TR3 of the clocked inverter circuit R1 in the latch circuit LT3, and the clock signal Xφ2 is supplied to the gate G of the transistor TR3 of the clocked inverter circuit R1 in the latch circuit LT4. .

  The condition of the signal supplied to each part in one latch circuit LT is the same as in the fifth embodiment. For example, the gate G of the transistor TR4 of the clocked inverter circuit R2 in the latch circuit LTi (i = 1, 2, 3,...) Is supplied to the gate G of the transistor TR3 of the clocked inverter circuit R1 in the latch circuit LTi. Clock signal to be supplied is supplied. In each of the clocked inverter circuit R1 and the clocked inverter circuit R2 in the latch circuit LTi, a clock signal whose phase is advanced by 90 ° from the clock signal of the gate G of the transistor TR3 is a signal supply point as the threshold control signal XSB. A clock signal having a phase advanced by 90 ° from the clock signal of the gate G of the transistor TR4 is supplied to the signal supply point P3 as the threshold control signal XSB. In each inverter circuit Q (Q1, Q2, Q3) of the latch circuit LTi, a signal obtained by delaying the output signal of the inverter circuit Q by the signal generation circuit 42 is supplied to the signal supply point P1 as the threshold control signal SA. The

  As shown in FIG. 18, the input signal PIN of the clocked inverter circuit R1 in the latch circuit LTi in each stage after the second stage has an output signal SOUTi-1 from the inverter circuit Q3 in the latch circuit LTi-1 in the previous stage. Is supplied. On the other hand, a start pulse SP is supplied from the control circuit 30 to the input pin PIN of the clocked inverter circuit R1 in the first-stage latch circuit LT1. Therefore, the output signal SOUT (SOUT1, SOUT2, SOUT3,...) Output from the inverter circuit Q3 of each latch circuit LT corresponds to the phase difference (1/4 cycle) of each clock signal as shown in FIG. The pulse signal is obtained by sequentially shifting the start pulse SP by the length of time. In FIG. 18, the signal XSi output from the clocked inverter circuit R1 of each latch circuit LTi is a signal having a waveform obtained by inverting the output signal SOUTi.

  As shown in FIG. 18, the electric circuit 105 includes a plurality of AND circuits 68. The AND circuit 68 at the i-th stage is a logical product of the signal XSi output from the clocked inverter circuit R1 of the latch circuit LTi and the output signal SOUTi + 1 generated by the inverter circuit Q3 of the latch circuit LTi + 1 at the next stage. Is output as a signal Zi. As shown in FIG. 19, the signal Z (Z1, Z2, Z3,...) Sequentially shifts to a high level every period corresponding to the phase difference (1/4 cycle) of the clock signal.

  As described in the first to fifth embodiments, the clocked inverter circuit R1 and the clocked inverter circuit R2 and the inverter circuit Q3 in each latch circuit LT have the body potential of the channel contact region A in each of the transistors TR1 to TR4. It operates at high speed by controlling VB1 to VB4. Therefore, according to this embodiment, the operation of the electric circuit 105 (shift register circuit) can be speeded up.

<G: Seventh Embodiment>
FIG. 20 is a block diagram showing a configuration of a display device 70 according to the seventh embodiment of the present invention. The display device 70 has a configuration in which a pixel portion 72, a scanning line driving circuit 74, and a data line driving circuit 76 are formed on the surface of the insulating substrate 10. In the pixel portion 72, m scanning lines 721 extending in the X direction and n data lines 722 extending in the Y direction are formed. A pixel PIX is arranged at each intersection of the scanning line 721 and the data line 722 via an N-channel transistor 724. A gate G of the transistor 724 is connected to the scan line 721.

  The scanning line driving circuit 74 includes a shift register circuit 742 having a configuration similar to that of the electric circuit 105 of the sixth embodiment (cascade connection of m-stage latch circuits LT). The shift register circuit 742 generates scanning signals Y1 to Ym (output signals Z1 to Zm in FIG. 19) and outputs them to each scanning line 721. The scanning signals Y1 to Ym are sequentially shifted to a high level every horizontal scanning period. When the scanning signal Yi supplied to the i-th (i = 1 to m) scanning line 721 transits to a high level (when the n pixels PIX in the i-th row are selected), the i-th row The transistors 724 are turned on all at once.

  The data line driving circuit 76 includes a shift register circuit 762 having a configuration similar to that of the electric circuit 105 of the sixth embodiment (cascade connection of n-stage latch circuits LT), a signal line 764, and a sampling circuit 766. The shift register circuit 762 generates and outputs sampling signals SM1 to SMn (output signals Z1 to Zn in FIG. 19). The sampling signals SM1 to SMn sequentially become high level during the horizontal scanning period when the scanning signal Yi is high level.

  The signal line 764 is supplied with an image signal SG for sequentially designating the gradation of each pixel PIX in a time division manner from an external circuit. Sampling circuit 766 includes n switching elements SW1 to SWn. The switching element SWj in the j-th column (j = 1 to n) is interposed between the signal line 764 and the data line 722 in the j-th column and controls the electrical connection therebetween. The switching element SWj changes to the on state when the sampling signal SMj transitions to a high level. The image signal SG when the sampling signal SMj changes to the ON state is output to the data line 722 of the jth column as the data signal Xj.

  In the above configuration, the data signal Xj is supplied to the pixel PIX in the j-th column belonging to the i-th row through the transistor 724 that is turned on in response to the scanning signal Yi. By sequentially setting the gradation of each pixel PIX according to the data signal Xj, an image corresponding to the image signal SG is displayed on the pixel unit 72. The configuration of each pixel PIX is arbitrary. For example, a configuration in which various electro-optical elements such as a liquid crystal element and an organic EL (Electroluminescence) element are connected to the transistor 724 is preferable.

  Since the electric circuit 105 of the sixth embodiment can operate at high speed, in this embodiment, the scanning line driving circuit 74 and the data line driving circuit 76 adopting the electric circuit 105 as shift register circuits (742, 762) are provided. High-quality images can be displayed by operating at high speed. In this embodiment, the electric circuit 105 of FIG. 18 is applied to the display device 70. However, for example, in an exposure apparatus employed in an electrophotographic image forming apparatus (printing apparatus), a plurality of light emission arranged in a straight line. The electric circuit 105 may be used as a driving circuit that sequentially emits light from the element.

<H: Application example>
Next, an electronic apparatus using the display device according to the present invention will be described. FIG. 21 to FIG. 23 show forms of electronic devices that employ the display device 70 according to the seventh embodiment.

  FIG. 21 is a perspective view showing the configuration of a mobile personal computer that employs the display device 70. The personal computer 2000 includes a display device 70 that displays various images, and a main body 2010 on which a power switch 2001 and a keyboard 2002 are installed.

  FIG. 22 is a perspective view showing a configuration of a mobile phone to which the display device 70 is applied. The cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and a display device 70 that displays various images. By operating the scroll button 3002, the screen displayed on the display device 70 is scrolled.

  FIG. 23 is a perspective view showing a configuration of a personal digital assistant (PDA) to which the display device 70 is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and a display device 70 that displays various images. When the power switch 4002 is operated, various information such as an address book and a schedule book are displayed on the display device 70.

  Note that examples of electronic devices to which the display device according to the present invention is applied include the digital still camera, television, video camera, car navigation device, pager, electronic notebook, electronic paper, in addition to the devices illustrated in FIGS. Examples include calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like.

It is a circuit diagram showing the composition of the electric circuit concerning a 1st embodiment of the present invention. FIG. 11 is a plan view illustrating a specific structure of a transistor. It is a graph which shows that the threshold voltage of a P channel type transistor changes according to body potential. It is a graph which shows that the threshold voltage of an N channel type transistor changes according to body potential. It is a timing chart for demonstrating operation | movement of an inverter circuit. 6 is a timing chart for explaining the operation of the comparative 1; 6 is a timing chart for explaining the operation of the comparative 2; It is a circuit diagram which shows the structure of the electric circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows the specific structure of a signal generation circuit. It is a circuit diagram which shows the structure of the electric circuit which concerns on 2nd Embodiment. It is a timing chart for explaining operation of the electric circuit concerning a 2nd embodiment. It is a circuit diagram which shows the structure of the electric circuit which concerns on 3rd Embodiment. It is a timing chart for demonstrating operation | movement of a clocked inverter circuit. It is a block diagram for demonstrating the signal generation circuit of 4th Embodiment. It is a block diagram for demonstrating the signal generation circuit of 4th Embodiment. It is a circuit diagram which shows the specific structure of a signal generation circuit. It is a circuit diagram which shows the structure of the electric circuit (latch circuit) which concerns on 5th Embodiment. It is a circuit diagram which shows the structure of the electric circuit (shift register circuit) which concerns on 6th Embodiment. It is a timing chart for explaining operation of the electric circuit concerning a 6th embodiment. It is a block diagram which shows the structure of the display apparatus which concerns on 7th Embodiment. It is a perspective view which shows the form (personal computer) of the electronic device which concerns on this invention. It is a perspective view which shows the form (cellular phone) of the electronic device which concerns on this invention. It is a perspective view which shows the form (mobile information terminal) of the electronic device which concerns on this invention.

Explanation of symbols

100, 101, 102, 103, 104, 105 ... Electric circuit, Q, Q1, Q2, Q3 ... Inverter circuit, TR1-TR4 ... Transistor, G ... Gate, A ... Channel contact region, L1, L2 ...... Power supply line, 42, 44, 62A, 62B, 64A, 64B ... Signal generation circuit, R, R1, R2 ... Clocked inverter circuit, SIN ... Input signal, SOUT ... Output signal, SA, SB, XSB ... threshold control signal, C, XC ... control signal, LT (LT1, LT2, LT3, ...) ... latch circuit, 70 ... display device, 72 ... pixel unit, PIX ... pixel, 74 ... ... Scanning line driving circuit, 76... Data line driving circuit, 742 and 762.

Claims (9)

An inverter circuit;
A clocked inverter circuit;
Comprising
The inverter circuit is
A P-channel first transistor and an N-channel second transistor connected in series between the first power line and the second power line;
A first capacitor interposed between a first signal supply point and a channel contact region of the first transistor;
Look including a second capacitor interposed between the channel contact region of the second transistor and the first signal feed point,
The clocked inverter circuit is
A P-channel third transistor interposed between the first power supply line and the first transistor;
An N-channel fourth transistor interposed between the second power supply line and the second transistor;
A third capacitor interposed between a second signal supply point and a channel contact region of the third transistor;
A fourth capacitor interposed between the channel contact region of the fourth transistor and the third signal feed point seen including,
A first threshold control signal that transitions to a low level before the input signal to the inverter circuit falls from a high level and transitions to a high level before the input signal rises from a low level is provided at the first signal supply point. Supplied ,
A first control signal is supplied to the gate of the third transistor, and a second control signal having a waveform obtained by inverting the first control signal is supplied to the gate of the fourth transistor.
A second threshold control signal that transitions to a low level before the first control signal falls from a high level and that transitions to a high level before the first control signal rises from a low level is the second signal supply point Supplied to
A third threshold control signal that transitions to a high level before the second control signal rises from a low level and that transitions to a low level before the second control signal falls from a high level is the third signal supply point Electric circuit supplied to . The electric circuit according to claim 1, further comprising: a signal generation circuit that generates the first threshold control signal from an input signal or an output signal of the inverter circuit. A first signal generation circuit for generating the second threshold control signal from one of the first control signal and the second control signal;
Wherein the first control signal and the second control signal other claims 1 or electrical circuit according to claim 2; and a second signal generating circuit for generating the third threshold value control signal. A first clocked inverter circuit including a first inverter circuit;
A second clocked inverter circuit including a second inverter circuit and having an output connected to the output of the first clocked inverter circuit;
A third inverter circuit having an input unit connected to an output unit of the first clocked inverter circuit and an output unit connected to an input unit of the second clocked inverter circuit;
Each of the first inverter circuit, the second inverter circuit, and the third inverter circuit is:
A P-channel first transistor and an N-channel second transistor connected in series between the first power line and the second power line;
A first capacitor interposed between a first signal supply point and a channel contact region of the first transistor;
A second capacitor interposed between the first signal supply point and the channel contact region of the second transistor;
A first threshold control signal that changes to a low level before the input signal to the inverter circuit falls from a high level and changes to a high level before the input signal rises from a low level is the first threshold control signal of the inverter circuit. An electrical circuit supplied to a signal supply point. Each of the first clocked inverter circuit and the second clocked inverter circuit is:
A P-channel third transistor interposed between the first power supply line and the first transistor;
An N-channel fourth transistor interposed between the second power supply line and the second transistor;
A third capacitor interposed between a second signal supply point and a channel contact region of the third transistor;
A fourth capacitor interposed between a third signal supply point and a channel contact region of the fourth transistor,
A first control signal is supplied to the gates of the third transistor of the first clocked inverter circuit and the fourth transistor of the second clocked inverter circuit, and the fourth transistor of the first clocked inverter circuit. And a second control signal having a waveform obtained by inverting the first control signal is supplied to each gate of the third transistor of the second clocked inverter circuit,
A second threshold control signal that transitions to a low level before the first control signal falls from a high level and that transitions to a high level before the first control signal rises from a low level is the first clocked inverter. Supplied to the second signal supply point of the circuit and the third signal supply point of the second clocked inverter circuit;
A third threshold control signal that transitions to a high level before the second control signal rises from a low level and that transitions to a low level before the second control signal falls from a high level is the first clocked inverter. The electric circuit according to claim 4 , wherein the electric signal is supplied to the third signal supply point of the circuit and the second signal supply point of the second clocked inverter circuit. A drive circuit including a shift register circuit in which a plurality of electrical circuits of claim 4 or 5 are connected in cascade, and sequentially outputting a plurality of drive signals based on an output signal generated by each of the electrical circuits;
A display device comprising: a plurality of pixels driven in accordance with each drive signal generated by the drive circuit. An electronic apparatus comprising the display device according to claim 6 . A first clocked inverter circuit including a first inverter circuit; a second clocked inverter circuit including a second inverter circuit; and an output unit connected to an output unit of the first clocked inverter circuit; A third inverter circuit connected to the output of the first clocked inverter circuit and having an output connected to the input of the second clocked inverter circuit, the first inverter circuit and the second inverter Each of the circuit and the third inverter circuit includes a P-channel first transistor and an N-channel second transistor connected in series between a first power line and a second power line, and a first signal A first capacitor interposed between a supply point and a channel contact region of the first transistor;
A method of driving an electric circuit including a second capacitor interposed between the first signal supply point and a channel contact region of the second transistor,
For each of the first inverter circuit, the second inverter circuit, and the third inverter circuit, the input signal to the inverter circuit transits to a low level before falling from the high level, and the input signal rises from the low level. A driving method of an electric circuit for supplying a first threshold control signal that transitions to a high level before rising to the first signal supply point of the inverter circuit. Each of the first clocked inverter circuit and the second clocked inverter circuit includes a P-channel third transistor interposed between the first power supply line and the first transistor, and the second power supply line. An N-channel fourth transistor interposed between the second transistor, a third capacitor interposed between the second signal supply point and the channel contact region of the third transistor, and a third signal supply point; A fourth capacitor interposed between the channel contact region of the fourth transistor,
A first control signal is supplied to the gates of the third transistor of the first clocked inverter circuit and the fourth transistor of the second clocked inverter circuit, and the fourth transistor of the first clocked inverter circuit And supplying a second control signal having a waveform obtained by inverting the first control signal to each gate of the third transistor of the second clocked inverter circuit,
A second threshold control signal that transitions to a low level before the first control signal falls from a high level and transitions to a high level before the first control signal rises from a low level is supplied to the first clocked inverter. Supplying the second signal supply point of the circuit and the third signal supply point of the second clocked inverter circuit;
A third threshold control signal that transitions to a high level before the second control signal rises from a low level and transitions to a low level before the second control signal falls from a high level is supplied to the first clocked inverter The method for driving an electric circuit according to claim 8 , wherein the third signal supply point of the circuit and the second signal supply point of the second clocked inverter circuit are supplied.

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