JP2006211158A - Semiconductor device provided with mos transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a MOS transistor operable with high accuracy at a high speed under a low voltage. <P>SOLUTION: The semiconductor device is provided with: at least one MOS transistor 10 including a gate input section 12 and a body input section 14; and a control circuit 20 including a first output section 22 for sending a first control signal (gate voltage V<SB>g</SB>(t)) to the gate input section 12, and a second output section 22 for sending a second control signal (body voltage V<SB>b</SB>(t)) to the body input section 14. The control circuit 20 turns on the MOS transistor 10 through the application of the gate voltage V<SB>g</SB>(t) and thereafter changes a level of the body voltage V<SB>b</SB>(t) to increase a threshold value of the MOS transistor 10 while the MOS transistor 10 stays in the ON state. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a MOS transistor, and more particularly to a semiconductor device capable of realizing high-speed switching of a MOS transistor with a low voltage source.

  In recent years, the power supply voltage of MOS transistors has been lowered for the purpose of reducing power consumption. For this reason, a technique for dynamically changing the threshold value of the MOS transistor so that a high-speed switching operation can be realized even when the power supply voltage is lowered has been studied. According to this technique, the threshold value of the transistor is switched between a relatively high state and a relatively low state depending on whether the transistor is in an on (ON) state or an off (OFF) state. A switched capacitor circuit realized by using such a dynamic threshold change technique is disclosed in Patent Document 1.

  Hereinafter, a conventional switched capacitor circuit in which the threshold value dynamically changes will be described with reference to FIG.

  The semiconductor device shown in FIG. 22A has a pair of MOS transistors constituting a CMOS inverter. A first clock CLK1 is input to the NMOS gate input section 100, and an inverted first clock CLK1 bar is input to the PMOS gate input section 200. In order to control the voltage of the substrate (body), the second clock CLK2 is input to the NMOS body input unit 102, and the inverted second clock CLK2 bar is input to the body input unit 202 of the PMOS. .

  FIG. 22B is a waveform diagram of the first clock CLK1 and the second clock CLK2. The vertical axis is voltage, and the horizontal axis is time. As can be seen from FIG. 22B, the first clock CLK1 and the second clock CLK2 are at a high level when the MOS transistor is in an ON state, and are at a low level when the MOS transistor is in an OFF state. . Note that the level of the second clock CLK2 in the ON state is set lower than the level of the first clock CLK1. In addition, when the first clock CLK1 and the second clock CLK2 transition from the ON state to the OFF state, the first clock CLK1 and the second clock CLK2 decrease to the zero level with substantially the same magnitude (slope).

The second clock CLK2 as shown in FIG. 22B and its inverted signal CLK2 bar are given to the body inputs 102 and 202 of the MOS transistor shown in FIG. Can be made larger than the threshold value of each MOS transistor in the ON state. When the absolute value of the threshold value of each MOS transistor in the OFF state increases, the leakage current in the OFF state is reduced. On the other hand, when the threshold value of each MOS transistor in the ON state is small, a high-speed switching operation is possible even when the gate voltage is low.
JP-A-11-163647

  However, in the semiconductor device described above, when the MOS transistor transitions from the ON state to the OFF state, the charge (channel charge) existing in the channel region is injected into the source / drain region, and an error occurs in the output voltage. There is a problem. As described above, the phenomenon that the channel charge of the MOS transistor is injected into the source / drain at the time of ON → OFF is conventionally known and is called “charge injection”. “Charge injection” is not limited to the semiconductor device disclosed in Patent Document 1, and is a phenomenon that can be observed in a normal MOS transistor. However, according to the study of the present inventor, it has been found that the output voltage error due to “charge injection” is particularly prominent in a semiconductor device that dynamically changes the body voltage, and the error is the MOS It was also found that the larger the switching operation of the type transistor, the larger it becomes.

FIG. 23 shows an error that occurs in the output voltage due to charge injection. The vertical axis of the graph is the output voltage (V _out ) of the switched capacitor, and the horizontal axis is time. For reference, in this graph, the input voltage of the switched capacitor is indicated by the reference symbol “IN”. The input voltage IN changes with time as indicated by a sine curve.

  Among the switched capacitors that have received the input voltage IN having such a waveform, the output voltage of the conventional capacitor having a MOS type transistor that fixes the body voltage is indicated by the reference symbol “MOS” in the graph. As can be seen from the graph of FIG. 23, the output voltage indicated by the reference symbol “MOS” does not follow the fast change of the input voltage IN.

  On the other hand, the graph of FIG. 23 shows the output voltage when the body voltage changes as in the semiconductor device of FIG. This output voltage follows the change in the input voltage IN, but periodically occurring voltage errors are observed. This voltage error continues to occur until the MOS transistor in FIG. 22 returns from the ON state to the OFF state and then returns to the ON state. For this reason, in the semiconductor device of FIG. 22, an output voltage in which a number of rectangular pulses are superimposed on a sine curve is obtained.

  As long as such a voltage error occurs in the output signal, it is practically difficult to adopt a technique for dynamically changing the body voltage for low voltage and high speed operation.

  An object of the present invention is to provide a semiconductor device including a MOS transistor capable of high-speed and high-precision operation at a low voltage.

  The semiconductor device according to the present invention includes at least one MOS transistor having a gate input portion and a body input portion, a first output portion for sending a first control signal to the gate input portion, and a second control for the body input portion. A control circuit having a second output section for transmitting a signal, wherein the control circuit turns on the MOS transistor by applying the first control signal, and then the MOS transistor The level of the second control signal is changed so as to raise the threshold value of the MOS transistor while the transistor is in the ON state.

  Another semiconductor device of the present invention includes at least one MOS transistor having a gate input section and a body input section, a first output section for sending a first control signal to the gate input section, and a second input to the body input section. A control circuit having a second output unit for transmitting a control signal, wherein the control circuit turns on the MOS transistor by applying the first control signal, and then the MOS transistor Is in the ON state, the level of the second control signal is lowered with a fall time longer than the fall time of the first control signal.

  In a preferred embodiment, the control circuit starts the fall of the second control signal before the fall of the first control signal starts.

  In a preferred embodiment, the control circuit has a time difference between the start of falling of the first control signal and the start of falling of the second control signal of 1 picosecond or more.

  In a preferred embodiment, the level of the first control signal increases from a first Low value to a first High value when the MOS transistor is switched from an off state to an on state, and the MOS transistor is turned on. When switching from a state to an off state, the first high value falls from the first high value to the first low value, and the level of the second control signal is the same as that of the first control signal. In at least a part of a period, the second high value having a magnitude between the first high value and the first low value is at a level, and the level of the first control signal is the first low value. The second low value is lower than the second high value in at least a part of the period in the value.

  In a preferred embodiment, the second Low value is equal to the first Low value.

  In a preferred embodiment, when the level of the second control signal reaches the second low value from the second high value, the level of the first control signal changes from the first high value to the first level. It is later than the timing when the low value is reached.

  In a preferred embodiment, the control circuit changes the levels of the first control signal and the second control signal in synchronization with a clock signal of 10 MHz or higher.

  In a preferred embodiment, the MOS transistor operates with a power supply voltage of 3 volts or less.

  According to the present invention, it is possible to provide a semiconductor device capable of low voltage and high speed operation while reducing an error in output voltage.

  First, the basic configuration and operation of the semiconductor device according to the present invention will be described with reference to FIGS.

  As shown in FIG. 1A, the semiconductor device of the present invention includes at least one MOS transistor 10 and a control circuit 20 that controls the operation of the MOS transistor 10.

The MOS transistor 10 has a gate input unit 12 and a body input unit 14. The source of the MOS transistor 10 is connected to the input terminal IN and receives a signal voltage (input signal) from a circuit (not shown). The drain of the MOS transistor 10 is connected to an output terminal OUT with a capacity C _L, the voltage corresponding to the charge accumulated in the capacitor C _L (output signal) is outputted to the output side terminal OUT.

  The control circuit 20 includes a first output unit 22 that transmits a first control signal to the gate input unit 12 of the MOS transistor 10 and a second output unit 24 that transmits a second control signal to the body input unit 14. ing.

The first control signal is a signal that defines the gate voltage of the MOS transistor 10, and its magnitude is represented by V _g (t) (t indicates time). In the preferred embodiment, the first control signal is a signal that periodically changes between a high level and a low level, and therefore may be referred to as a first clock CLK1.

On the other hand, the second control signal is a signal that defines the body voltage (substrate voltage) of the MOS transistor 10, and its magnitude is represented by V _b (t). Similarly to the first control signal, the second control signal is also referred to as a second clock CLK2 when it periodically changes between the High level and the Low level.

In the following description, the first control signal is referred to as “gate voltage V _g (t)” or “first clock CLK1”, and the second control signal is referred to as “body voltage V _b (t)” or “second clock CLK2”. It shall be called.

The gate voltage V _g (t) and the body voltage V _b (t) have waveforms shown in FIG. In the following drawings, the rise and fall of the gate voltage V _g (t) and the body voltage V _b (t) are linearly described. Due to the capacitance, the edge portion becomes dull in a curve. In the present specification, the gate voltage V _g (t) and body voltage V _b of (t) and "fall time", the gate voltage V _g (t) and body voltage V _b (t) is the maximum value ( (VDD ₁ or VDD ₂ ) is defined as the time until the value decreases from 0.9 times to 0.1 times. Further, the slope (gradient) S of the falling portion of the gate voltage V _g (t) and the body voltage V _b (t) is a value obtained by dividing “0.8 × VDD” by the above-described falling time. .

In the first aspect of the present invention, the control circuit 20 applies the gate voltage V _g (t) having a magnitude exceeding the threshold to the gate input section 12 of the MOS transistor 10 to turn on the MOS transistor 10. After that, the level of the body voltage V _b (t) is changed (the absolute value of the threshold is lowered) so that the threshold of the MOS transistor 10 is raised while the MOS transistor 10 is in the ON state. Such an operation is referred to as a “timing adjustment type operation”.

In the second aspect of the present invention, after the control circuit 20 turns on the MOS transistor 10 by applying the gate voltage V _g (t) having a magnitude exceeding the threshold, the MOS transistor 10 When transitioning to the OFF state, the absolute value of the body voltage V _b (t) is lowered with a fall time longer than the fall time of the gate voltage V _g (t). As the fall time becomes longer, the gradient of the voltage change (slope S) becomes smaller, and such an operation is referred to as a “slope adjustment type operation”.

The waveform shown in FIG. 1B is an example of a signal waveform when the first and second modes are combined. In FIG. 1B, the vertical axis represents voltage (Voltage), and the horizontal axis represents time (t). In this example, the gate voltage V _g (t) periodically increases and decreases between the level VDD ₁ and the level 0, and the body voltage V _b (t) periodically changes between the level VDD ₂ and the level 0. Increase or decrease. The level VDD ₂ is lower than the level VDD _{1 and} the slope (slope) of the transition curve of the body voltage V _b (t) is smaller than the slope of the gate voltage V _g (t).

  In the semiconductor device of the present invention, an error in the output voltage due to charge injection, which has been a problem when the transistor is changed from the ON state to the OFF state by executing “timing adjustment type operation” or “slope adjustment type operation”. Is greatly reduced.

  In the following, before explaining the reason why the influence of charge injection is reduced by the “timing adjustment type operation” and “slope adjustment type operation” in the present invention, first, charge injection causes voltage error in a conventional semiconductor device. Explain the mechanism to make it.

  FIG. 2 is a diagram showing a schematic cross-sectional configuration and an equivalent circuit of the MOS transistor 10 shown in FIG. The contents of each parameter relating to the MOS transistor 10 of FIG. 2 are as shown in Table 1 below.

When the MOS transistor 10 shown in FIG. 2 is in the ON state, a channel (inversion layer) is formed near the interface between the semiconductor 30 and the gate insulating film 32. Assuming that the input voltage V _in and the output voltage V _out are substantially equal, the total charge Q _ch in the inversion layer is expressed by an expression of Q _ch = WLC _ox (V _g −V _in −V _th ).

As described above, when the MOS transistor 10 transitions from the ON state to the OFF state, the charge Q _ch existing in the inversion layer is injected into the source / drain (channel charge injection). The charge injected into the source on the input side is absorbed by the input source and thus does not cause an error. However, since the charge injected into the drain on the output side is accumulated in the load capacitor C _L , the output voltage V _out Is displaced from the true value, causing a voltage error.

Usually, when the MOS transistor is NMOS, the body voltage _Vb is fixed to the ground, and when it is PMOS, it is fixed to the power supply voltage. In the case of such a configuration, the amount of charges accumulated in the drain substrate capacitance C _db and the source substrate capacitance C _sb hardly changes depending on ON / OFF of the MOS transistor. As a result, the charge injected into the output side (drain) by charge injection is only the charge caused by a change in the gate voltage V _g.

However, when the body voltage V _b changes with the gate voltage V _g (t) as in the semiconductor device described in Patent Document 1, when the MOS transistor transitions from the ON state to the OFF state, the source substrate The charges accumulated in the capacitor C _sb and the drain-substrate capacitor C _db are also injected into the source / drain. Therefore, when the body voltage V _b changes together with the gate voltage V _g , the charge injection amount increases, and as a result, the error of the output voltage V _out increases.

Thus, in the semiconductor device raising and lowering the body voltage V _b for the purpose of dynamically changing the transistor threshold, the output voltage error due to charge injection amount is increased, it becomes difficult to achieve an accurate operation End up.

  In order to solve this problem, in the present invention, the “timing adjustment type operation” and the “slope adjustment type operation” are executed, thereby reducing the charge injection amount and reducing the error of the output voltage Vout. Hereinafter, it will be described with reference to FIGS. 3 to 13 that the charge injection amount is reduced by the configuration of the present invention.

First, refer to FIGS. 3A and 3B. FIG. 3A is an equivalent circuit diagram of the MOS transistor 10 included in the semiconductor device of the present invention. FIG. 3B shows the waveforms of the gate voltage V _g (t) and the body voltage V _b (t). It is a graph which shows a part (falling part). The vertical axis of the graph of FIG. 3B is voltage (Voltage), and the horizontal axis is time (t).

In FIG. 3A, for simplicity, the gate voltage V _g (t) and the body voltage V _b (t) are represented by “V _g ” and “V _b ”, respectively. Here, V _s and V _d are an input voltage and an output voltage, respectively, and “I _d ” and “C _L ” are a drain current and a capacitance, respectively.

Here, as shown in FIG. 3 (b), it is assumed that the gate voltage V _g is reduced from a level VDD ₁ Slope S _1, body voltage V _b is lowered from the level VDD ₂ Slope S _2. It should be noted that the fall of the body voltage V _b is started as soon as the time of Δt than the fall of the gate voltage V _g. At this time, the gate voltage V _g and the body voltage V _b are respectively expressed by the following equations.

V _g (t) = VDD ₁ −S ₁ · t
V _b (t) = VDD ₂ −S ₂ · t

  Furthermore, the following formula is established from Kirchhoff's law.

Here, the relationship V _ds = V _d −V _s = V _out −V _in is established, and V _ds is an “output voltage error”.

  Assuming that the same amount of charge Q moves to each of the source and drain, the charge Q in the above equation is represented by the sum of half of the channel charge and the charge accumulated in the drain substrate. That is, the following expression is established.

Here, Q _ch is the channel charge, and Q _body is the charge accumulated in the drain-substrate capacitance. Note that γ is a substrate bias coefficient. For simplicity, assuming that the MOS transistor operates in a linear region, the drain current I _d is expressed by the following equation using the on-conductance G _on .

In the conventional semiconductor device that maintains the body voltage V _b at a constant value (V _b = 0), the following equation is established.

  For this reason, the following formula is obtained.

  here,

Then the above equation can be rewritten as:

When this equation is solved, the output voltage error V _ds is expressed by the following equation.

Here, when t = V _HT / S ₁ , the output voltage is held, and finally the output voltage error V _ds is expressed by the following equation.

On the other hand, in the case of a conventional semiconductor device in which the body voltage V _b (t) rises and falls in the same manner as the gate voltage V _g (t), the following equation is obtained by creating a differential equation similar to the above.

  Here, using the following equation:

  The following formula is obtained:

When this equation is solved, the output voltage error V _ds is expressed by the following equation.

When t = V _HT ^′ / S ^′ , the output voltage is held, and finally the output voltage error V _ds is expressed by the following equation.

  The following numerical examples are substituted into the above equation using typical NMOS parameters designed with a 0.13 μm rule.

S ₁ = S ₂ = 1.0 × 10 ¹⁰ [V / sec]
VDD ₁ = VDD ₂ = 1.0 [V]
V _in = 0.2 [V]
C _L = 0.1 [pF]

  FIG. 4 is a graph showing the results of calculation using the above numerical values and equations.

In the conventional semiconductor device (Comparative Example 1) in which the body voltage V _b (t) is held at zero volts, the output voltage error is about −7 mV. On the other hand, in the semiconductor device (Comparative Example 2) in which the body voltage V _b (t) changes in the same manner as the gate voltage V _g (t), the output voltage error reaches about −11 mV, and the voltage error is about 1.5 times. It can be seen that it increases.

Next, calculation results regarding the falling timing of the body voltage V _b (t) will be described. FIG. 5 shows a waveform of the body voltage V _b (t) in which the falling timing is advanced by time TD compared to the conventional case. The slope of the fall (slope) is not changed.

  Assume that the fall time is 0.1 nsec. FIGS. 6A and 6B are graphs showing calculation results for NMOS and PMOS, respectively. The vertical axis of the graph is the voltage error, and the horizontal axis is the input voltage. FIG. 6 shows a voltage error curve when the time TD is increased from 0 nsec (= conventional example) to 0.25 nsec in units of 0.05 nsec.

  As can be seen from FIG. 6, in either case of NMOS or PMOS, the absolute value of the voltage error decreases as the time TD increases. The effect of reducing the voltage error is more remarkable in the NMOS.

FIGS. 7A and 7B show the fall time of the gate voltage V _g (t) for the NMOS and PMOS without changing the fall timing of the body voltage V _b (t). It is a graph which shows the output voltage error at the time of making it increase to 2 times of down time. The vertical axis of the graph is the voltage error, and the horizontal axis is the fall time of the gate voltage V _g (t).

As can be seen from the graphs of FIGS. 7A and 7B, when the fall time of the body voltage V _b (t) is doubled, the fall time of the gate voltage V _g (t) is 1.0 nsec or less. In the entire region, the output voltage error is reduced. The degree of error reduction becomes more conspicuous as the fall time of the gate voltage V _g (t) becomes shorter (particularly at 0.2 nsec or less). That is, the effect of reducing the error appears remarkably when the MOS transistor is switched at high speed. In the case where the input voltage V _in is at the ground level (0V) or the power supply voltage level (1.5V), because the on-resistance of the MOS transistor is very small, the amount of charge injection is increased, the output voltage error However, according to the present invention, the increase can be suppressed.

FIG. 8 is a diagram showing a falling slope in the body voltage V _b (t). In the following example, in order to reduce this slope, the fall time is increased to 2 times, 3 times, 4 times, and 5 times that of the conventional example. 9, FIG. 10, and FIG. 11 are graphs showing the relationship between the fall time and the output voltage error in the NMOS, PMOS, and CMOS switches.

From the above graph, it can be seen that the longer the fall time of the body voltage V _b (t), the more the output voltage error is reduced. More specifically, when the fall time is doubled, the output voltage error is cut by about 70% at the maximum, and when the fall time is doubled, the voltage error is cut by about 90% at the maximum. it can.

Next, a calculation result related to the amplitude of the body voltage V _b (t) (the value of the level VDD2) will be described with reference to FIGS.

In the example described below, when the fall timings of the gate voltage V _g (t) and the body voltage V _b (t) are the same, the fall time of the body voltage V _b (t) is expressed as the gate voltage V _g (t ) Fall time (0.1 nsec). As can be seen from the graphs of FIGS. 12 and 13, the error appearing in the output voltage can be further reduced by reducing the amplitude of the body voltage V _b (t). However, if the amplitude of the body voltage V _b (t) is reduced, the effect obtained by dynamically changing the threshold value is reduced, so the output voltage cannot follow the change in the input voltage, and low voltage and high speed operation is realized. It becomes difficult to do. For this reason, the optimum amplitude of the body voltage V _b (t) is determined by the trade-off between the error reduction of the output voltage and the high-speed operation characteristic of the semiconductor device.

Next, the preferable magnitude of Δt when the fall timing of the body voltage V _b (t) is advanced by Δt will be examined.

V _g (t) = VDD ₁ −S ₁ · t
V _b (t) = VDD ₂ −S ₂ · (t + Δt) = (VDD ₂ −S ₂ · t) −S ₂ · Δt

Since the above equation is established, if (VDD ₂ −S ₂ · t) = VDD ₂ ′, analysis is performed in the same manner as the operation of a conventional MOS transistor in which the body voltage falling timing is not relatively advanced. be able to.

Therefore, when the falling timing of the body voltage V _b (t) is advanced by Δt, the time for the MOS transistor to transition from the ON state to the OFF state is expressed by the following equation.

  That is, the following relationship is established.

In order to shorten the switching time by advancing the timing by Δt, the following relational expression should be satisfied.

When this formula is arranged, the following formula is obtained.

  From the above, it is preferable to set Δt so as to satisfy the following condition.

For example, assuming that VDD1 = VDD2 = 1.0, S1 = S2 = 10 ¹⁰ , γ = 0.5, and V _th = 0.2, each value is substituted into the above equation. At this time, the fall time of the gate voltage V _g (t) is 0.1 nanosecond, which corresponds to a clock operation of about 3.5 GHz. In this case, the following formula is established.

Therefore, it is preferable to set the time Δt for accelerating the fall of the body voltage V _b (t) within the range of 20 picoseconds to 110 picoseconds with respect to the fall of the gate voltage V _g (t). When S1 = 10 ¹⁰ and S2 = 5 × 10 ⁹ , the preferable range of Δt is as follows.

  In the case of a voltage signal that changes in synchronization with a clock frequency in the order of GHz, the timing jitter is less than 1 picosecond, and it is sufficiently possible to control the timing in several picoseconds to several hundred picoseconds. . Similarly, an optimum value can be obtained when a MOS transistor is controlled using a clock signal having a frequency of several MHz or more.

FIG. 24 is a graph showing the relationship between the frequency (clock frequency) of the body voltage V _b (t) and the fall time.

Hereinafter, the relationship between the waveforms of the gate voltage V _g (t) and the body voltage V _b (t) that can be employed in the present invention will be described with reference to FIGS. The important point in the present invention is that the body voltage V _b (t) starts to fall while the MOS transistor is in the ON state (timing adjustment type operation) or the body voltage V _b (t) falls. The time is longer than the fall time of the gate voltage Vg (t). As long as this condition is satisfied, the gate voltage Vg (t) and the body voltage V _b (t) can exhibit various waveforms.

14 and 15 are both fall time of the body voltage V _b (t) indicates an example of a case longer than the rise time of the body voltage V _b (t). On the other hand, FIGS. 16 and 17 are both fall time of the body voltage V _b (t) indicates an example of a case equal to the rise time of the body voltage V _b (t). In these diagrams, (a), (b), and (c) indicate that the rising timing of the body voltage V _b (t) is “earlier” than the rising timing of the gate voltage V _g (t), and “ It corresponds to the case of “same” and “slow”.

The difference between the waveform in FIG. 14 and the waveform in FIG. 15 is the difference between the timing at which the gate voltage Vg (t) reaches the zero level and the timing at which the body voltage V _b (t) reaches the zero level. is there. The difference between the waveform in FIG. 15 and the waveform in FIG. 16 is the same.

[Embodiment 1]
Hereinafter, a first embodiment of a semiconductor device according to the present invention will be described with reference to FIGS.

  The control circuit unit 20 in the semiconductor device of the present embodiment includes a clock generation circuit 40, a buffer circuit 42, and a delay circuit 44.

The delay circuit 44 receives the clock signal CLK output from the clock generation circuit 40 and outputs a first clock CLK1 that functions as a first control signal. A delay circuit 44, the power supply voltage similarly level VDD ₁ and a clock generating circuit 40 is supplied. The clock signal CLK output from the clock generation circuit 40 has a waveform shown in FIG. 19A, and the first clock CLK1 has a waveform shown in FIG. As is clear from these drawings, the clock signal CLK is delayed while propagating through the delay circuit 44, and is output as the first clock CLK1. The delay time is Δt2. The waveform of the first clock CLK1 is the same as the waveform of the clock signal CLK.

On the other hand, the buffer circuit 42 receives the clock signal CLK output from the clock generation circuit 40, and outputs a second clock CLK2 that functions as a second control signal. A power supply voltage of level VDD ₂ is supplied to the buffer circuit 42. As shown in FIG. 19B, the second clock CLK2 output from the buffer circuit 42 has a waveform in which the value of the High level is lowered to VDD ₂ and the slope (gradient) is relatively small. Yes. That is, the clock signal CLK is delayed while propagating through the buffer circuit 42, and both the maximum value and the slope are reduced, and the fall time is increased to about Δt1.

  The control circuit 20 according to the present embodiment has the above-described configuration, so that the two types of clock signals CLK1 and CLK2 shown in FIG. 19B are supplied to the gate input unit 12 and the body input unit 14 of the MOS transistor 10, respectively. To supply. Thereby, the MOS transistor 10 performs the above-described operation, and can exhibit the effects of the present invention.

[Embodiment 2]
Hereinafter, a second embodiment of the semiconductor device according to the present invention will be described with reference to FIGS.

  The control circuit unit in the semiconductor device of the present embodiment includes a clock generation circuit 50 and a waveform adjustment circuit 52.

The waveform adjustment circuit 52 receives the clock signal CLK output from the clock generation circuit 50 and outputs a clock signal CLK ′ with a reduced pulse width and amplitude. A power supply voltage of level VDD ₂ is supplied to the waveform adjustment circuit 52.

  The clock signal CLK output from the clock generation circuit 50 has the waveforms shown in FIGS. 21A and 21B, and the clock signal CLK ′ with a reduced pulse width and amplitude is shown in FIG. It has the waveform shown in b).

  Thereafter, the clock signal CLK ′ passes through a circuit constituted by the resistor R and the capacitor C, and is then output as the second clock signal CLK2 that functions as the second control signal. The waveform of the second clock signal CLK2 is duller than the clock signal CLK 'and has a smaller slope.

  The second clock signal CLK2 having the above waveform is input to the body input unit 14 of the MOS transistor 10. On the other hand, the clock signal CLK output from the control circuit 20 is directly input to the gate input unit 12 as the first control signal. As a result, the MOS transistor 10 in this embodiment also performs the above-described operation, and can exhibit the effects of the present invention.

  According to the configuration of each of the embodiments described above, the output voltage error can be reduced to a level that does not cause a problem in practice even when the power supply voltage is lowered to 3 volts or less and operated at a high clock frequency (10 MHz or more). Can do.

  Note that the transistor in the ON state can be set even if the slope of the second control signal in the present invention is set to be the same as the slope of the first control signal while the fall timing of the second control signal is set earlier than the fall timing of the first control signal. Since the threshold value is sufficiently reduced, an output voltage error due to charge injection can be reduced. However, in that case, the effect of applying the body voltage tends to be insufficient, and as a result, it is difficult to follow the input signal. For this reason, when it is necessary to perform switching with higher accuracy and higher speed, it is preferable to reduce the slope of the second control signal.

  The present invention is not limited to the semiconductor device including the NMOS, PMOS, or CMOS described above, but can be widely applied to various semiconductor devices including various switching circuits including a plurality of MOS transistors. Further, the control circuit is not limited to the one having the above configuration.

  Since the semiconductor device of the present invention is capable of high-speed and high-precision operation at a low voltage, it is suitably used for electronic devices that require reduced power consumption, for example, electronic devices such as mobile phones and mobile terminals.

(A) is a figure which shows the fundamental structure of the semiconductor device by this invention, (b) is a wave form diagram of "gate voltage _Vg (t)" and "body voltage _Vb (t)". . It is drawing which shows the typical cross-sectional structure and equivalent circuit of a MOS type transistor shown to Fig.1 (a). (A) is an equivalent circuit diagram of a MOS transistor included in the semiconductor device of the present invention, and (b) is a part (falling edge) of waveforms of the gate voltage V _g (t) and the body voltage V _b (t). It is a graph which shows a part. The vertical axis of the graph of (b) is voltage (Voltage), and a horizontal axis is time (t). It is a graph which shows the result of the numerical calculation regarding the output voltage error in the conventional semiconductor device. It is a wave form chart of body voltage _Vb (t) which advanced the fall timing by time TD compared with the past. (A) And (b) is a graph which shows the calculation result about NMOS and PMOS, respectively. The vertical axis of the graph is the voltage error, and the horizontal axis is the input voltage. A voltage error curve is shown when the time TD is increased from 0 nsec (= conventional example) to 0.25 nsec in units of 0.05 nsec. (A) and (b) show the fall time at the gate voltage V _g (t) without changing the fall timing at the body voltage V _b (t) for NMOS and PMOS, respectively. It is a graph which shows the output voltage error at the time of making it increase 2 times. The vertical axis of the graph is the voltage error, and the horizontal axis is the fall time of the gate voltage V _g (t). It is a figure which shows the slope of the fall in body voltage _Vb (t). It is a graph which shows the relationship between the fall time in an NMOS switch, and an output voltage error. It is a graph which shows the relationship between the fall time and output voltage error in a PMOS switch. It is a graph which shows the relationship between the fall time and output voltage error in a CMOS switch. Is a graph showing calculation results regarding the amplitude of the body voltage V _b (t) (the value of the level VDD _2). Is a graph showing calculation results regarding the amplitude of the body voltage V _b (t) (the value of the level VDD _2). Fall time of the body voltage V _b (t) indicates an example of a case longer than the rise time of the body voltage V _b (t). Fall time of the body voltage V _b (t) indicates another example of a case longer than the rise time of the body voltage V _b (t). Fall time of the body voltage V _b (t) indicates an example of a case equal to the rise time of the body voltage V _b (t). Fall time of the body voltage V _b (t) indicates another example of equal to the rise time of the body voltage V _b (t). It is a figure which shows the structure of the control circuit part in 1st Embodiment of the semiconductor device by this invention. FIG. 19A is a waveform diagram of the clock signal CLK output from the clock circuit, and FIG. 19B is a waveform diagram of the first clock CLK1. It is a figure which shows the structure of the control circuit part in 2nd Embodiment of the semiconductor device by this invention. (A) is a waveform diagram of the clock signal CLK output from the clock circuit, (b) is a waveform diagram of the clock signal CLK ′ with a reduced pulse width and amplitude, and (c) is a second waveform diagram. It is a wave form diagram of clock signal CLK2. (A) is an equivalent circuit diagram of the conventional switched capacitor circuit. (B) is a waveform diagram of the first clock CLK1 input to the gate input unit and the second clock CLK2 input to the body input unit. It is a graph which shows the error which arises in an output voltage by charge injection. It is a graph which shows the relationship between the frequency of body voltage _Vb (t), and fall time.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 MOS type transistor 12 Gate input part 14 Body input part 20 Control circuit 22 First output part of control circuit 24 Second output part of control circuit 30 Semiconductor substrate 32 Gate insulating film 40 Clock generation circuit 42 Buffer circuit 44 Delay circuit 50 Clock Generation circuit 52 Waveform adjustment circuit 100 NMOS gate input section 102 NMOS body input section 200 PMOS gate input section 202 PMOS body input section

Claims (9)

At least one MOS transistor having a gate input and a body input;
A control circuit having a first output section for sending a first control signal to the gate input section, and a second output section for sending a second control signal to the body input section;
A semiconductor device comprising:
The control circuit includes:
After turning on the MOS transistor by applying the first control signal, the level of the second control signal is increased so that the threshold of the MOS transistor is raised while the MOS transistor is in the ON state. Changing semiconductor devices. At least one MOS transistor having a gate input and a body input;
A control circuit having a first output section for sending a first control signal to the gate input section, and a second output section for sending a second control signal to the body input section;
A semiconductor device comprising:
The control circuit includes:
After the MOS transistor is turned on by applying the first control signal, the second transistor has a fall time longer than the fall time of the first control signal while the MOS transistor is in the ON state. A semiconductor device that reduces the level of a control signal.   The semiconductor device according to claim 1, wherein the control circuit starts falling of the second control signal before falling of the first control signal starts.   4. The semiconductor device according to claim 3, wherein the control circuit has a time difference of 1 picosecond or more between a fall start of the first control signal and a fall start of the second control signal. The level of the first control signal rises from a first low value to a first high value when the MOS transistor is switched from an off state to an on state, and the MOS transistor is switched from an on state to an off state. When switching, the first High value falls to the first Low value,
The level of the second control signal is a magnitude between the first high value and the first low value in at least a part of a period in which the level of the first control signal is at the first high value. The first control signal is at a second low value that is lower than the second high value in at least part of a period in which the level of the first control signal is at the first low value. The semiconductor device according to claim 1 or 2.   The semiconductor device according to claim 5, wherein the second Low value is equal to the first Low value.   When the level of the second control signal reaches the second Low value from the second High value, the level of the first control signal reaches the first Low value from the first High value. The semiconductor device according to claim 5, which is later than timing.   The semiconductor device according to claim 1, wherein the control circuit changes levels of the first control signal and the second control signal in synchronization with a clock signal of 10 MHz or more.   The semiconductor device according to claim 8, wherein the MOS transistor operates with a power supply voltage of 3 volts or less.