JP2013158042A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that allows further high accuracy and high reliability operation by controlling an error amount associated with switching of a main switching element.SOLUTION: A semiconductor device includes: at least one main switching element 1 having a first electrode S1 connected to a first node, a second electrode D1 connected to a second node, and a first control electrode G1 controlling the connection between the first and second electrodes by a first control signal CS1; a first cancel element 2 having a third electrode S2 and a fourth electrode D2 connected to the second node, and a second control electrode G2 receiving a second control signal CS2; and a control section 4 outputting the first control signal and the second control signal. The control section cancels charges occurring at the second node by the first cancel element on the basis of the second control signal when changing the main switching element from on to off on the basis of the first control signal.

Description

  This application relates to a semiconductor device, and more particularly to a semiconductor device that uses a canceling element to compensate for the influence of clock leakage of a main switching element.

  Conventionally, for example, in a switch circuit using a MOS transistor, it is known that when a transistor is switched from on to off, a charge is generated in the source electrode or the drain electrode due to a phenomenon called clock leakage. In the present specification, the term “clock leakage” includes charge injection and clock feedthrough.

  The clock leakage when the MOS transistor changes from on to off, for example, in the sample hold circuit (comparator) or the like, the potential fluctuation occurs due to the off at the high impedance node, which adversely affects the accuracy. .

  Charge injection is a phenomenon in which when a transistor (switching element) is turned on, charges (electrons or holes) forming a channel move to the source electrode or drain electrode of the transistor. In addition, for example, in the case of an n-channel MOS (nMOS) transistor, the clock feedthrough is performed between the gate electrode and the drain electrode as the potential of the gate electrode changes from the high level “H” to the low level “L”. This is a phenomenon that affects the potential by the electrostatic effect caused by the parasitic capacitance between the gate electrode and the source electrode.

  By the way, in a conventional switch circuit using MOS transistors, a main switching transistor and a canceling transistor having a half size (half channel width) of the main switching transistor are provided, and when the main switching transistor is switched from on to off, canceling is performed. There is known a technique for compensating for the influence of clock leakage by operating the operating transistor in a phase opposite to the switching operation of the main switching transistor.

  FIG. 1 is a diagram for schematically explaining charge injection and countermeasures. FIG. 1 (a) shows how the main switching transistor 1 changes from on to off, and FIG. 1 (b) shows this. The operation of the canceling transistor 2 is shown. In FIG. 1, the main switching transistor 1 and the canceling transistor 2 are described as nMOS transistors.

  First, as shown in the left diagram of FIG. 1A, the main switching transistor 1 is opposed to the gate electrode G1 when the high level signal “H” is applied to the gate electrode G1 and turned on. An electron channel CH1 is formed between the source electrode S1 and the drain electrode D1 in the substrate. 1A, the high level signal “H” applied to the gate electrode G1 becomes the low level signal “L”, and the main switching transistor 1 is turned from on to off. When the channel CH1 changes, the channel CH1 disappears, but the charge Qd that formed the channel CH1 moves to the source electrode S1 and the drain electrode D1 of the main switching transistor 1 by a charge Qd / 2.

  On the other hand, first, as shown in the left diagram of FIG. 1B, the canceling transistor 2 has a low level signal “L” applied to the gate electrode G2 when the main switching transistor 1 is on. Is turned off. 1B, when the main switching transistor 1 changes from on to off, the signal applied to the gate electrode G2 of the canceling transistor 2 is low-level signal “L”. Becomes a high level signal “H”, and a channel CH2 is formed (turned on) between the source electrode S2 and the drain electrode D2 in the substrate facing the gate electrode G2 of the canceling transistor 2.

  Here, since the size of the canceling transistor 2 is half that of the main switching transistor 1, the charge of the channel CH2 formed when the canceling transistor 2 is turned on is when the main switching transistor 1 is on. The electrode of the canceling transistor 2 is connected to the source electrode S1 or the drain electrode D1 of the main switching transistor 1 (for example, the source electrode S2 and the drain electrode). D2 is short-circuited and connected), so that the charge (Qd / 2) that formed the channel CH1 that disappears when the main switching transistor 1 changes from on to off is changed from the off state to the on state. Channel formed when So as to absorb (compensate) by H2.

  In FIG. 1, the main switching transistor 1 and the canceling transistor 2 are nMOS transistors, but the same applies to a p-channel MOS (pMOS) transistor.

  FIG. 2 is a diagram for schematically explaining clock feedthrough and countermeasures. FIG. 2A shows a connection state between the main switching transistor 1 and the canceling transistor 2, and FIG. 2B shows the main switching. The state of the main switching transistor 1 and the canceling transistor 2 when the transistor 1 is on is shown, and FIG. 2C shows the main switching transistor 1 and the canceling transistor when the main switching transistor 1 changes from on to off. The state of 2 is shown. Also with reference to FIG. 2, the main switching transistor 1 and the canceling transistor 2 are described as nMOS transistors.

  As shown in FIG. 2A, the canceling transistor 2 is connected to the drain electrode D1 of the main switching transistor 1 by short-circuiting the source electrode S2 and the drain electrode D2. Here, the size (gate electrode width) of the canceling transistor 2 is half that of the main switching transistor 1. Reference numeral 3 denotes a buffer amplifier that shapes the waveform of the signal (output signal) of the drain electrode D1 of the main switching transistor 1 and outputs the signal.

  In the main switching transistor 1, the gate electrode G1 and the drain electrode D1 are electrostatically coupled by a parasitic capacitance (gate electrode capacitance). Also in the canceling transistor 2, the gate electrode G2, the source electrode S2, and the drain electrode D2 are Capacitively coupled by parasitic capacitance. The drain electrode D1 of the main switching transistor 1 is connected to the source electrode S2 and the drain electrode D2 of the canceling transistor 2.

  Therefore, as shown in FIG. 2B, the main switching transistor 1 is turned on by applying a high level signal “H” to its gate electrode 1G, as shown in FIG. Further, when the high level signal “H” of the gate electrode G1 is switched to the low level signal “L” and the main switching transistor 1 is turned off, the canceling transistor 2 is applied to the gate electrode G2. The low level signal “L” is switched to the high level signal “H”, so that the potential fluctuation due to the electrostatic coupling of the main switching transistor 1 can be compensated by the electrostatic coupling in the canceling transistor 2. Yes.

  As described above, there is conventionally known one that compensates for the influence of clock leakage when the main switching transistor 1 is switched from on to off by operating the canceling transistor 2 in a phase opposite to that of the main switching transistor 1.

  Conventionally, as a sample switch, at least two transistors whose both ends are connected in parallel with each other between an analog input voltage and one end of a hold capacitor are provided, and at least two transistors are used when sampling the analog input voltage. A sample-and-hold circuit has been proposed in which one of the transistors is turned off with the timing shifted after the other transistors are turned off, thereby increasing the sampling speed and improving the sampling accuracy. (For example, refer to Patent Document 1).

  Further, conventionally, when the sample switch is turned off, the control voltage of the sample switch is controlled so as to change stepwise, thereby maintaining the wide band characteristics without increasing the chip cost, and the analog due to the influence of clock feedthrough. A sample hold circuit that can reduce an error in output voltage has also been proposed (see, for example, Patent Document 2).

Japanese Patent Laid-Open No. 11-224496 JP 2000-232348 A

  As described above, conventionally, the canceling element (cancellation transistor 2) half the size of the main switching element (main switching transistor 1) is operated in the opposite phase to the main switching element, and the main switching element is turned off from on. A semiconductor device has been proposed that compensates for the effects of clock leakage when changing to.

  However, the conventional semiconductor device can reduce the error associated with the switching of the main switching element, but it is difficult to control the error amount.

  In view of the above-described problems of the related art, it is an object of the present application to provide a semiconductor device that can operate with higher accuracy and reliability by controlling an error amount associated with switching of a main switching element.

  According to this embodiment, a semiconductor device having at least one main switching element, a first canceling element, and a control unit is provided. The main switching element includes a first electrode connected to a first node, a second electrode connected to a second node, and a first control signal that controls connection between the first and second electrodes by a first control signal. It has a control electrode.

  The first cancel element includes a third electrode and a fourth electrode connected to the second node, and a second control electrode supplied with a second control signal. The control unit outputs the first control signal and the second control signal. When the main switching element is switched from on to off based on the first control signal, the control unit causes the first canceling element to generate charges generated at the second node based on the second control signal. Cancel.

  Note that the above semiconductor device can be applied between the output nodes of a comparator to control the reset operation of the comparator. Also, the semiconductor device is provided in parallel with each of the pair of differential input transistors of the comparator, and is configured to connect the control electrode of the main switching element in each semiconductor device to the control electrode of each differential input transistor. Can do.

  According to each embodiment, it is possible to provide a semiconductor device that can operate with higher accuracy and reliability by controlling an error amount associated with switching of the main switching element.

FIG. 1 is a diagram for schematically explaining charge injection and its countermeasures. It is a figure for demonstrating schematically a clock feedthrough and its countermeasure. It is a figure for demonstrating the principle of one Embodiment. It is a figure which shows 1st Example schematically. It is a figure which shows a 2nd Example schematically. It is a figure which shows a 3rd Example schematically. It is a figure which shows 4th Example schematically. It is a figure which shows the circuit for producing | generating the control signal in 4th Example shown in FIG. It is a figure which shows a 5th Example schematically.

First, the principle of one embodiment will be described with reference to FIG.
FIG. 3 is a diagram for explaining the principle of the embodiment. FIG. 3A shows a connection state between the main switching transistor 1 and the canceling transistor 2, and FIG. 3B shows the main switching transistor 1 and the canceling transistor. 3 shows how the voltage (Vgs) between the gate electrode and the source electrode of the transistor 2 changes with respect to time t.

  As shown in FIG. 3A, the canceling transistor 2 is connected to the drain electrode D1 of the main switching transistor 1 by short-circuiting the source electrode S2 and the drain electrode D2. Reference numeral 3 denotes a buffer amplifier that shapes the waveform of the signal of the drain electrode D1 of the main switching transistor 1 and outputs the signal. Note that the threshold voltages (gate electrode-source electrode voltage Vgs) of the main switching transistor 1 and the canceling transistor 2 are both Vth.

  As shown in FIG. 3B, when the main switching transistor 1 in the on state is changed to the off state, first, a high level “H” (V2) control signal applied to the gate electrode (gate electrode) The voltage CS1 starts to change to the low level “L” at timing t2, and the gate electrode voltage CS1 gradually decreases to become the same potential as the threshold voltage Vth at timing t3. After this timing t3, the main switching transistor 1 Turns off.

  At this time, the control signal (gate electrode voltage) CS2 applied to the gate electrode of the canceling transistor 2 changes from the low level “L” to the high level “H” at the timing t1 slightly before the timing t2, for example. Starts.

  With regard to charge injection, when the main switching transistor 1 is in an ON state, a channel is formed in the substrate facing the gate electrode G1, and the charge amount Qd is Qd = W × L × Cox × (Vgs−Vth). (W is the gate electrode width, L is the gate electrode length, Cox is the gate electrode oxide film thickness, Vgs is the voltage between the gate electrode G1 and the source electrode S1 of the main switching transistor 1 (between the gate electrode and the source electrode). Voltage) and Vth indicates the threshold voltage of the main switching transistor 1).

  That is, when the main switching transistor 1 and the canceling transistor 2 are operated, the charge compensation by the canceling transistor 2 is actually effective after the period P2 of the timing t3 when the main switching transistor 1 is turned off. In the previous period P1, since the main switching transistor 1 is in a conductive state, the charge is not held and becomes invalid.

  Therefore, the actual charge compensation amount is after timing t3 when the control signal (gate electrode voltage) CS1 of the gate electrode G1 at which the main switching transistor 1 is turned off becomes equal to or lower than the threshold voltage Vth, and the gate electrode of the canceling transistor 2 Only the period P2 in which the control signal (gate electrode voltage) CS2 of G2 is equal to or higher than the threshold voltage Vth.

  Thus, by controlling the gate electrode voltage CS1 of the main switching transistor 1 and the gate electrode voltage CS2 of the canceling transistor 2, the amount of charge compensation by the canceling transistor 2 changes.

  The same applies to clock feedthrough, but the difference from charge injection is that the voltage after charge injection exceeds the threshold voltage Vth is proportional to Vod (= Vgs−Vth), whereas clock feedthrough is different. Is simply a point proportional to the gate-source voltage Vgs.

  That is, the clock feedthrough depends on the gate electrode-source electrode voltage Vgs after the main switching transistor 1 is turned off, and controls the gate electrode voltage CS1 of the main switching transistor 1 and the gate electrode voltage CS2 of the canceling transistor 2. Thus, the potential after switching (after the main switching transistor 1 is turned off) can be controlled.

  In the above description, the canceling transistor 2 is provided only on the drain electrode D1 side of the main switching transistor 1. However, the canceling transistor 2 is also provided on the source electrode S1 side of the main switching transistor 1, so that the main switching transistor 1 is turned on. It can also be configured such that the charge when changing to the off state is compensated by two canceling transistors provided on both the drain electrode D1 and the source electrode S1 of the main switching transistor 1.

Hereinafter, embodiments of the semiconductor device will be described in detail with reference to the accompanying drawings.
FIG. 4 is a diagram schematically showing the first embodiment, FIG. 4 (a) is a circuit diagram, and FIG. 4 (b) is a timing diagram.

  As shown in FIG. 4A, the canceling transistor 2 is connected to the drain electrode D1 of the main switching transistor 1 by short-circuiting the source electrode S2 and the drain electrode D2. Here, reference numeral 4 is a control signal that receives the control signal CS and generates a control signal CS1 supplied to the gate electrode G1 of the main switching transistor 1 and a control signal CS2 supplied to the gate electrode G2 of the canceling transistor 2. A generation circuit is shown.

  As shown in FIG. 4B, the control signal generation circuit 4 receives the control signal CS that changes from the high level “H” to the low level “L” and is supplied to the gate electrode G 1 of the main switching transistor 1. The high level “H” control signal CS 1 is switched to the low level “L” to turn off the main switching transistor 1 and the low level “L” control signal CS 2 supplied to the gate electrode G 2 of the canceling transistor 2. The charge amount compensated (absorbed) by the canceling transistor 2 is adjusted by variably controlling the timing of switching to the high level “H”.

  4A, the pMOS transistor 1 ′ is connected in parallel to the source electrode S1 and the drain electrode D1 of the nMOS transistor 1, and the main switching element is configured as a complementary switch. You can also.

  FIG. 5 is a diagram schematically showing the second embodiment, FIG. 5 (a) is a circuit diagram, and FIG. 5 (b) is a timing diagram.

  As is clear from the comparison between FIG. 5A and FIG. 4A, in the second embodiment, a canceling capacitor 2 ′ is applied instead of the canceling transistor 2 of the first embodiment described above. It has become. In this way, by applying the canceling capacitor 2 'as the canceling element, unlike the case of the transistor, no channel is formed, so that error control by a simple electrostatic effect can be performed.

  As the canceling capacitor 2 ′, for example, a circuit wiring capacitor can be used in addition to the dedicated capacitor. Further, as indicated by broken line brackets in FIG. 5A, the gate electrode G2 is connected to the drain electrode D1 of the main switching transistor 1, and the source electrode S2 and the drain electrode D2 are commonly connected to generate a control signal. It is also possible to configure to receive the control signal CS2 from the circuit 4.

  FIG. 6 is a diagram schematically showing a third embodiment, FIG. 6 (a) is a circuit diagram, and FIG. 6 (b) is a timing diagram.

  As is apparent from a comparison between FIG. 6B and FIG. 4B, in the third embodiment, the control signal generation circuit 4 controls the control signal that changes from the high level “H” to the low level “L”. When CS is received, the control signal CS1 of high level “H” supplied to the gate electrode G1 of the main switching transistor 1 is switched to low level “L” to turn off the main switching transistor 1, and the canceling transistor 2 The amount of charge compensated (absorbed) by the canceling transistor 2 is adjusted by variably controlling the inclination of switching the low level “L” control signal CS2 supplied to the gate electrode G2 to the high level “H”. ing.

  Here, in order to adjust the slope (slew rate) of the control signal CS2 supplied to the gate electrode G2 of the canceling transistor 2, for example, there is a method of making the load capacitance of the node of the gate electrode G2 of the canceling transistor 2 variable. is there.

  FIG. 7 is a diagram schematically showing a fourth embodiment, showing an embodiment applied to a positive feedback latch type comparator. FIG. 7A is a circuit diagram of a positive feedback latch type comparator. FIG. 7B shows a timing chart of the control signals CS10, CS21 and CS22.

  As shown in FIG. 7A, in the latch type comparator of the fourth embodiment, each source electrode is connected to the high potential power supply line Vdd, and complementary input signals Vi + and Vi− are supplied to each gate electrode. PMOS transistors 41 and 42, source electrodes connected to the low potential power supply line Vss, drain electrodes and gate electrodes of each other are cross-connected, and nMOS transistors 51 and 52 constituting a latch, and drains of the pMOS transistors 41 and 42 Inverters 31 and 32 are connected to common connection nodes N1 and N2 between the electrodes and the drain electrodes of nMOS transistors 51 and 52 and output latched complementary signals Vo− and Vo +.

  Further, nMOS transistors 21, 10 and 22 are connected in series between common connection nodes N1 and N2. Here, the transistor 10 corresponds to the main switching transistor 1 described above, and the transistors 21 and 22 correspond to the canceling transistor 2. That is, the transistors 21, 10, and 22 connected in series are provided with canceling transistors 21 and 22 on the source electrode and the drain electrode of the main switching transistor 10, respectively, and when the main switching transistor 10 changes from an on state to an off state The charge is compensated by controlling the timing at which the two canceling transistors 21 and 22 change from the off state to the on state.

  That is, as shown in FIG. 7B, after the main switching transistor 10 is turned on by the high level “H” control signal CS10 to reset the comparator, the control signal CS10 is changed from the high level “H” to the low level. By changing to “L”, the main switching transistor 10 is turned off, the comparator is operated (positive feedback state), and the potential difference between the input signals Vi + and Vi− is determined.

  At this time, in the actual comparator (circuit), not only the influence of the charge generated when the main switching transistor 10 is changed from the on-state to the off-state, but also, for example, the input signal An error occurs in the determination of the potential difference between Vi + and Vi−.

  Therefore, in this embodiment, when the control signal CS10 is changed from the high level “H” to the low level “L” and the main switching transistor 10 transitions from the on state to the off state, the control signals of the canceling transistors 21 and 22 are controlled. The timing at which CS21 and CS22 are changed from the low level “L” to the high level “H” is individually controlled to compensate the determination error of the comparator.

  FIG. 8 is a diagram showing a circuit for generating a control signal in the fourth embodiment shown in FIG. 7, and FIG. 8A shows an example of the control signal generation circuit 4 for generating the control signals CS10, CS21 and CS22. FIG. 8B shows a circuit example of inverters (variable delay inverters) 44 and 45 for generating the control signals CS21 and CS22.

  As shown in FIG. 8A, the control signal generation circuit 4 includes two stages of inverters 42 and 43 connected in series, a control unit 41, and variable delay inverters 44 and 45 controlled by the control unit 41. It has.

  The control signal CS10 supplied to the gate electrode of the main switching transistor 10 is generated through the two-stage inverters 42 and 43, and the control signal CS21 supplied to the gate electrode of the first canceling transistor 21 is The control signal CS22 generated through the first variable delay inverter 44 and supplied to the gate electrode of the second canceling transistor 22 is supplied to the control signal CS22 through the second variable delay inverter 45. Generated.

  Here, the delay time of each of the first variable delay inverter 44 and the second variable delay inverter 45 is controlled independently by a signal from the control unit 41 that receives the outputs Vo + and Vo− and performs feedback control. As shown in FIG. 7B, the control signal CS10 of the main switching transistor 10 changes from the low level “L” to the high level at different timings with respect to the timing when the control signal CS10 changes from the high level “H” to the low level “L”. First and second control signals CS21 and CS22 that change to "H" are generated.

  As shown in FIG. 8B, the variable delay inverters 44 and 45 have the same configuration, and the control unit 41 is interposed between the inverter constituted by the pMOS transistor 402 and the nMOS transistor 403 and the high potential power supply line Vdd. A variable resistor 401 whose resistance value is controlled by a signal from is inserted. That is, by controlling the resistance value of the variable resistor 401, the inclination of the control signal CS21 (CS22) changing from the low level “L” to the high level “H” is controlled and absorbed by the canceling transistor 21 (22). The amount of charge to be controlled is controlled.

  The variable resistor 401 can be configured, for example, by digitally controlling the connection of a plurality of resistors provided in parallel, but a current source is provided instead of the variable resistor 401, and the current source The current value can also be controlled in an analog manner. Furthermore, the variable resistor 401 can be configured as a switch, and the timing at which the control signal CS21 (CS22) changes from the low level “L” to the high level “H” can be controlled by a signal from the control unit 41. Note that the resistance value in the variable resistor 401 is optimum by performing a calibration process, for example, at the test stage of an IC incorporating the comparator, or at the time of power-on actually using a device using the IC. Can be set to a value.

  FIG. 9 is a diagram schematically showing the fifth embodiment, and shows another example of a latch type comparator.

  As is clear from the comparison between FIG. 9 and FIG. 7A, the latch type comparator of the fifth embodiment includes the reset nMOS transistors 21, 10 and 22 in the latch type comparator of the fourth embodiment described above. In addition, the pMOS transistors 101, 201, 102, and 202 connected in series are connected in parallel to the source electrode and the drain electrode of the pMOS transistors 41 and 42, respectively, and the transistors 51 and 52 connected in common are connected. An nMOS transistor 60 is inserted between the source electrode and the low potential power supply line Vss.

  Here, the transistors 101 and 102 correspond to the main switching transistor 10 described above, and the transistors 201 and 202 correspond to the canceling transistor 21 (22) described above.

  In the comparator of the fifth embodiment, the control signals CS101 and CS102 of the main switching transistors 101 and 102 and the control signal CS60 of the transistor 60 are set to a low level “L” to turn on the main switching transistors 101 and 102 and After turning off and performing reset processing, the control signals CS101, CS102 and CS60 are changed from the low level “L” to the high level “H” to turn off the main switching transistors 101 and 102 and turn off the transistor 60. Change it to the on state. The potential difference between the input signals Vi + and Vi− is determined.

  At this time, the influence of the charge generated when the main switching transistors 101 and 102 are changed from the on state to the off state, and the determination error of the potential difference between the input signals Vi + and Vi− due to element variation in the manufacturing stage are as follows: Compensation is performed by controlling the timing or inclination of changing the canceling transistors 201 and 202 from the off state to the on state by the control signals CS201 and CS202, respectively. The control signals CS101, CS102, CS60, CS201, and CS202 supplied to the gate electrodes of the transistors 101, 102, 60, 201, and 202 can be generated by applying various conventionally known circuits. .

  Although the fourth and fifth embodiments described above show the latch type comparator, the present invention is not limited to the latch type comparator, and can be widely applied to various semiconductor devices.

Regarding the embodiment including the above first to fifth examples, the following additional notes are further disclosed.
(Appendix 1)
At least one main switching element having a first electrode connected to the first node, a second electrode connected to the second node, and a first control electrode for controlling connection between the first and second electrodes; ,
A canceling element that has a third electrode and a fourth electrode connected to the second node, and a second control electrode, and cancels an electric charge generated when the main switching element is switched from on to off. ,
A semiconductor device that variably controls driving of the canceling element with respect to a timing at which the main switching element switches from on to off.

(Appendix 2)
In the semiconductor device according to attachment 1,
The driving of the canceling element is a semiconductor that variably controls the timing of the second control signal for switching the canceling element from off to on with respect to the timing of the first control signal for switching the main switching element from on to off. apparatus.

(Appendix 3)
In the semiconductor device according to attachment 1,
The canceling element is driven by a semiconductor that variably controls the slope of the second control signal for switching the canceling element from off to on with respect to the timing of the first control signal for switching the main switching element from on to off. apparatus.

(Appendix 4)
At least one main switching element having a first electrode connected to the first node, a second electrode connected to the second node, and a first control electrode for controlling connection between the first and second electrodes; ,
A third electrode connected to the second node; a fourth electrode connected to the third node; and a second control electrode for controlling connection between the third and fourth electrodes; A canceling element that cancels the charge generated when the switch is turned from on to off, and
The second control electrode of the canceling element is connected to the first or second electrode of the main switching element, and the main switching element turns on the potential of the third or fourth electrode of the canceling element. Semiconductor device variably controlled with respect to the timing of switching from off to off.

(Appendix 5)
In the semiconductor device according to attachment 4,
A semiconductor device in which the potential of the third or fourth electrode of the canceling element is controlled at a variable timing with respect to a timing of switching the main switching element from on to off.

(Appendix 6)
In the semiconductor device according to attachment 4,
The semiconductor device in which the potential of the third or fourth electrode of the canceling element is controlled with a variable inclination with respect to the timing of switching the main switching element from on to off.

(Appendix 7)
In the semiconductor device according to any one of appendices 1 to 6,
The main switching element and the canceling element are transistors, and a transistor size of the canceling element is half of a transistor size of the main switching element.

(Appendix 8)
In the semiconductor device according to attachment 7,
The main switching element includes a first conductive type first main switching element and a second conductive type second main switching element, and the first and second main switching elements are connected in parallel to be complementary switches. The semiconductor device which comprises.

(Appendix 9)
At least one main switching element having a first electrode connected to the first node, a second electrode connected to the second node, and a control electrode for controlling the connection between the first and second electrodes;
A canceling capacitor that has a third electrode connected to the second node and a fourth electrode connected to the third node, and cancels a charge generated when the main switching element is switched from on to off; With
A semiconductor device that variably controls the potential of the fourth electrode of the canceling capacitor with respect to a timing at which the main switching element is switched from on to off.

(Appendix 10)
First and second transistors of a first conductivity type, each source electrode being connected to a first power supply line, and first and second input signals being supplied to each gate electrode;
A third electrode and a second transistor of the second conductivity type, each having a source electrode connected to the second power supply line and a drain electrode and a gate electrode cross-connected to form a latch;
A first common connection node between the drain electrode of the first transistor and the drain electrode of the third transistor; and a second common connection between the drain electrode of the second transistor and the drain electrode of the fourth transistor. A comparator that outputs a complementary signal latched from a node,
The semiconductor device according to any one of appendices 1 to 9 is provided between the first common connection node and the second common connection node, and the reset operation of the comparator is executed by the main switching element in the semiconductor device. A comparator to do.

(Appendix 11)
First and second transistors of a first conductivity type, each source electrode being connected to a first power supply line, and first and second input signals being supplied to each gate electrode;
A third electrode and a second transistor of the second conductivity type, each having a source electrode connected to the second power supply line and a drain electrode and a gate electrode cross-connected to form a latch;
A first common connection node between the drain electrode of the first transistor and the drain electrode of the third transistor; and a second common connection between the drain electrode of the second transistor and the drain electrode of the fourth transistor. A comparator that outputs a complementary signal latched from a node,
The semiconductor device according to any one of appendices 1 to 9 is provided in parallel with each of the first and second transistors, and the control electrode of the main switching element in each semiconductor device is connected to the first and second transistors. A comparator connected to each of the control electrodes.

1, 1 ';10; 101, 102 Main switching transistor (main switching element)
2; 21, 22; 201, 202 Canceling transistor (cancelling element)
2 'canceling capacity (cancellation element)
3 Buffer amplifier 4 Control signal generation circuit CS1; CS10; CS101, CS102 Main switching transistor control signal (gate electrode voltage)
CS2; CS21, CS22; CS201, CS202 Cancel transistor control signal (gate electrode voltage)
D1, D2 Drain electrode G1, G2 Gate electrode S1, S2 Source electrode

Claims (6)

At least one having a first electrode connected to the first node, a second electrode connected to the second node, and a first control electrode for controlling the connection between the first and second electrodes by a first control signal Two main switching elements,
A first canceling element having a third electrode and a fourth electrode connected to the second node, and a second control electrode to which a second control signal is supplied;
A control unit that outputs the first control signal and the second control signal,
The controller is
When switching the main switching element from on to off based on the first control signal, the charge generated in the second node is canceled by the first canceling element based on the second control signal;
A semiconductor device. The amount of charge canceled by the first canceling element is such that the level of the first control signal crosses the threshold voltage of the main switching element, the main switching element switches from on to off, and the second control Based on the amount of charge absorbed by the first canceling element across a threshold voltage of the first canceling element,
The semiconductor device according to claim 1. further,
A second canceling element having a fifth electrode and a sixth electrode connected to the first node, and a third control electrode supplied with a third control signal output from the control unit;
The controller is
When the main switching element is switched from on to off based on the first control signal, the charge generated at the first node is canceled by the second canceling element based on the third control signal;
The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. The amount of charge canceled by the second canceling element is such that the level of the first control signal crosses the threshold voltage of the main switching element, the main switching element is switched from on to off, and the third control signal is Based on the amount of charge absorbed by the second canceling element across the threshold voltage of the second canceling element,
The semiconductor device according to claim 3. The control unit separately and independently controls the second control signal and the third control signal;
The semiconductor device according to claim 3, wherein the semiconductor device is a semiconductor device. The main switching element includes a first conductive type first main switching element and a second conductive type second main switching element connected in parallel to the first main switching element.
The semiconductor device according to claim 1, wherein:

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