JP2013009138A - High frequency switch circuit and composite high frequency switch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high frequency switch circuit that keeps a gate-body voltage within the withstanding voltage of a MOSFET with high reliability.SOLUTION: In the high frequency switch circuit having the MOSFET and a control circuit capable of controlling gate and body potentials of the MOSFET, the control circuit includes a timing control circuit, and the timing control circuit can change the gate potential of the MOSFET before changing the body potential when a high frequency signal path is switched from a connected state to a disconnected state, and can change the body potential of the MOSFET before changing the gate potential when the disconnected state is changed to the connected state.

Description

  The present invention relates to a high-frequency switch circuit and a composite high-frequency switch circuit for high-frequency signals used in wireless devices such as mobile phones.

In a wireless device that performs transmission / reception by switching a plurality of radio systems, the antenna is selectively connected to one of the plurality of transmission circuits or reception circuits by a high-frequency switch circuit, and at the same time, an unselected transmission circuit or reception circuit Is not connected. This makes it possible to share a single antenna among multiple frequency bands or communication systems, and reduce the number of antennas in the wireless device, enabling downsizing and cost reduction of the wireless device. Become.
Conventionally, this high-frequency switch circuit has been prepared using a compound semiconductor, but in recent years, replacement with a MOS field-effect transistor (hereinafter simply referred to as a MOSFET), which can be manufactured at low cost, has been studied.

  In a silicon MOSFET, it is required to reduce harmonic distortion. Patent Document 1 proposes a technique for controlling the body potential of a silicon MOSFET. Patent Document 2 proposes a control circuit thereof.

Special table 2009-500868 JP 2010-28304 A

  A four-terminal type in which the source, drain, gate and body are separated is used for the MOSFET. With this type of MOSFET, the breakdown voltage between the gate and the body has been reduced because the thickness of the oxide film has decreased with the miniaturization. In Patent Document 2, a positive voltage is applied to the gate when the switch circuit is connected, and a negative voltage is applied to the body when the switch circuit is disconnected. Therefore, depending on the timing of switching the state of the switch circuit, an excessive voltage exceeding the breakdown voltage may be applied between the gate and the body.

  The point where this excessive voltage is applied will be described with reference to the block diagram of FIG. 12 showing a conventional high-frequency switch circuit. A conventional high-frequency switch circuit 100 includes a MOSFET 8, a control terminal 1, level shift circuits 11 and 12, a gate terminal 41 connected to the gate of the MOSFET 8, and a body terminal 42 connected to the body of the MOSFET 8. 200. The level shift circuit 11 is connected to the gate terminal 41 of the MOSFET 8 and controls the gate potential. The level shift circuit 12 is connected to the body terminal 42 of the MOSFET 8 and controls the body potential. The MOSFET 8 has a gate-body breakdown voltage of 3V.

The level shift circuit 11 is supplied with a first potential and a third potential from a power supply terminal (not shown). The level shift circuit 11 outputs a first potential of 2.5 V when a high potential of 2.5 V is input from the control terminal 1, and outputs a third potential of −2.5 V when a low potential of 0 V is input. Output.
The level shift circuit 12 is supplied with a second potential and a third potential from a power supply terminal (not shown). The level shift circuit 12 outputs the second potential 0V when the High potential 2.5V is input, and outputs the third potential −2.5V when the Low potential 0V is input.

When a high potential of 2.5 V is applied from the control terminal 1, the MOSFET 8 in the switch unit is applied with a potential of 2.5 V at the gate and 0 V at the body. At this time, since the voltage between the gate and the body is 2.5 V, which is equal to or lower than the withstand voltage, the MOSFET 8 can be driven in a state in which reliability is ensured.
However, reliability is not always ensured even when the potential of the control terminal changes from the high potential of 2.5 V to the low potential of 0 V. If the level shift circuit 11 has a longer delay time than the level shift circuit 12, the potential on the body side first changes from the second potential 0V to the third potential -2.5V. At this time, the voltage between the gate and the body is 2.5 V − (− 2.5 V) = 5.0 V obtained by subtracting the third potential from the first potential, which exceeds the withstand voltage of the MOSFET 8 in the switch portion. It becomes a problem in reliability.

  In order to prevent the voltage between the gate and the body from exceeding the withstand voltage, for example, the delay time of the level shift circuit 12 may be lengthened, and the delay times of both level shift circuits may be the same. However, in this case, since the delay time of the level shift circuit 12 is lengthened, when the control terminal changes from the low potential to the high potential, the potential on the gate side first changes. For this reason, since a potential of 2.5 V is applied to the gate and −2.5 V to the body, the voltage between the gate and the body exceeds the breakdown voltage as described above, making it difficult to ensure reliability.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a high-reliability high-frequency switch circuit and a composite high-frequency switch circuit that can make the voltage between the gate and the body less than the breakdown voltage of the MOSFET when switching between connection and non-connection of the high-frequency signal path. It is to be realized.

The present invention is a high frequency switch circuit comprising a MOSFET arranged in a high frequency signal path and a control circuit capable of controlling the potential of the gate and body of the MOSFET,
The control circuit includes a timing control circuit,
The timing control circuit is capable of switching the body potential after switching the gate potential of the MOSFET when the high-frequency signal path is switched from the connected state to the disconnected state, and connected from the disconnected state. When switching to a state, the gate potential can be switched after the body potential of the MOSFET is switched.

The control circuit can switch the potential of the gate to the first potential or the third potential, and can switch the potential of the body to the second potential or the third potential.
The second potential may be set lower than the first potential, and the third potential may be set lower than the second potential.

  The potential difference between the first potential and the third potential is preferably larger than the gate-body breakdown voltage of the MOSFET.

The above high frequency switch circuit is
The control circuit includes a control terminal to which a high potential and a low potential are applied, a timing control circuit connected to the control terminal, a gate terminal connected to the gate of the MOSFET, and a body terminal connected to the body. With
The timing control circuit includes an AND circuit and an OR circuit, one input terminal of the AND circuit and one input terminal of the OR circuit are connected to the control terminal, and an output terminal of the AND circuit is the OR circuit. Connected to the other input terminal of the circuit, the output terminal of the OR circuit is connected to the other input terminal of the AND circuit,
A first node between the output terminal of the AND circuit and the other input terminal of the OR circuit is connected to the gate terminal, and between the output terminal of the OR circuit and the other input terminal of the AND circuit. The second node may be connected to the body terminal.

  It is preferable that a first level shift circuit is disposed between the first node and the gate terminal, and a second level shift circuit is disposed between the second node and the body terminal.

  In the timing control circuit, it is preferable that delay means is disposed between at least one of the first node and the other input terminal of the OR circuit and between the second node and the other input terminal of the AND circuit. .

In addition, as a high-frequency switch circuit of another configuration,
The control circuit includes a control terminal to which a high potential and a low potential are applied, a timing control circuit connected to the control terminal, a gate terminal connected to the gate of the MOSFET, and a body terminal connected to the body. With
The timing control circuit includes an AND circuit, an OR circuit, and first to fourth level shift circuits, and one input terminal of the AND circuit and one input terminal of the OR circuit are connected to the control terminal. The output terminal of the AND circuit and the other input terminal of the OR circuit are connected, and the first and third level shift circuits are arranged in the connected path, and the output terminal of the OR circuit The other input terminal of the AND circuit is connected, and the second and fourth level shift circuits are arranged in the connected path,
A third node between the first and third level shift circuits is connected to a gate terminal connected to the gate of the MOSFET;
A fourth node between the second and fourth level shift circuits may be connected to a body terminal connected to the body of the MOSFET.

In addition, as a high-frequency switch circuit of another configuration,
The control circuit includes a control terminal to which a high potential and a low potential are applied, a timing control circuit connected to the control terminal, a gate terminal connected to the gate of the MOSFET, and a body terminal connected to the body. With
The timing control circuit includes a NOR circuit, a NAND circuit, and first to third NOT circuits, an input terminal of the first NOT circuit is connected to the control terminal, and an output terminal of the first NOT circuit Are connected to one input terminal of the NOR circuit and one input terminal of the NAND circuit,
The output terminal of the NOR circuit and the other input terminal of the NAND circuit are connected, and the second NOT circuit is arranged in the connected path,
The output terminal of the NAND circuit and the other input terminal of the NOR circuit are connected, and the third NOT circuit is arranged in the connected path,
A fifth node between the output terminal of the NOR circuit and the second NOT circuit is connected to the gate terminal, and a sixth node between the output terminal of the NAND circuit and the third NOT circuit Can be connected to the body terminal.

  It is preferable that a first level shift circuit is disposed between the fifth node and the gate terminal, and a second level shift circuit is disposed between the sixth node and the body terminal.

  Between the fifth node and the second NOT circuit, between the second NOT circuit and the other input terminal of the NAND circuit, or between the sixth node and the third NOT circuit, or It is preferable that a delay unit is disposed at least one between the third NOT circuit and the other input terminal of the NOR circuit.

In addition, as a high-frequency switch circuit of another configuration,
The control circuit includes a control terminal to which a high potential and a low potential are applied, a timing control circuit connected to the control terminal, a gate terminal connected to the gate of the MOSFET, and a body terminal connected to the body. With
The timing control circuit includes a NOR circuit, a NAND circuit, first to third NOT circuits, and first to fourth level shift circuits, and an input terminal of the first NOT circuit is connected to the control terminal. The output terminal of the first NOT circuit is connected to one input terminal of the NOR circuit and one input terminal of the NAND circuit, respectively.
The output terminal of the NOR circuit and the other input terminal of the NAND circuit are connected, and the first and third level shift circuits are arranged in the connected path,
The output terminal of the NAND circuit and the other input terminal of the NOR circuit are connected, and the second and fourth level shift circuits are arranged in the connected path,
A seventh node between the first and third level shift circuits is connected to the gate terminal; an eighth node between the second and fourth level shift circuits is connected to the body terminal;
The second NOT circuit is arranged between the seventh node and the third level shift circuit, or between the third level shift circuit and the other input terminal of the NAND circuit, and The third NOT circuit may be arranged between a node and the fourth level shift circuit, or between the fourth level shift circuit and the other input terminal of the NOR circuit.

  A composite high-frequency switch circuit using a plurality of the high-frequency switch circuits, wherein control terminals of the plurality of high-frequency switch circuits are respectively connected to a common control terminal, and at least one of the high-frequency switch circuits includes a NOT circuit as the control terminal. The high-frequency switch circuit connected to the common control terminal via the NOT circuit is connected to the common control terminal via the NOT control circuit by a potential applied from the common control terminal. Thus, it is possible to provide a composite high-frequency switch circuit that switches so that connection / disconnection of each high-frequency signal path is reversed.

A composite high-frequency switch circuit using a plurality of the above high-frequency switch circuits,
A single-pole multi-throw switch circuit having a common terminal and a plurality of branch terminals connected via a high-frequency signal path branched from the common terminal;
A complex high-frequency switch circuit in which the high-frequency switch circuit is arranged in each of the branched high-frequency signal paths can be provided.

  According to the present invention, an inexpensive MOSFET is used, and the high-reliability high-frequency that can maintain the voltage between the gate and body of the MOSFET below the breakdown voltage of the MOSFET when the connection and disconnection of the high-frequency signal path are switched. A switch circuit and a composite high-frequency switch circuit can be realized.

It is a block diagram of the high frequency switch circuit of an embodiment. It is a block diagram of the high frequency switch circuit of another embodiment. It is a block diagram of the high frequency switch circuit of another embodiment. It is a block diagram of the high frequency switch circuit of another embodiment. It is a block diagram of the high frequency switch circuit of another embodiment. 2 is a block diagram illustrating an example of level shift circuits 11 and 12. FIG. 3 is a block diagram illustrating an example of a level shift circuit 13. FIG. 3 is a block diagram illustrating an example of a level shift circuit 14. FIG. It is a block diagram which shows an example of a delay means. It is a block diagram of a composite high frequency switch circuit. It is a block diagram of another composite high frequency switch circuit. It is a block diagram of the conventional high frequency switch circuit.

  Embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited to these embodiments.

The high-frequency switch circuit of this embodiment includes a MOSFET and a control circuit that can control the potential of the gate and body of the MOSFET.
The control circuit includes a timing control circuit. When the high-frequency signal path switches from the connected state to the disconnected state, the timing control circuit can switch the MOSFET body potential after switching the MOSFET gate potential, and from the disconnected state to the connected state. When switching, it is possible to switch the MOSFET gate potential after switching the MOSFET body potential. In the present invention, the high-frequency signal path includes not only a path connecting the first signal terminal on the signal input side and the second signal terminal on the output side but also a path grounded from a node of this path to the ground. Shall be.

The control circuit can switch the gate potential to the first potential or the third potential, and can switch the body potential to the second potential or the third potential.
The second potential is set to be lower than the first potential, and the third potential is set to be lower than the second potential.
When the potential difference between the first potential and the third potential is larger than the breakdown voltage between the gate and body of the MOSFET, a high-frequency switch circuit with high reliability can be realized by employing the high-frequency switch circuit of this embodiment.
In the above description, the lower potential on the gate side and the lower potential on the body side are the same third potential. However, it is not always necessary to have the same potential, and a current substantially flows between the source and the drain. Any potential difference can be set as appropriate.

As the MOSFET, a four-terminal type MOSFET in which a source, a drain, a gate, and a body are separated is used. Either an SOI (Silicon on Insulator) type MOSFET or an SOS (Silicon on Sapphire) type MOSFET can be used.
For example, an SOI-type n-type MOSFET is formed on a dielectric layer formed on a silicon substrate, a gate is formed on an oxide film formed on the dielectric layer, and a body is formed of the oxide film. Formed below. The gate and the body are galvanically insulated by this oxide film, and the body is composed of a region doped with a p-type dopant formed in the dielectric layer. The source is a region adjacent to the body of the dielectric layer and is a region heavily doped with an n-type dopant. The drain is a region adjacent to the opposite side of the source of the body of the dielectric layer, and similarly comprises a region heavily doped with an n-type dopant.
In this embodiment, the breakdown voltage between the gate and body of the MOSFET is set to 3.0V.

  The high-frequency signal path is, for example, a path that connects between the first signal terminal 2 and the second signal terminal 3. In this case, one of the source and the drain of the MOSFET is connected to the first signal terminal 2, and the other of the source and the drain is connected to the second signal terminal 3. A circuit structure in which another MOSFET is disposed in another high-frequency signal path connected to the high-frequency signal path may be employed.

  The first signal terminal and the second signal terminal of the high-frequency signal path are connected to a second potential via a resistor or an inductor to determine the source or drain potential of the MOSFET.

Example 1
The high frequency switch circuit 100a of FIG. 1 will be described. The MOSFET 8 has the structure described above, and a description thereof is omitted.
The control circuit 200a will be described.
The control circuit 200a is connected to a control terminal 1 to which a high potential or a low potential is applied, a timing control circuit 201a connected to the control terminal, a gate terminal 41 connected to the gate of the MOSFET, and a body. The body terminal 42 is provided. In the embodiment, the high potential is 2.5 V and the low potential is 0 V.
The timing control circuit 201a includes an AND circuit 4 and an OR circuit 5, and one input terminal of the AND circuit 4 and one input terminal of the OR circuit 5 are connected to the control terminal 1, and the AND circuit 4 is connected to the other input terminal of the OR circuit 5, and the output terminal of the OR circuit 5 is connected to the other input terminal of the AND circuit 4.
A first node n1 between the output terminal of the AND circuit 4 and the other input terminal of the OR circuit 5 is connected to the gate terminal 41, and the output terminal of the OR circuit 5 and the other of the AND circuit 4 are connected. A second node n2 between the input terminals is connected to the body terminal.

  In the control circuit 200a, the first level shift circuit 11 is disposed between the first node n1 and the gate terminal 41, and the second level is between the second node n2 and the body terminal 42. A shift circuit 12 is arranged.

The first level shift circuit 11 includes a first power supply terminal to which at least a first potential 2.5V (hereinafter simply referred to as a first potential) is supplied, and a third potential −2.5V (hereinafter simply referred to as a first potential). The third power supply terminal to which a potential of 3 is supplied is connected. When a high potential of 2.5 V (hereinafter simply referred to as a high potential) is applied from the input terminal side connected to the first node n1, the first level shift circuit 11 receives the first level shift circuit 11 from the output terminal on the body terminal side. When a low potential of 0 V (hereinafter simply referred to as a low potential) is applied, a third potential is output.
The second level shift circuit 12 includes at least a second power supply terminal to which a second potential 0V (hereinafter simply referred to as a second potential) is supplied and a third power supply terminal to which a third potential is supplied. Is connected. The second level shift circuit 12 outputs a second potential from the output terminal on the body terminal side when a high potential of 2.5 V is applied from the input terminal side connected to the second node n2, and the Low level shift circuit 12 When a potential is applied, a third potential is output.

  Table 1 shows the first to third potentials output from the level shift circuit, the high potential of the control terminal, the low potential, and the gate-body breakdown voltage of the MOSFET.

  As described above, when the high potential and the low potential supplied from the control terminal 1 are equal to the second potential and the third potential, the second level shift circuit 12 is omitted. You can also. In this case, the first level shift circuit uses a circuit having a function of shifting the High potential to 2.5V and outputting the Low potential as it is at −2.5V.

As the level shift circuit 11, for example, a circuit shown in FIG. 6A can be used. In FIG. 6A, Tr1 to Tr10 are first to tenth MOSFETs. Hereinafter, the MOSFET is simply referred to as Tr for simplification. Of these, Tr1, 2, 5, 6, and 9 are p-type MOSFETs, and at least Tr1, 2, 5, and 6 use transistors having the same characteristics and the same gate width and withstand voltage. Tr3, 4, 7, 8, and 10 are n-type MOSFETs, and at least Tr3, 4, 7, and 8 use transistors having the same characteristics with the same gate width and breakdown voltage. In the level shift circuit, the high potential and the first potential are the same potential, and the low potential and the second potential are the same potential. Both p-type and n-type transistors are enhancement type.
The gates of Tr9 and Tr10 are connected to the input terminal 111 of the level shift circuit. The source of the p-type Tr9 is connected to the first power supply terminal Vc1. The source of the n-type Tr10 is connected to the second power supply terminal Vc2. The drains of Tr9 and Tr10 are connected to each other. Tr9 and Tr10, and first and second power supply terminals Vc1 and Vc2 constitute a CMOS inverter circuit.
A node between the drains of Tr9 and Tr10 is connected to the gate of Tr1. The gate of Tr2 is connected to the second power supply terminal Vc2. The sources of Tr1 and Tr5 are connected to the first power supply terminal Vc1. The drains of Tr1 and Tr5 are connected to the sources of Tr2 and Tr6.
The drains of Tr2 and Tr6 are connected to the drains of Tr3 and Tr7. The sources of Tr3 and Tr7 are connected to the drains of Tr4 and Tr8. The sources of Tr4 and Tr8 are connected to the third power supply terminal Vc3.
The gate of Tr4 is connected to a node between the source of Tr7 and the drain of Tr8. The gate of Tr8 is connected to a node between the source of Tr3 and the drain of Tr4.
The gates of Tr2, 3, 6, and 7 are connected to the second power supply terminal.
The output terminal 112a is connected to a node between the drain of Tr2 and the drain of Tr3.

The operation of the level shift circuit 11 in FIG.
When a high potential is supplied from the input terminal 111, a second potential is supplied to the gate of Tr1 by the CMOS inverter circuit. Since the first potential is supplied to the source of Tr1, the gate-source voltage is -2.5V, and the source and drain of Tr1 are connected. Similarly, Tr2 is also connected between the source and drain. On the other hand, the first potential, which is a high potential, is supplied to the gate of Tr5, and the first potential of the first power supply terminal Vc1 is also supplied to the source, so that the source and drain of Tr5 are not connected. It becomes. In this state, the source of Tr3 and the gate of Tr8 are at the second potential, and the source of Tr7 and the gate of Tr4 are at the third potential and are stabilized. Since the drain of Tr6 is at the third potential and the second potential is supplied to the gate of Tr6, the source of Tr6 is at the second potential from the balance with Tr5. Since the gate and the source of Tr3 and Tr4 have the same potential, no current flows between the source and the drain. As a result, the first potential supplied from the first power supply terminal Vc1 is output from the output terminal 112a.
On the other hand, when a low potential is supplied from the input terminal 111, the first potential is supplied to both the gate and the source of Tr1, so that no current flows between the source and the drain of Tr1. Since the gate of Tr5 is supplied with a low potential and the first potential from the first power supply terminal is supplied to the source, the source and drain of Tr5 are connected. Similarly, since the source and the drain of Tr6 are also connected, the first potential from the first power supply terminal is supplied to the drain of Tr7. A second potential is supplied from the second power supply terminal to the gates of Tr3 and Tr7. In this state, the source of Tr7 and the gate of Tr4 are the second potential, and the source of Tr3 and the gate of Tr8 are the third potential. Stable at a potential of. At this time, since the source and drain of Tr3 and Tr4 are connected, the third potential supplied from the third power supply terminal Vc3 is output from the output terminal 112a.

  As the level shift circuit 12, for example, a circuit shown in FIG. 6B can be used. For the level shift circuit 11 of FIG. 6A, the output terminal 112b is connected to the gate of the eighth Tr. By using the same configuration as in FIG. 6A, the characteristics can be stably obtained by the level shifters 11 and 12, and unlike the case of FIG. 6A, the second potential or the third potential is output. It can be a potential. Description of the operation of the level shift circuit 12 is omitted.

  In the block circuit of FIG. 1, the level shift circuits 11 and 12 are described separately from the AND circuit 4 and the OR circuit 5, but some circuit elements may be shared in the actual circuit. For example, when an inverter circuit is used for the output of the AND circuit 4 or the OR circuit 5, this can be shared.

The operation of the control circuit 200a will be described.
First, a case where a high potential is supplied to the control terminal 1 will be described.
When a high potential is supplied to the control terminal 1, the output terminal side of the OR circuit 5 also becomes a high potential.
Since the first input terminal of the AND circuit 4 is connected to the control terminal, the first input terminal side is at a high potential, and the second input terminal is also connected to the output terminal of the OR circuit 5, so that the second input terminal is connected. The input terminal side is also at a high potential. Thus, a high potential is output from the output terminal side of the AND circuit 4.
The second level shift circuit 12 receives the High potential supplied from the output terminal of the OR circuit 5 and outputs the second potential to the body terminal 22. On the other hand, the first level shift circuit 11 receives the High potential supplied from the output terminal of the AND circuit 4 and outputs the first potential to the gate terminal 21. At this time, the voltage between the gate and body of the MOSFET becomes 2.5 V, and the drain and source are connected. As a result, the high-frequency signal path is connected.

Next, a state in which the potential supplied to the control terminal 1 is switched from a high potential to a low potential will be described.
When the potential supplied to the control terminal 1 is switched from the high potential to the low potential, the output terminal side of the OR circuit 5 maintains the high potential until the output terminal side of the AND circuit 4 becomes the low potential. That is, the OR circuit 5 is temporarily supplied with the High potential from the second input terminal even if the Low potential of the control terminal is supplied from the first input terminal. A high potential is output. On the other hand, since the AND circuit 4 is supplied with a high potential from the second input terminal and is supplied with the low potential of the control terminal from the first input terminal, the AND circuit 4 is supplied with a low potential from the output terminal. A potential is output, and a low potential is supplied to the node n1. After that, since the OR circuit 5 is supplied with the Low potential from the second input terminal, the Output terminal of the OR circuit 5 outputs the Low potential, and becomes the Low potential at the node n2.
In this manner, the node n1 is first set to the low potential, and then the node n2 is switched to the low potential. Using this timing difference, the potential of the gate terminal 41 can be lowered from the first potential to the third potential first, and then the body side potential can be lowered from the second potential to the third potential. As described above, the voltage between the gate and the body of the MOSFET of the switch circuit portion is kept in a range not exceeding the breakdown voltage.
In a state where the Low potential is supplied from the control terminal, the node n1 on the output terminal side of the AND circuit 4 is always Low, and the first and second input terminal sides of the OR circuit 5 are also Low, so the OR circuit 5 The node n2 on the output terminal side is also Low, and the MOSFET of the switch circuit portion also keeps the cutoff state.

Next, a state in which the potential supplied to the control terminal 1 is switched from the low potential to the high potential will be described.
When the potential supplied to the control terminal 1 is switched from the low potential to the high potential, the output terminal side of the AND circuit 4 maintains the low potential until the output terminal side of the OR circuit 5 becomes the high potential. That is, the OR circuit 5 is supplied with the High potential of the control terminal from the first input terminal, so that the High potential is first output from the output terminal. On the other hand, the AND circuit 4 is supplied with the High potential of the control terminal from the first input terminal at this time, but is temporarily supplied with the Low potential from the second input terminal. When the High potential is output from the output terminal of the circuit 5, the output terminal side of the AND circuit 4 remains at the Low potential. After that, since the High potential supplied from the output terminal of the OR circuit 5 is supplied to the second input terminal of the AND circuit 4, the AND circuit 4 is supplied with the High potential at both the first and second input terminals. In response, a high potential is supplied from the output terminal.
In this way, the node n2 is first set to the high potential V, and then the node n1 is switched to the high potential. Using this timing difference as it is, the potential of the body terminal 42 is first raised from the third potential to the second potential, and then the potential of the gate terminal 41 is changed from the third potential −2.5 V to the first potential 2. Can be raised to 5V. In this way, the voltage between the gate and body of the MOSFET is kept in a range that does not exceed the breakdown voltage.

(Example 2)
The block diagram of FIG. 2 differs from the block diagram of FIG. 1 in that the timing control circuit 201b includes delay units 21 and 22. The elements and circuits having the same reference numerals as those in FIG. 1 are the same in structure and effect, and thus description thereof is omitted.
In the timing control circuit, delay means (21 or 22) is arranged between at least one of the first node n1 and the OR circuit 5 and between the second node n2 and the AND circuit 4.
In the circuit of FIG. 2, the first delay means 21 is disposed between the first node n1 and the OR circuit 5, and the second delay means 22 is disposed between the second node n2 and the AND circuit 4. It is the structure which was made.
By arranging the delay means 21 and 22, it becomes possible to increase the timing difference in switching between the high potential and the low potential at the node n1 and the node n2, and the control with a large delay time difference between the level shift circuits 11 and 12 is achieved. Even in the circuit, the switching timing can be maintained so that the voltage between the gate and the body of the MOSFET does not exceed the breakdown voltage.
When the delay time of the level shift circuit 11 is even longer, when the potential of the control terminal changes from the high potential to the low potential, the potential on the body side changes from the second potential to the third potential at an earlier timing. Therefore, the timing at which the body-side potential changes is earlier than the timing at which the gate-side potential changes, and the gate-body voltage tends to exceed the breakdown voltage of the MOSFET 8. The timing control circuit 201a in FIG. 1 is also driven so as to lower the potential of the node n2 after the potential of the node n1 decreases. However, the timing control circuit 201b in which the delay means 21 is arranged decreases the potential of the node n1 and the node n2. Since the timing difference is further increased, the potential on the gate side can be lowered at an earlier timing than the potential on the body side even if the delay time of the level shift circuit 11 is further increased. This ensures that the voltage between the gate and body of the MOSFET does not exceed the breakdown voltage.
On the other hand, when the delay time of the level shift circuit 12 is large, when the potential of the control terminal changes from the low potential to the high potential, the potential on the gate side is changed from the third potential to the first potential at an earlier timing. Therefore, the timing at which the potential on the gate side changes is earlier than the timing at which the potential on the body side changes, and the gate-body voltage tends to exceed the breakdown voltage of the MOSFET 8. The timing control circuit 201a is also driven so as to increase the potential of the node n1 after the potential of the node n2 decreases. However, the timing control circuit 201b in which the delay means 22 is arranged has a difference in timing when the potential of the node n2 and the node n1 increases. Therefore, even if the delay time of the level shift circuit 12 is further increased, the potential on the body side can be raised earlier than the potential on the gate side. This ensures that the voltage between the gate and body of the MOSFET does not exceed the breakdown voltage.
When the control circuit 200b is configured with the delay times of the level shift circuit 11 and the level shift circuit 12 unknown, the timing control circuit 201b includes both the delay means 21 and the delay means 22 as shown in FIG. It is preferable. In either case where the potential of the control terminal 1 is changed from a high potential to a low potential, or from a low potential to a high potential, the timing of the potential change at the node n1 and the node n2 can be increased, so that the level shift Even if the magnitude relationship between the delay times of the circuit 11 and the level shift circuit 12 is unknown, it is possible to make the structure that the voltage between the gate and the body of the MOSFET does not exceed the withstand voltage.

  FIG. 9 shows an example of the delay means. FIG. 9A shows a structure in which a resistor R3 is disposed between the input terminal 211a and the output terminal 212a of the delay means, and a node between the resistor R3 and the output terminal 212a is grounded via the capacitor C1. Prepare. FIG. 9B has a structure in which an even number of inverter circuits 301 and 302 having the same configuration are arranged in series between the input terminal 211b and the output terminal 212b of the delay means.

(Example 3)
3 is different from the block diagram of FIG. 1 in that a level shift circuit is included in the timing control circuit 201c (between the control terminal and the nodes n3 and n4), and the timing control circuit 201c and the gate terminal 41 are included. The difference is that no level shift circuit is required between the body terminals 42. Also, the elements and circuits having the same reference numerals as those in FIG.
The timing control circuit 201c will be described.
The timing control circuit 201 c includes an AND circuit 4, an OR circuit 5, and first to fourth level shift circuits 11 to 14, and one input terminal of the AND circuit 4 and one input terminal of the OR circuit 5. Are connected to the control terminal 1, the output terminal of the AND circuit 4 and the other input terminal of the OR circuit 5 are connected, and the first and third level shift circuits are connected to the connected path. 11 and 13 are arranged, the output terminal of the OR circuit 5 and the other input terminal of the AND circuit 4 are connected, and the second and fourth level shift circuits 12 and 14 are connected to the connected path. Arranged,
A third node n3 between the first and third level shift circuits 11 and 13 is connected to a gate terminal 41 connected to the gate of the MOSFET 8,
A fourth node n4 between the second and fourth level shift circuits 12 and 14 is connected to a body terminal 42 connected to the body of the MOSFET 8.

The operation of the high frequency switch circuit of FIG. 3 will be described.
The timing control circuit 201c can change the switching timing of the high potential and the low potential at the node n1 and the node n2 by the operation of the AND circuit 4 and the OR circuit 5, and this technical operation is illustrated in FIG. 1 is the same as the high-frequency circuit 1.
In the high-frequency switch circuit of FIG. 3, the potential of the node n3 is switched between the first potential and the third potential by the level shift circuits 11 and 12 arranged inside the timing control circuit 201c, and the potential of the node n4 is changed to the first potential. Switching between 2 and the third potential. The potential switched by the level shift circuit 11 is switched again to the High potential and Low potential supplied to the control terminal 1 by the level shift circuit 13 and the potential is supplied from the second input terminal of the OR circuit 5. Is done. Similarly, the potential switched by the level shift circuit 12 is switched to the High potential and the Low potential supplied again to the control terminal by the level shift circuit 14, and the potential is switched from the second input terminal of the AND circuit 4. Supplied.

As the level shift circuit 13, for example, a circuit shown in FIG. 7 can be used. This level shift circuit can be used for a switch circuit in which the first potential is the same as the high potential and the second potential is the same as the low potential. An intermediate potential between the first potential and the third potential is the second potential.
The operation of the level shift circuit 13 will be described.
The input terminal 111b is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to one end of the first resistor r1. The other end of the first resistor R1 is connected to the first power supply terminal Vc1. The resistance values of the first resistor R1 and the second resistor Rr2 are the same.
The output terminal 112c is connected to a node between the first resistor R1 and the second resistor R2.
When a high potential is supplied from the output terminal 111b, the high potential and the first potential from the first power supply terminal are the same, so the first potential is also output from the output terminal 112c.
When a low potential is supplied from the output terminal 111b, the output terminal 112c outputs a second potential that is intermediate between the low potential (third potential) and the first potential from the first power supply terminal. The

As the level shift circuit 14, for example, the circuit shown in FIG. 8 can be used.
The level shift circuit 14 has the same configuration as the level shift circuit 12 in FIG. 6B except that the first and third power supply terminals are replaced with the third and first power supply terminals. A description of the operation of the level shift circuit 14 is omitted.

Example 4
The high frequency switch circuit of FIG. 4 will be described. The elements and circuits having the same reference numerals as those in FIG. 1 are the same in structure and effect and will not be described.
The timing control circuit 201d includes a NOR circuit 6, a NAND circuit 7, and first to third NOT circuits 31 to 33, and an input terminal of the first NOT circuit 31 is connected to the control terminal 1, and the first The output terminal of one NOT circuit 31 is connected to one input terminal of the NOR circuit 6 and one input terminal of the NAND circuit 7,
The output terminal of the NOR circuit 6 and the other input terminal of the NAND circuit 7 are connected, and a second NOT circuit 32 is arranged in the connected path.
The output terminal of the NAND circuit 7 and the other input terminal of the NOR circuit 6 are connected, and a third NOT circuit 33 is disposed on the connected path.
A fifth node n5 between the output terminal of the NOR circuit 6 and the second NOT circuit 32 is connected to the gate terminal 41, and the output terminal of the NAND circuit 7 and the third NOT circuit 33 A sixth node n6 therebetween is connected to the body terminal 42.

The operation of the timing control circuit 201d will be described.
First, a case where a high potential is supplied to the control terminal 1 will be described.
When a high potential is supplied to the control terminal 1, the output terminal side of the first NOT circuit 31 is inverted to become a low potential.
The output terminal side of the NAND circuit 7 connected to the output terminal of the first NOT circuit 31 has a high potential.
Since the first input terminal of the NOR circuit 6 is connected to the output terminal of the first NOT circuit 31, the first input terminal side has a low potential. Further, since the second input terminal is connected to the High potential supplied to the output terminal of the NAND circuit 7 via the third NOT circuit 33, the potential becomes Low. Thus, a high potential is output from the output terminal of the NOR circuit 6.
The first level shift circuit 11 receives the High potential from the NOR circuit 6 and outputs the first potential to the gate terminal 41. On the other hand, the second level shift circuit 12 receives the High potential from the NAND circuit 7 and outputs the second potential to the body terminal 42. At this time, the voltage between the gate and body of the MOSFET becomes 2.5 V, and the drain and source are connected. As a result, the high-frequency signal path is connected.

Next, a state in which the potential supplied to the control terminal 1 is switched from a high potential to a low potential will be described.
When the potential supplied to the control terminal 1 is switched from the High potential to the Low potential, the inverted High potential is supplied from the output terminal of the first NOT circuit 31.
The output terminal side of the NAND circuit 7 maintains a high potential until the output terminal side of the NOR circuit 6 becomes a low potential. That is, the NAND circuit 7 is temporarily supplied with the Low potential from the second input terminal even if the High potential of the output terminal of the first NOT circuit 31 is supplied from the first input terminal. A high potential continues to be output from the output terminal of the circuit 7. On the other hand, the NOR circuit 6 is supplied with a low potential from the second input terminal and is supplied with a high potential from the output terminal of the first NOT circuit 31 from the first input terminal. 6 outputs a low potential, and the node n5 has a low potential. Thereafter, the NAND circuit 7 is supplied with a high potential from the second input terminal, so that the output terminal of the NAND circuit 7 outputs a low potential, and the node n6 also has a low potential.
In this way, since the node n5 is first set to the low potential and then the node n6 is switched to the low potential, the voltage between the gate and the body of the MOSFET 8 is kept in a range not exceeding the withstand voltage as in the high-frequency switch circuit of FIG. Be drunk.

Next, a state in which the potential supplied to the control terminal 1 is switched from the low potential to the high potential will be described.
When the potential supplied to the control terminal 1 is switched from the Low potential to the High potential, the inverted Low potential is supplied from the output terminal of the first NOT circuit 31.
The output terminal side of the NOR circuit 6 maintains a low potential until the output terminal side of the NAND circuit 7 becomes a high potential. That is, the NAND circuit 7 is supplied with the Low potential supplied from the output terminal of the first NOT circuit 31 from the first input terminal, so that the High potential is first output from the output terminal.
On the other hand, the NOR circuit 6 is supplied with the Low potential inverted by the first NOT circuit 31 from the first input terminal. At this time, the High potential is temporarily supplied from the second input terminal. Therefore, the output terminal side also remains at the low potential.
After that, the High potential supplied from the output terminal of the NAND circuit 7 is inverted by the third NOT circuit 33 and supplied to the second input terminal of the NOR circuit 6 as the Low potential 0V. The first and second input terminals are supplied with a low potential of 0 V, and receive this to output a high potential from the output terminal.
In this way, the node n6 is first set to the high potential, and then the node n5 is switched to the high potential, so that the voltage between the gate and the body of the MOSFET is always kept within a range that does not exceed the breakdown voltage.
As the NOT circuit, a known inverter circuit can be used.

Between the fifth node n5 and the second NOT circuit 32, between the second NOT circuit 32 and the other input terminal of the NAND circuit 7, or between the sixth node n6 and the third node A delay means (not shown) may be arranged between the NOT circuits 33 or at least one of the third NOT circuit 33 and the other input terminal of the NOR circuit 6.
For example, by arranging the first delay means between the fifth node n5 and the second NOT circuit 32, or between the second NOT circuit 32 and the other input terminal of the NAND circuit 7, FIG. Similarly to the description in the circuit, when the potential of the control terminal 1 is changed from the high potential to the low potential, the potential on the gate side can be lowered at an earlier timing than the potential on the body side. This ensures that the voltage between the gate and body of the MOSFET 8 does not exceed the breakdown voltage.
Further, by arranging the second delay means between the sixth node n6 and the third NOT circuit 33 or between the third NOT circuit 33 and the other input terminal of the NOR circuit 6, FIG. Similarly to the description in the circuit, when the potential of the control terminal changes from the low potential to the high potential, the body side potential can be raised at a timing earlier than the gate side potential. This ensures that the voltage between the gate and body of the MOSFET 8 does not exceed the breakdown voltage.
By arranging both the first delay means and the second delay means, the voltage between the gate and the body of the MOSFET 8 has a withstand voltage even if the magnitude relationship between the delay times of the level shift circuit 11 and the level shift circuit 12 is unknown. It is possible to make the structure easy to avoid exceeding.

(Example 5)
5 is different from the block diagram of FIG. 4 in that the level shift circuits 11 to 14 are included in the timing control circuit 201e, and the level is between the timing control circuit 201e and the gate terminal 41 and the body terminal 42. The difference is that a shift circuit is unnecessary. Also, the elements and circuits having the same reference numerals as those in FIG.
The timing control circuit 201e will be described.
The timing control circuit 201 e includes a NOR circuit 6, a NAND circuit 7, first to third NOT circuits 31 to 33, and first to fourth level shift circuits 11 to 14, and includes the first NOT circuit 31. An input terminal is connected to the control terminal, an output terminal of the first NOT circuit 31 is connected to one input terminal of the NOR circuit 6 and one input terminal of the NAND circuit 7,
The output terminal of the NOR circuit 6 and the other input terminal of the NAND circuit 7 are connected, and the first and third level shift circuits 11 and 13 are arranged in the connected path,
The output terminal of the NAND circuit 7 and the other input terminal of the NOR circuit 6 are connected, and the second and fourth level shift circuits 12 and 14 are arranged in the connected path.
A seventh node n7 between the first and third level shift circuits 11 and 13 is connected to the gate terminal 41, and an eighth node between the second and fourth level shift circuits 12 and 14 is connected. n8 is connected to the body terminal 42;
The second NOT circuit 32 is disposed between the seventh node n7 and the third level shift circuit 13, or between the third level shift circuit 13 and the other input terminal of the NAND circuit 7, The third NOT circuit 33 is arranged between the eighth node n8 and the fourth level shift circuit 14, or between the fourth level shift circuit 14 and the other input terminal of the NOR circuit 6. .
In the circuit shown in FIG. 5, the second NOT circuit 32 is arranged between the third level shift circuit 13 and the other input terminal of the NAND circuit 7, and the fourth level shift circuit 14 The third NOT circuit 33 is arranged between the other input terminals of the NOR circuit 6.

The operation of the high frequency switch circuit of FIG. 5 will be described.
The timing control circuit 201e can change the switching timing of the high potential and the low potential at the node n7 and the node n8 by the operation of the NOR circuit 6 and the NAND circuit 7, and this technical operation is illustrated in FIG. The description is omitted because it is the same as the high frequency circuit 4.
In the high-frequency switch circuit of FIG. 5, the potential of the node n7 is switched between the first potential and the third potential by the level shift circuit 11 disposed inside the timing control circuit 201e, and the potential of the node n8 is switched by the level shift circuit 12. Are switched between the second and third potentials. Further, the potential switched by the level shift circuit 11 or further inverted by the second NOT circuit 32 becomes the same potential as the High potential and Low potential supplied to the control terminal again by the level shift circuit 13. The potential is supplied from the second input terminal of the NAND circuit 7. Similarly, the potential switched by the level shift circuit 12 or the potential inverted by the third NOT circuit 33 is the same as the High potential and the Low potential supplied again to the control terminal by the level shift circuit 14. The potential is switched to and supplied from the second input terminal of the NOR circuit 6.
Thereafter, as in FIG. 4, the voltage between the gate and the body of the MOSFET is always kept in a range that does not exceed the withstand voltage by the action of the timing control circuit 201 e.

A composite high-frequency switch circuit can be formed using the above-described high-frequency switch circuit.
FIG. 10 shows an example of a composite high frequency switch circuit. The detailed structure of the high-frequency switch circuit will be omitted.
In this composite high-frequency switch circuit, the first high-frequency switch circuit 100 (1) is arranged in a high-frequency signal path that connects the first signal terminal 2 and the second signal terminal 3. The high-frequency switch circuit 100 (1) may be any of the high-frequency switch circuits shown in FIGS.
The node n10 between the first signal terminal and the high frequency switch circuit 100 (1) is grounded, and the second high frequency switch circuit 100 (2) is disposed between the node n10 and the ground. The control terminals 1-1 and 1-2 of the first and second high-frequency switch circuits are connected to the common control terminal 9, respectively, and one is connected to the common control terminal via the NOT circuit 30.
The high frequency switch circuit 100 (2) connected via the NOT circuit by the potential applied from the common control terminal 9 is connected to the other high frequency switch circuits 100 (1) by connecting / disconnecting each high frequency signal path. Switch so that the non-connection is reversed.

A single-pole multi-throw high-frequency switch circuit can be formed using the above-described high-frequency switch circuit.
FIG. 11 shows an example of a single-pole multi-throw high-frequency switch circuit. The detailed structure of the high-frequency switch circuit will be omitted.
The circuit of FIG. 11 includes a common terminal 50 and a plurality of branch terminals 51 (1) to 51 (n) connected via a high-frequency signal path branched from the common terminal. High-frequency switch circuits 100 (1) to 100 (n) are arranged in each of the branched high-frequency signal paths. The connection / disconnection of each high frequency switch circuit is controlled by a control means (not shown) connected to the control terminal of each high frequency switch circuit, and each high frequency switch arranged other than the high frequency signal path connected to the common terminal 50. The circuit is held in a disconnected state.

1: control terminal,
2: First signal terminal,
3: Second signal terminal,
4: AND circuit,
5: OR circuit,
6: NOR circuit,
7: NAND circuit,
8: MOSFET,
9: Common control terminal,
11-14: First to fourth level shift circuits,
31-33: 1st-3rd NOT circuit,
41: Gate terminal,
42: body terminal,
50: Common signal terminals 100, 100a to 100e: High-frequency switch circuit,
200, 200a to 200e: control circuit,
201, 201a to 201e: timing control circuit,
n1 to n8, n10: nodes,
Tr1 to Tr10: MOSFET,

Claims (13)

A high-frequency switch circuit comprising a MOSFET arranged in a high-frequency signal path and a control circuit capable of controlling the potential of the gate and body of the MOSFET,
The control circuit includes a timing control circuit,
The timing control circuit is capable of switching the body potential after switching the gate potential of the MOSFET when the high-frequency signal path is switched from the connected state to the disconnected state, and connected from the disconnected state. A high-frequency switch circuit characterized in that, when switching to a state, the gate potential can be switched after the body potential of the MOSFET is switched. The high-frequency switch circuit according to claim 1,
The control circuit can switch the potential of the gate to the first potential or the third potential, and can switch the potential of the body to the second potential or the third potential.
The high-frequency switch circuit, wherein the second potential is set lower than the first potential, and the third potential is set lower than the second potential. A high-frequency switch circuit according to claim 2,
A high-frequency switch circuit, wherein a potential difference between the first potential and the third potential is larger than a breakdown voltage between a gate and a body of the MOSFET. A high-frequency switch circuit according to any one of claims 1 to 3,
The control circuit includes a control terminal to which a high potential and a low potential are applied, a timing control circuit connected to the control terminal, a gate terminal connected to the gate of the MOSFET, and a body terminal connected to the body. With
The timing control circuit includes an AND circuit and an OR circuit, one input terminal of the AND circuit and one input terminal of the OR circuit are connected to the control terminal, and an output terminal of the AND circuit is the OR circuit. Connected to the other input terminal of the circuit, the output terminal of the OR circuit is connected to the other input terminal of the AND circuit,
A first node between the output terminal of the AND circuit and the other input terminal of the OR circuit is connected to the gate terminal, and between the output terminal of the OR circuit and the other input terminal of the AND circuit. A high frequency switch circuit, wherein a second node is connected to the body terminal. The high-frequency switch circuit according to claim 4,
A high frequency circuit comprising: a first level shift circuit disposed between the first node and the gate terminal; and a second level shift circuit disposed between the second node and the body terminal. Switch circuit. In the high frequency switch circuit according to claim 4 or 5,
The timing control circuit is characterized in that delay means is arranged between at least one of a first node and the other input terminal of the OR circuit and between a second node and the other input terminal of the AND circuit. High frequency switch circuit. A high-frequency switch circuit according to any one of claims 1 to 3,
The control circuit includes a control terminal to which a high potential and a low potential are applied, a timing control circuit connected to the control terminal, a gate terminal connected to the gate of the MOSFET, and a body terminal connected to the body. With
The timing control circuit includes an AND circuit, an OR circuit, and first to fourth level shift circuits, and one input terminal of the AND circuit and one input terminal of the OR circuit are connected to the control terminal. The output terminal of the AND circuit and the other input terminal of the OR circuit are connected, and the first and third level shift circuits are arranged in the connected path, and the output terminal of the OR circuit The other input terminal of the AND circuit is connected, and the second and fourth level shift circuits are arranged in the connected path,
A third node between the first and third level shift circuits is connected to a gate terminal connected to the gate of the MOSFET;
A high-frequency switch circuit, wherein a fourth node between the second and fourth level shift circuits is connected to a body terminal connected to the body of the MOSFET. A high-frequency switch circuit according to any one of claims 1 to 3,
The control circuit includes a control terminal to which a high potential and a low potential are applied, a timing control circuit connected to the control terminal, a gate terminal connected to the gate of the MOSFET, and a body terminal connected to the body. With
The timing control circuit includes a NOR circuit, a NAND circuit, and first to third NOT circuits, an input terminal of the first NOT circuit is connected to the control terminal, and an output terminal of the first NOT circuit Are connected to one input terminal of the NOR circuit and one input terminal of the NAND circuit,
The output terminal of the NOR circuit and the other input terminal of the NAND circuit are connected, and a second NOT circuit is arranged in the connected path,
An output terminal of the NAND circuit and the other input terminal of the NOR circuit are connected, and a third NOT circuit is arranged in the connected path,
A fifth node between the output terminal of the NOR circuit and the second NOT circuit is connected to the gate terminal, and a sixth node between the output terminal of the NAND circuit and the third NOT circuit Is connected to the body terminal. The high-frequency switch circuit according to claim 8,
A high frequency circuit comprising: a first level shift circuit disposed between the fifth node and the gate terminal; and a second level shift circuit disposed between the sixth node and the body terminal. Switch circuit. The high-frequency switch circuit according to claim 8 or 9, wherein
Between the fifth node and the second NOT circuit, between the second NOT circuit and the other input terminal of the NAND circuit, or between the sixth node and the third NOT circuit, or A high-frequency switch circuit, characterized in that a delay means is disposed at least one between the third NOT circuit and the other input terminal of the NOR circuit. A high-frequency switch circuit according to any one of claims 1 to 3,
The control circuit includes a control terminal to which a high potential and a low potential are applied, a timing control circuit connected to the control terminal, a gate terminal connected to the gate of the MOSFET, and a body terminal connected to the body. With
The timing control circuit includes a NOR circuit, a NAND circuit, first to third NOT circuits, and first to fourth level shift circuits, and an input terminal of the first NOT circuit is connected to the control terminal. The output terminal of the first NOT circuit is connected to one input terminal of the NOR circuit and one input terminal of the NAND circuit, respectively.
The output terminal of the NOR circuit and the other input terminal of the NAND circuit are connected, and first and third level shift circuits are arranged in the connected path,
An output terminal of the NAND circuit and the other input terminal of the NOR circuit are connected, and second and fourth level shift circuits are arranged in the connected path, and the first and third level shift circuits A seventh node between is connected to the gate terminal, an eighth node between the second and fourth level shift circuits is connected to the body terminal,
The second NOT circuit is arranged between the seventh node and the third level shift circuit, or between the third level shift circuit and the other input terminal of the NAND circuit, and A high frequency switch, wherein the third NOT circuit is arranged between a node and the fourth level shift circuit, or between the fourth level shift circuit and the other input terminal of the NOR circuit. circuit. 12. A composite high-frequency switch circuit using a plurality of high-frequency switch circuits according to claim 1, wherein control terminals of the plurality of high-frequency switch circuits are respectively connected to a common control terminal, and at least one of the The control terminal of the high frequency switch circuit is connected to the common control terminal via a NOT circuit,
The high-frequency switch circuit connected to the common control terminal via the NOT circuit by the potential applied from the common control terminal connects / disconnects each high-frequency signal path to the other high-frequency switch circuits. A composite high-frequency switch circuit characterized in that the connection is switched so as to be reversed. A composite high-frequency switch circuit using a plurality of high-frequency switch circuits according to any one of claims 1 to 11,
A single-pole multi-throw switch circuit having a common terminal and a plurality of branch terminals connected via a high-frequency signal path branched from the common terminal;
A composite high-frequency switch circuit, wherein the high-frequency switch circuit is disposed in each of the branched high-frequency signal paths.

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