JP5061168B2 - 電子機器の製造方法 - Google Patents
電子機器の製造方法 Download PDFInfo
- Publication number
- JP5061168B2 JP5061168B2 JP2009215153A JP2009215153A JP5061168B2 JP 5061168 B2 JP5061168 B2 JP 5061168B2 JP 2009215153 A JP2009215153 A JP 2009215153A JP 2009215153 A JP2009215153 A JP 2009215153A JP 5061168 B2 JP5061168 B2 JP 5061168B2
- Authority
- JP
- Japan
- Prior art keywords
- solder
- layer
- alloy
- lead
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/858—Bonding techniques
- H01L2224/85801—Soldering or alloying
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
界面の様子を調べた。また、引っ張り試験を行った試料の剥離面をSEMで観察した。この代表的な組み合わせについての結果を説明する。
Claims (1)
- 基板と、表面層となるSn−(1〜20)重量%(ただし、4重量%以上15重量%以下の範囲を除く)Bi系層をFe−Ni系リード上にCu層を介して形成した半導体装置とを、鉛フリーはんだ材料を用いてはんだ接続することを特徴とする電子機器の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009215153A JP5061168B2 (ja) | 2009-09-17 | 2009-09-17 | 電子機器の製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009215153A JP5061168B2 (ja) | 2009-09-17 | 2009-09-17 | 電子機器の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007278307A Division JP4535464B2 (ja) | 2007-10-26 | 2007-10-26 | 電子機器の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009302568A JP2009302568A (ja) | 2009-12-24 |
JP5061168B2 true JP5061168B2 (ja) | 2012-10-31 |
Family
ID=41549070
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009215153A Expired - Lifetime JP5061168B2 (ja) | 2009-09-17 | 2009-09-17 | 電子機器の製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5061168B2 (ja) |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3040929B2 (ja) * | 1995-02-06 | 2000-05-15 | 松下電器産業株式会社 | はんだ材料 |
JPH1093004A (ja) * | 1996-09-11 | 1998-04-10 | Matsushita Electron Corp | 電子部品およびその製造方法 |
JPH10229152A (ja) * | 1996-12-10 | 1998-08-25 | Furukawa Electric Co Ltd:The | 電子部品用リード材、それを用いたリードおよび半導体装置 |
JP3243195B2 (ja) * | 1997-01-28 | 2002-01-07 | 古河電気工業株式会社 | リフロー半田めっき材およびその製造方法 |
JP3551167B2 (ja) * | 2001-08-23 | 2004-08-04 | 株式会社日立製作所 | 半導体装置 |
JP4535429B2 (ja) * | 2004-05-28 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
-
2009
- 2009-09-17 JP JP2009215153A patent/JP5061168B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2009302568A (ja) | 2009-12-24 |
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