JP5051409B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- JP5051409B2 JP5051409B2 JP2005152125A JP2005152125A JP5051409B2 JP 5051409 B2 JP5051409 B2 JP 5051409B2 JP 2005152125 A JP2005152125 A JP 2005152125A JP 2005152125 A JP2005152125 A JP 2005152125A JP 5051409 B2 JP5051409 B2 JP 5051409B2
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- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 64
- 239000002184 metal Substances 0.000 claims description 63
- 238000000034 method Methods 0.000 claims description 21
- 238000010438 heat treatment Methods 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 230000003014 reinforcing effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 description 82
- 230000035882 stress Effects 0.000 description 49
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 23
- 230000008569 process Effects 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 230000000087 stabilizing effect Effects 0.000 description 6
- 230000008646 thermal stress Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 4
- 238000002844 melting Methods 0.000 description 4
- 230000008018 melting Effects 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000035515 penetration Effects 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- 239000004215 Carbon black (E152) Substances 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011819 refractory material Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
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- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
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- H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
- H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/314—Inorganic layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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Description
本発明は、半導体素子の製造方法に係り、特に、MLM(MetalLayerMetal)工程の際に絶縁膜に発生するクラック(crack)の抑制に適した半導体素子の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for suppressing cracks generated in an insulating film during an MLM (Metal Layer Metal) process.
半導体素子のMLM(MetalLayerMetal)形成方法は、アルミニウム(Al)やタングステン(W)などのメタルライン(MetalLine)を形成した後、高密度プラズマ(HighDensityPlasma)のようなシリコン酸化膜を用いて金属配線間の絶縁を行う。 The MLM (MetalLayerMetal) formation method of semiconductor elements is a method of forming metal lines such as aluminum (Al) and tungsten (W) and then using a silicon oxide film such as high-density plasma (HighDensityPlasma). Insulate.
このようなメタル工程の完了後、リフレッシュ(refresh)特性の改善およびメタル抵抗の安定化のためのアニール(anneal)を行わなければならない。 After the metal process is completed, an annealing process for improving refresh characteristics and stabilizing the metal resistance must be performed.
一般に、金属の場合、絶縁膜に比べて熱膨張速度が数十倍以上なので、熱処理の際にメタルと酸化膜間の熱膨張度の差異による熱応力の発生は不可避であり、このような熱応力は絶縁膜の脆弱地点でクラック(crack)を誘発する。 In general, in the case of metal, the thermal expansion rate is several tens or more times higher than that of an insulating film. Therefore, it is inevitable that thermal stress is generated due to the difference in thermal expansion between the metal and the oxide film during heat treatment. The stress induces a crack at the weak point of the insulating film.
図1は熱応力により絶縁膜に生じたクラックを撮影したSEM写真であって、熱応力により発生した1次絶縁膜のクラックと1次クラックによる陥没で形成された2次クラックとが示されている。 FIG. 1 is a SEM photograph of a crack generated in an insulating film due to thermal stress, showing a crack in the primary insulating film generated by the thermal stress and a secondary crack formed by the depression due to the primary crack. Yes.
また、アニール(anneal)工程は、一般に400〜450℃の温度で20〜30分間行うが、このようなアニール条件は、アルミニウム配線を使用する場合、アルミニウムの溶融温度が600℃であって2/3Tm程度の高温なので、液体挙動を誘発する。したがって、アニール工程中に配線用アルミニウムが液体挙動を示す。 The annealing process is generally performed at a temperature of 400 to 450 ° C. for 20 to 30 minutes. Such an annealing condition is that when aluminum wiring is used, the melting temperature of aluminum is 600 ° C. High temperature of about 3 Tm induces liquid behavior. Therefore, the wiring aluminum exhibits a liquid behavior during the annealing process.
この際、熱応力によるクラックが存在する場合、毛細管現象およびAl体積膨張により前記クラックにAlが浸透してメタルラインブリッジフェール(metallinebridgefail)が発生する。 At this time, if there is a crack due to thermal stress, Al penetrates into the crack due to capillary phenomenon and Al volume expansion, and a metalline bridge failure occurs.
図2はメタルラインブリッジフェールを撮影したSEM写真であって、クラックに金属(Al)が浸透してA部分でのように金属が下部導電層に連結される不良が発生することを示している。 FIG. 2 is an SEM photograph of a metal line bridge failure, showing that metal (Al) penetrates into the crack and a defect occurs in which the metal is connected to the lower conductive layer as in the A portion. .
メタルと絶縁膜が存在する場合、熱処理の際にメタルと絶縁膜間の熱膨張度の差異による熱応力の発生は不可避であり、この際、絶縁膜が受ける応力程度は−3.5E11dyn/cm2程度の圧縮応力が発生する。特に、メタルラインの角部地域では、応力集中が発生し、一般に取り扱う薄膜ストレスレベル(thinfilmstresslevel)である〜1E9dyn/cm2の数百倍の応力が発生する。 In the case where a metal and an insulating film are present, the generation of thermal stress due to the difference in thermal expansion between the metal and the insulating film is unavoidable during the heat treatment. At this time, the degree of stress received by the insulating film is −3.5E11 dyn / cm. A compressive stress of about 2 is generated. In particular, stress concentration occurs in the corner area of the metal line, and stress that is several hundred times as large as a generally handled thin film stress level of ˜1E9 dyn / cm 2 is generated.
メタルによって絶縁膜が受ける応力(σox)は次の数式1のとおりである。 The stress (σ ox ) applied to the insulating film by the metal is as shown in the following formula 1.
ここで、σoxはメタルによって絶縁膜が受ける応力、EAIはAlの弾性係数(=6E11dyn/cm2)、VAIはAlのポイソン比(poission's ratio)(=0.3)、αAIはAlの熱膨張度(=10ppm/k)、aoxは絶縁膜の熱膨張度(=0.55ppm/k)、dTは常温と熱処理時の温度との差(=425K)である。 Here, σ ox is the stress applied to the insulating film by the metal, E AI is the elastic modulus of Al (= 6E11 dyn / cm 2 ), V AI is the Poission's ratio of Al (= 0.3), α AI is the thermal expansion degree of Al (= 10 ppm / k), a ox is the thermal expansion degree of the insulating film (= 0.55 ppm / k), and dT is the difference between the normal temperature and the temperature during heat treatment (= 425 K).
図3(a)および図3(b)はそれぞれ温度によるAlとHDP酸化膜の応力履歴曲線を示したグラフである。 FIG. 3A and FIG. 3B are graphs showing stress history curves of Al and HDP oxide films according to temperature, respectively.
図3(a)を参照すると、アルミニウムは、初期には引張応力を持つが、温度の増加に伴って熱膨張度が大きくなるため、圧縮応力に変化した後、冷却の際にさらに引張応力に変化することを確認することができる。 Referring to FIG. 3 (a), aluminum initially has a tensile stress, but the thermal expansion increases as the temperature increases. Therefore, after changing to a compressive stress, aluminum further increases the tensile stress during cooling. It can be confirmed that it changes.
しかし、HDP酸化膜の場合、初期状態では圧縮応力を持つが、温度の増加に伴って引張応力の方向に変化するが、依然として圧縮応力を示し、冷却の際にさらに圧縮応力が増加する。 However, although the HDP oxide film has a compressive stress in the initial state, it changes in the direction of the tensile stress as the temperature increases, but still shows the compressive stress, and the compressive stress further increases during cooling.
図4(a)〜図4(c)は図3(a)および図3(b)の応力履歴曲線の結果に基づいて熱処理の際にAlとHDP酸化膜にそれぞれ発生する応力の状態を図式的に示した図である。 4 (a) to 4 (c) are graphs showing the states of stresses respectively generated in the Al and HDP oxide films during heat treatment based on the results of the stress history curves of FIGS. 3 (a) and 3 (b). FIG.
ここで、矢印方向は膜が変化したがる方向を示し、矢印の長さは応力の大きさを示す。 Here, the arrow direction indicates the direction in which the film wants to change, and the length of the arrow indicates the magnitude of the stress.
加熱前(図4(a))と冷却後(図4(c))の状態では、Alは引張応力、HDP酸化膜は圧縮応力により、応力方向が逆に作用して応力緩和効果をもたらす可能性がある。 In the state before heating (FIG. 4 (a)) and after cooling (FIG. 4 (c)), Al is tensile stress, HDP oxide film is compressive stress, and the stress direction can be reversed to bring about stress relaxation effect. There is sex.
ところが、加熱の際(図4(b))にはAlの応力が圧縮応力に変わるので、AlとHDP酸化膜の両方とも圧縮応力を示して非常に高い応力が発生する。 However, during heating (FIG. 4B), since the stress of Al changes to compressive stress, both Al and the HDP oxide film exhibit compressive stress and generate very high stress.
したがって、図4(b)のB部分に示すように、メタルラインボタムコーナー(metallinebottomcorner)地域における応力集中をもたらす。 Accordingly, as shown in part B of FIG. 4 (b), stress concentration occurs in the metallinebottomcorner area.
Alボトムコーナー地域は、メタルライン形成の際にメタルラインブリッジの除去のために50%程度のオーバーエッチ(overetch)を行うが、このときにオーバーエッチによる下部TEOS酸化膜の損失(loss)が発生する地域である。 In the Al bottom corner area, overetching of about 50% is performed to remove the metal line bridge when forming the metal line. At this time, loss of the lower TEOS oxide film due to overetching occurs. It is an area to do.
図5はAlエッチングプロファイルを示す図である。図5より、オーバーエッチによってボトムコーナー地域のTEOS酸化膜が損失したことを確認することができる。 FIG. 5 shows an Al etching profile. From FIG. 5, it can be confirmed that the TEOS oxide film in the bottom corner region has been lost due to overetching.
このようなAlボトム地域は、応力集中とともに異種膜の界面(TEOS/HDP)で形成されるので、亀裂に非常に脆弱な構造である。 Such an Al bottom region is formed at the interface between different kinds of films (TEOS / HDP) together with stress concentration, and is therefore very vulnerable to cracks.
図6はオーバーエッチ地域の亀裂と亀裂によるAl浸透現象を示したSEM写真であって、Alボトム地域が亀裂に脆弱であり、それによるAl浸透の問題があることを示している。 FIG. 6 is an SEM photograph showing the Al penetration phenomenon due to cracks and cracks in the over-etched region, and shows that the Al bottom region is vulnerable to cracks and thus has a problem of Al penetration.
さらに、TEOS酸化膜は、表面に水分および炭化水素(hydro-carbon)不純物などが多量含有された膜なので、その界面が非常に不安定であって問題の素子を常に内包している。 Furthermore, since the TEOS oxide film is a film containing a large amount of moisture, hydrocarbon (hydro-carbon) impurities, and the like on its surface, its interface is very unstable and always contains the device in question.
図7はSIMSを用いてTEOS酸化膜の表面の不純物を測定した結果を示すグラフである。図7よりは、TEOS酸化膜の表面にH2、CxHy、H2O、CO、O2、CO2などの不純物が多量含有されていることを確認することができ、これによる界面不安定性を予測することができる。 FIG. 7 is a graph showing the results of measuring impurities on the surface of the TEOS oxide film using SIMS. From FIG. 7, it can be confirmed that the surface of the TEOS oxide film contains a large amount of impurities such as H 2 , C x H y , H 2 O, CO, O 2 , CO 2. Instability can be predicted.
図8はTEOS/TEOS界面のアタック程度を示す図である。TEOS酸化膜の蒸着後、真空破壊(vaccumbreak)のみを行ってからさらに酸化膜を蒸着し、ウェットクリーニング(wetcleaning)のみを行っても、TEOS/TEOS界面におけるエッチング率が高くてアタック(attack)が発生する。よって、TEOS/HDP界面結合力が非常に良くないものと推定することができる。 FIG. 8 is a diagram showing the degree of attack at the TEOS / TEOS interface. Even after the deposition of the TEOS oxide film, only the vacuum break (vaccumbreak) is performed, and then the oxide film is further deposited and only wet cleaning is performed, so that the etching rate at the TEOS / TEOS interface is high and the attack is high. appear. Therefore, it can be estimated that the TEOS / HDP interface binding force is not very good.
したがって、前述した原因により、メタルラインオーバーエッチ地域であるTEOS/HDP界面におけるクラックが始まってクラックによるAlブリッジフェールが発生する。 Therefore, due to the above-described causes, cracks at the TEOS / HDP interface, which is a metal line overetch region, start and an Al bridge failure due to the cracks occurs.
そこで、本発明の目的は、高温で膜の応力状態を変化させ、あるいはこのような応力が加わったときにクラック(crack)の発生が抑制されるようにメタルラインボトムコーナーのような亀裂脆弱部位の界面特性を改善させ、あるいはクラックの原因となる異種界面を除去することにより、半導体素子におけるクラック発生を防止することができ、ひいてはクラックによるメタルラインブリッジフェールを防止することができる、半導体素子の製造方法を提供することにある。 Therefore, an object of the present invention is to change the stress state of the film at a high temperature, or to generate a crack vulnerable part such as a metal line bottom corner so that the occurrence of cracks is suppressed when such stress is applied. By improving the interfacial characteristics of the semiconductor element or by removing the heterogeneous interface that causes cracks, it is possible to prevent the occurrence of cracks in the semiconductor element, and thus to prevent metal line bridge failure due to cracks. It is to provide a manufacturing method.
上記の目的を達成するために、本発明の一特徴に係る半導体素子の製造方法は、(a)第1絶縁膜の形成された基板上にメタルラインを形成するが、前記メタルラインはAl金属膜にAl 2 O 3 およびWが含まれるように形成する段階と、(b)前記メタルラインをパターニングする段階と、(c)前記メタルライン上に第2絶縁膜を形成する段階と、(d)熱処理工程を行う段階とを含んでなることを特徴とする。
In order to achieve the above object, a method of manufacturing a semiconductor device according to one aspect of the present invention includes: (a) forming a metal line on a substrate on which a first insulating film is formed; Forming the film so as to contain Al 2 O 3 and W , (b) patterning the metal line, (c) forming a second insulating film on the metal line, and (d) And a step of performing a heat treatment step.
本発明は、メタルラインまたはHDP酸化膜の圧縮応力を減少させることができるので、後続のメタルライン熱処理工程の際に圧縮応力を減らすことができる。したがって、圧縮応力に起因するクラックの発生を減らすことができる。また、クラックの原因となる異種界面を除去することにより、半導体素子におけるクラック発生を防止することができる。さらに、不安定であったTEOS酸化膜の界面を安定化させることにより、半導体素子のクラック発生を防止することができる。 Since the present invention can reduce the compressive stress of the metal line or HDP oxide film, the compressive stress can be reduced during the subsequent metal line heat treatment process. Therefore, the occurrence of cracks due to compressive stress can be reduced. Further, by removing the heterogeneous interface that causes the crack, the occurrence of cracks in the semiconductor element can be prevented. Further, by stabilizing the unstable interface of the TEOS oxide film, the occurrence of cracks in the semiconductor element can be prevented.
次に、本発明を説明するに先立ち、本発明と関連した一般的な半導体素子の製造工程を説明する。 Next, prior to describing the present invention, a general process for manufacturing a semiconductor device related to the present invention will be described.
図9(a)〜図9(d)は本発明と関連した一般的な半導体素子の製造工程を示す断面図である。 FIG. 9A to FIG. 9D are cross-sectional views showing a general semiconductor device manufacturing process related to the present invention.
まず、図9(a)に示すように、第1絶縁膜101の形成された基板上に金属膜102を形成する。前記金属膜102はアルミニウム(Al)を蒸着して形成する。 First, as shown in FIG. 9A, a metal film 102 is formed on a substrate on which the first insulating film 101 is formed. The metal film 102 is formed by depositing aluminum (Al).
その後、図9(b)に示すように、前記金属膜102をパターニングしてメタルライン102aを形成する。この際、前記メタルライン102aのボトムコーナー(bottomcorner)地域は、メタルライン間のブリッジを防止するために50%程度のオーバーエッチを行うが、オーバーエッチによって下部の第1絶縁膜101が一部損失する。 Thereafter, as shown in FIG. 9B, the metal film 102 is patterned to form a metal line 102a. At this time, in the bottom corner area of the metal line 102a, overetching of about 50% is performed to prevent a bridge between the metal lines, but the first insulating film 101 below is partially lost due to overetching. To do.
次いで、図9(c)に示すように、全面に第2絶縁膜103を形成する。その後、リフレッシュ特性およびメタル抵抗の安定化のために、図9(d)に示すように450℃の温度で熱処理する。この際、前記第2絶縁膜103とメタルライン102aが全て圧縮応力を示し、メタルラインボトムコーナーにおける応力集中をもたらしている。 Next, as shown in FIG. 9C, a second insulating film 103 is formed on the entire surface. Thereafter, heat treatment is performed at a temperature of 450 ° C. as shown in FIG. 9D in order to stabilize refresh characteristics and metal resistance. At this time, the second insulating film 103 and the metal line 102a all exhibit compressive stress, which causes stress concentration at the metal line bottom corner.
(第1参考例)
本発明の第1参考例は、前記メタルライン102aを形成した後、第2絶縁膜103を蒸着する前に熱処理工程を行ってメタルライン102aの圧縮応力を減少させようとする。
( First Reference Example )
The first reference example of the present invention attempts to reduce the compressive stress of the metal line 102a by performing a heat treatment process after the metal line 102a is formed and before the second insulating film 103 is deposited.
前記熱処理工程は、炉(Furnace)で300〜450℃の温度範囲のN2およびArガス雰囲気中で20〜60分間行う方法、あるいは300〜550℃の温度範囲のN2ガス雰囲気中で10〜60秒間急速熱処理(RTP)を行う方法を使用する。 The heat treatment step is performed in a furnace at a temperature range of 300 to 450 ° C. in a N 2 and Ar gas atmosphere for 20 to 60 minutes, or in a N 2 gas atmosphere at a temperature range of 300 to 550 ° C. A method of performing rapid thermal processing (RTP) for 60 seconds is used.
前述した熱処理工程によって前記メタルライン102aの圧縮応力を減少させることができ、これによりメタルライン102aのリフレッシュ特性およびメタル抵抗安定化のための後続の熱処理工程(図9(d))における応力集中現象を減らすことができる。 The compressive stress of the metal line 102a can be reduced by the heat treatment process described above, whereby the stress concentration phenomenon in the subsequent heat treatment process (FIG. 9D) for stabilizing the refresh characteristics and metal resistance of the metal line 102a. Can be reduced.
(第1実施例)
本発明の第1実施例は、メタルライン102aの溶融を抑制させてメタルライン102aの応力を変更させようとするもので、前記メタルライン102aを高融点金属成分が含まれるように構成する。
( First embodiment )
The first embodiment of the present invention attempts to change the stress of the metal line 102a by suppressing the melting of the metal line 102a, and the metal line 102a is configured to contain a refractory metal component.
高融点金属成分含有のメタルライン102aを形成する方法としては、金属膜102の形成の際に金属膜102に高融点物質を分散強化処理する方法や、金属膜102の形成の際に金属と高融点物質を同時スパッタリング法を用いて2相を同時に蒸着する方法がある。 As a method of forming the metal line 102 a containing a refractory metal component, a method of dispersing and strengthening a refractory substance in the metal film 102 when forming the metal film 102, There is a method of simultaneously depositing two phases using a simultaneous sputtering method with a melting point material.
例えば、Al金属の内部にAl2O3およびWなどを分散強化処理し、あるいはAlと同時にAl2O3およびWなどの高融点物質を同時スパッタリング法を用いて同時に蒸着する。 For example, Al 2 O 3 and W are dispersed and strengthened in the Al metal, or refractory materials such as Al 2 O 3 and W are simultaneously deposited by simultaneous sputtering using Al.
このように、メタルライン102aを高融点金属成分が含まれるように形成すると、メタルライン102aの溶融を抑制させることができ、これによりメタルライン102aのリフレッシュ特性およびメタル抵抗安定化のための後続の熱処理工程(図9(d))で応力集中現象を減らすことができる。 As described above, when the metal line 102a is formed so as to include the refractory metal component, the melting of the metal line 102a can be suppressed, and thereby, the subsequent refresh for stabilizing the metal line 102a and stabilizing the metal resistance can be achieved. The stress concentration phenomenon can be reduced in the heat treatment step (FIG. 9D).
(第2実施例)
本発明の第2実施例では、第2絶縁膜103の蒸着の際にバイアスパワーを3000〜6000Wattにして第2絶縁膜103の圧縮応力を減少させようとする。
( Second embodiment )
In the second embodiment of the present invention, when the second insulating film 103 is deposited, the bias power is set to 3000 to 6000 Watt to reduce the compressive stress of the second insulating film 103.
絶縁膜の蒸着の際にバイアスパワーが増加すると、絶縁膜の圧縮応力は減少するものと知られている。本発明の第2絶縁膜103の蒸着の際にバイアスパワーを十分高く設定して第2絶縁膜103の圧縮応力を減らそうとする。 It is known that when the bias power increases during the deposition of the insulating film, the compressive stress of the insulating film decreases. The bias power is set sufficiently high during the deposition of the second insulating film 103 of the present invention to reduce the compressive stress of the second insulating film 103.
したがって、第2絶縁膜103の圧縮応力を減少させることができ、これによりメタルライン102aのリフレッシュ特性およびメタル抵抗安定化のための後続の熱処理工程(図9(d))における応力集中現象を減らすことができる。 Therefore, the compressive stress of the second insulating film 103 can be reduced, thereby reducing the stress concentration phenomenon in the subsequent heat treatment process (FIG. 9D) for stabilizing the refresh characteristics and metal resistance of the metal line 102a. be able to.
(第3実施例)
従来の技術で説明したように、第1絶縁膜101と第2絶縁膜103がお互い異なる二種膜の場合、すなわち第1絶縁膜101をTEOS酸化膜、第2絶縁膜103をHDP酸化膜から構成する場合、2膜の界面における界面結合力(adhesive)が悪くてクラックが発生する。
( Third embodiment )
As described in the prior art, when the first insulating film 101 and the second insulating film 103 are two different types of films, that is, the first insulating film 101 is a TEOS oxide film, and the second insulating film 103 is an HDP oxide film. When configured, cracks are generated due to poor adhesion at the interface between the two films.
本発明の第3実施例では、前記第1、第2絶縁膜101、103を同種の物質で形成する。 In the third embodiment of the present invention, the first and second insulating films 101 and 103 are formed of the same material.
例えば、前記第1、第2絶縁膜101、103を全てTEOS酸化膜から構成し、あるいは前記第1、第2絶縁膜101、103を全てHDP酸化膜から構成する。 For example, the first and second insulating films 101 and 103 are all composed of TEOS oxide films, or the first and second insulating films 101 and 103 are all composed of HDP oxide films.
したがって、本発明の第3実施例によれば、第1、第2絶縁膜101、103間の界面結合力が強化されるので、クラックの発生を減らすことができる。 Therefore, according to the third embodiment of the present invention, since the interface bonding force between the first and second insulating films 101 and 103 is strengthened, the occurrence of cracks can be reduced.
(第4実施例)
従来の技術で説明したように、第1絶縁膜101としてTEOS酸化膜を使用する場合、TEOS酸化膜の表面にH2、CxHy、H2O、CO、O2、CO2などの不純物が多量含有されてその界面が非常に不安定である。
( Fourth embodiment )
As described in the prior art, when a TEOS oxide film is used as the first insulating film 101, H 2 , C x H y , H 2 O, CO, O 2 , CO 2, etc. are formed on the surface of the TEOS oxide film. The interface is very unstable because of a large amount of impurities.
本発明の第4実施例では、第1絶縁膜101をTEOS酸化膜で形成した場合、第1絶縁膜101の界面安定化のためにTEOS酸化膜で第1絶縁膜101を形成した後、第1絶縁膜に対すてプラズマ処理する工程を行う。 In the fourth embodiment of the present invention, when the first insulating film 101 is formed of the TEOS oxide film, the first insulating film 101 is formed of the TEOS oxide film to stabilize the interface of the first insulating film 101, and then the first insulating film 101 is formed. A step of performing plasma treatment on one insulating film is performed.
前記プラズマ処理は、Ar、O2、Heの少なくとも一つを含む雰囲気中で2000〜6000Wattのバイアスパワーで10〜100秒(sec)間行う。 The plasma treatment is performed for 10 to 100 seconds (sec) with a bias power of 2000 to 6000 Watt in an atmosphere containing at least one of Ar, O 2 , and He.
101 第1絶縁膜
102 金属膜
102a メタルライン
103 第2絶縁膜
101 first insulating film 102 metal film 102a metal line 103 second insulating film
Claims (3)
(b)前記メタルラインをパターニングする段階と、
(c)前記メタルライン上に第2絶縁膜を形成する段階と、
(d)熱処理工程を行う段階とを含んでなる半導体素子の製造方法。 (A) forming a metal line on the substrate on which the first insulating film is formed, the metal line being formed so that Al 2 O 3 and W are included in the Al metal film ;
(B) patterning the metal line;
(C) forming a second insulating film on the metal line;
(D) A method for manufacturing a semiconductor device, comprising performing a heat treatment step.
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