KR100511916B1 - Method for controlling insulating layer crack of semiconductor device - Google Patents
Method for controlling insulating layer crack of semiconductor device Download PDFInfo
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- KR100511916B1 KR100511916B1 KR10-2003-0031136A KR20030031136A KR100511916B1 KR 100511916 B1 KR100511916 B1 KR 100511916B1 KR 20030031136 A KR20030031136 A KR 20030031136A KR 100511916 B1 KR100511916 B1 KR 100511916B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76828—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
- H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
Abstract
본 발명은 반도체소자의 절연막 크랙 억제방법을 개시한다. 개시된 발명의 방법은, 반도체기판 상에 일정간격을 두고 다수의 금속배선을 형성하는 단계; 상기 금속배선 상에 응력완화막을 형성하는 단계; 상기 응력완화막이 형성된 금속배선에 대해 응력완화 열처리를 진행하는 단계; 및 상기 금속배선 상단 모서리부에서의 균열 발생이 억제되도록 기판 결과물 상에 HDP막을 11,300Å 이상의 두께로 증착하는 단계;를 포함하는 것을 특징으로 한다. The present invention discloses a method for suppressing insulating film cracks in semiconductor devices. The disclosed method includes forming a plurality of metal interconnections on a semiconductor substrate at a predetermined interval; Forming a stress relaxation film on the metal wiring; Performing a stress relaxation heat treatment on the metal wiring on which the stress relaxation film is formed; And depositing an HDP film having a thickness of 11,300 Å or more on the substrate resultant so that cracking at the upper edge portion of the metal wiring is suppressed.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 HDP막의 응력 및 모서리부의 증착두께를 조절하여 크랙(crack)을 억제하는 반도체소자의 절연막 크랙 억제방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an insulating film crack suppression method of a semiconductor device which suppresses cracks by controlling stress and deposition thickness of an edge portion of an HDP film.
현재 다층 금속배선 형성방법은 금속배선(예를들어 Al)을 형성한후 전체 구조의 상면에 절연막으로 SOG 또는 HDP를 사용하고 있다.Currently, the method for forming a multi-layered metal wiring uses SOG or HDP as an insulating film on the upper surface of the entire structure after forming the metal wiring (eg Al).
디램에서의 이와 같은 공정으로는 하부배선 레벨의 층간절연막과 상부배선 레벨의 보호막 형성공정 등이 있다.Such a process in the DRAM includes an interlayer insulating film at the lower wiring level and a protective film forming process at the upper wiring level.
그런데, 열처리시에 금속과 산화막 간의 열팽창도 차이로 인한 열응력 발생은 불가피하다. 특히, 금속의 경우 절연막보다 열팽창도가 수십배 이상이다.However, thermal stress is inevitable due to the difference in thermal expansion between the metal and the oxide film during the heat treatment. In particular, in the case of metal, the thermal expansion degree is several ten times or more than the insulating film.
이 같은 열응력을 절연막의 약한 지점(weak point) 에서의 크랙을 유발하게 된다.This thermal stress causes a crack at the weak point of the insulating film.
또한, 열처리는 일반적으로 430∼450℃ 온도에서 20∼30분 정도를 행하게 되는데, 이 같은 아닐링 조건은 배선용 Al을 사용하는 경우 Al의 용융온도가 660℃이므로 2/3 Tm 정도의 고온이므로 액체거동을 유발하게 된다.In addition, heat treatment is generally performed at a temperature of 430 to 450 ° C. for about 20 to 30 minutes. The annealing condition is a high temperature of about 2/3 Tm because Al has a melting temperature of 660 ° C. when using Al for wiring. It causes behavior.
따라서, 아닐링시에 배선용 Al이 액상거동을 보이게 되는데, 도 1에서와 같이, 이때 발생하는 열응력으로 인한 HDP 크랙을 통한 Al의 브릿지 불량(bridge fail)이 발생하여 수율이 감소된다.Accordingly, the wiring Al exhibits a liquid phase behavior at the time of annealing. As shown in FIG. 1, a bridge failure of Al through the HDP crack due to the thermal stress generated at this time occurs, and thus the yield is reduced.
이러한 HDP 크랙(crack)에 발생하는 원인들에 대해 첨부된 도면을 참조하여 설명하면 다음과 같다.The causes of such HDP cracks will be described with reference to the accompanying drawings.
먼저 금속과 절연막이 존재하는 경우, 열처리시에 열팽창 차이로 인한 열응력 발생은 불가피하며, 이때 HDP가 받는 응력의 정도는 -3.5 E11 dyn/cm2 정도의 압축응력이 발생된다. 특히, 금속배선 모서리 지역에서는 응력집중이 발생하여 일반적으로 다루는 박막 응력 레벨 (∼E9)의 수백배의 응력이 발생하게 된다. 여기서, 금속에 의해 HDP이 받는 응력을 식(1)으로 나타내면 다음과 같다.First, when the metal and the insulating film are present, thermal stress due to the difference in thermal expansion during heat treatment is inevitable, and the compressive stress of about -3.5 E11 dyn / cm2 is generated at the stress of HDP. In particular, stress concentrations occur in the edge area of the metal wiring, which causes several hundred times the stress of the thin film stress level (-E9). Here, when the stress which HDP receives by a metal is represented by Formula (1), it is as follows.
σHDD = [E/(1-v)Al(αHDP - αAl)dT = -3.5 dyn/cm2 - - - - - (1)σ HDD = (E / (1-v) Al (α HDP -α Al ) dT = -3.5 dyn / cm2-----(1)
여기서, σHDD = 금속에 의하여 HDP막이 받는 응력이고, EAl = Al의 탄성계수 6E 11dyn/cm2이며, VAl = Al의 포이즌 비율(poission's ratio) 0.3, αHDP(10ppm/K) 및 αHDP(0.55ppm/K) = Al과 HDP막의 열팽창도이며, dT = 상온과 열처리시의 온도차 425 K이다.Here, σ is the HDD = receiving HDP film stress by a metal, E Al = Al and of the modulus of elasticity 6E 11dyn / cm2, V Al = poison ratio of Al (poission's ratio) 0.3, α HDP (10ppm / K) , and α HDP (0.55 ppm / K) = thermal expansion of Al and HDP film, dT = temperature difference of 425 K at normal temperature and heat treatment.
한편, 온도에 따른 Al, HDP, 질화막의 응력 히스테리시스(stress hysteresis)를 도 2a 내지 도 2c를 참조하여 설명하면 다음과 같다.Meanwhile, stress hysteresis of Al, HDP, and nitride films according to temperature will be described with reference to FIGS. 2A to 2C.
Al 박막의 경우, 도 2a에 도시된 바와같이, 증착상태에서는 인장응력이지만, 온도가 증가됨에 따라 열팽창도가 크기 때문에 압축응력을 보이다가 냉각시에 다시 인장응력으로 변화된다.In the case of the Al thin film, as shown in FIG. 2A, the tensile stress in the deposition state, but due to the large thermal expansion as the temperature is increased, the compressive stress is shown and then changed to the tensile stress upon cooling.
또한, HDP 박막의 경우, 도 2b에 도시된 바와같이, 증착상태에서는 압축응력이며, 온도가 증가됨에 따라 인장응력 방향으로 변화되나, 여전히 압축응력을 나타낸다. 냉각시에 다시 압축응력의 크기는 증가된다.In addition, in the case of the HDP thin film, as shown in FIG. Upon cooling again the magnitude of the compressive stress is increased.
그리고, 질화막의 경우, 도 2c에 도시된 바와같이, 증착상태에서는 압축응력이며, 온도가 증가됨에 따라 인장응력으로 변화되며, 냉각(cooling)시는 응력이 거의 없는 상태가 된다.In the case of the nitride film, as shown in FIG. 2C, the compressive stress in the deposition state is changed to the tensile stress as the temperature is increased, and there is almost no stress during cooling.
이러한 응력 히스테리시스 결과를 토대로 열처리시에 Al과 HDP막에서 각각 발생하는 응력의 상태를 도 3a 내지 도 3c를 참조하여 설명하면 다음과 같다.Based on the stress hysteresis result, the states of the stresses generated in the Al and HDP films during the heat treatment will be described with reference to FIGS. 3A to 3C as follows.
여기서, 화살표 방향은 막이 가고 싶어 하는 방향을 나타내며, 화살표 길이는 응력 크기를 나타낸다.Here, the arrow direction indicates the direction in which the film is desired to go, and the arrow length indicates the stress magnitude.
도 3a 및 도 3c에 도시된 바와 같이, 상온과 냉각시에는 금속막(11, 인장응력)과 HDP막(13, 압축응력)간의 응력방향이 서로 반대로 작용하여 응력완화 효과를 가져올 수 있으나, 도 3b에 도시된 열처리시에는 금속의 응력이 압축응력으로 작용하므로 Al, HDP, 질화막 모두 압축 응력을 나타내게 되어 매우 높은 응력이 발생하게 된다. 따라서, 열처리단계에서 금속배선의 상부 모서리지역에서의 HDP막의 크랙(crack)이 발생된다.As shown in FIGS. 3A and 3C, the stress direction between the metal film 11 (tensile stress) and the HDP film 13 (compressive stress) may be reversed at room temperature and cooling to bring about a stress relaxation effect. In the heat treatment shown in 3b, since the stress of the metal acts as a compressive stress, Al, HDP, and nitride film all exhibit compressive stress, and very high stress is generated. Therefore, a crack of the HDP film is generated in the upper edge region of the metal wiring in the heat treatment step.
또한, 위에서 언급한 바와같이, 약 450℃ 정도의 온도면 Al이 액체거동을 보이게 되므로써 도 1에서와 같이 HDP크랙을 통한 Al 배선 브릿지를 유발하게 된다.In addition, as mentioned above, since Al exhibits liquid behavior at a temperature of about 450 ° C., it causes an Al wiring bridge through the HDP crack as shown in FIG. 1.
따라서, 본 발명은 상기한 바와 같은 종래기술의 제반 문제점을 해결하기 위해 안출한 것으로서, HDP막의 응력 및 두께를 조절하여 크랙을 억제할 수 있는 반도체소자의 절연막 크랙 억제방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide an insulating film crack suppression method of a semiconductor device capable of suppressing cracks by controlling stress and thickness of an HDP film as described above to solve various problems of the prior art. .
상기와 같은 목적을 달성하기 위하여, 본 발명은, 반도체기판 상에 일정간격을 두고 다수의 금속배선을 형성하는 단계; 상기 금속배선 상에 응력완화막을 형성하는 단계; 상기 응력완화막이 형성된 금속배선에 대해 응력완화 열처리를 진행하는 단계; 및 상기 금속배선 상단 모서리부에서의 균열 발생이 억제되도록 기판 결과물 상에 HDP막을 11,300Å 이상의 두께로 증착하는 단계;를 포함하는 반도체소자의 절연막 크랙 억제방법을 제공한다. In order to achieve the above object, the present invention comprises the steps of forming a plurality of metal wiring on a semiconductor substrate at a predetermined interval; Forming a stress relaxation film on the metal wiring; Performing a stress relaxation heat treatment on the metal wiring on which the stress relaxation film is formed; And depositing an HDP film to a thickness of 11,300 GPa or more on a substrate resultant so that the occurrence of cracks in the upper edge portion of the metal wiring is suppressed.
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(실시예)(Example)
이하, 본 발명에 따른 반도체소자 제조시의 크랙 억제방법에 대해 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a crack suppression method in manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 4는 본 발명에 따른 반도체소자의 절연막 크랙 억제방법에 있어서의 금속막과 HDP막 및 질화막에서의 응력 현상이 나타난 소자 단면도이다.4 is a cross-sectional view illustrating devices in which stress phenomena occur in a metal film, an HDP film, and a nitride film in the method for suppressing insulation cracks of a semiconductor device according to the present invention.
도 5은 본 발명에 따른 HDP막의 응력/모서리부간 증착 두께비에 따른 크랙 억제값을 비교한 그래프이다.5 is a graph comparing crack suppression values according to the deposition thickness ratio between stress / edge portions of the HDP film according to the present invention.
도 6은 본 발명에 따른 HDP두께에 따른 크랙의 변화를 나타낸 것이고, 도 7은 HDP 응력에 따른 크랙의 변화를 나타낸 그래프이다.6 is a view showing a change in crack according to the HDP thickness according to the present invention, Figure 7 is a graph showing a change in crack according to the HDP stress.
본 발명에 따른 반도체소자의 절연막 크랙 억제방법은, 도 4에 도시된 바와같이, 기존의 경우(도 3b 참조)에 가열시의 응력상태가 금속막 및 HDP막 모두 압축응력이 발생되기 때문에 막의 응력상태를 변화시키는, 예를들어 압축→인장으로 변화시키거나 완화시키는 방법을 제안한다. In the method of suppressing the insulating film crack of the semiconductor device according to the present invention, as shown in FIG. 4, in the conventional case (see FIG. 3B), the stress of the film is caused because the compressive stress occurs in both the metal film and the HDP film. We propose a method of changing or mitigating a state, for example from compression to tension.
또한, 본 발명에 따른 반도체소자의 절연막 크랙 억제방법은, 균열취약 부위, 즉, 금속배선 상단 모서리부(metal line top corner)의 HDP막 두께를 증가시키므로써 종래와 동일한 응력이 가해지더라도 이 부위에서 균열 발생을 억제하는 방법을 제안한다.In addition, the insulating film crack suppression method of the semiconductor device according to the present invention increases the thickness of the HDP film at the crack-vulnerable portion, that is, the metal line top corner, even if the same stress is applied as before. We propose a method of suppressing the occurrence of cracks.
본 발명은, 도 4에 도시된 바와같이, 반도체기판(도시안됨) 상에 일정간격을 두고 다수의 금속배선(31)을 형성한 후, 상기 다수의 금속배선(31)을 포함한 반도체기판 상에 HDP막(33)을 형성하고, 이어서, 상기 HDP막(33) 상에 보호막으로 질화막(35)을 증착한다. 이때, 상기 HDP막 형성시의 바이어스 파워는 2000∼3000 W로 조절한다.The present invention, as shown in Figure 4, after forming a plurality of metal wiring 31 at a predetermined interval on the semiconductor substrate (not shown), and on the semiconductor substrate including the plurality of metal wiring 31 An HDP film 33 is formed, and then a nitride film 35 is deposited on the HDP film 33 as a protective film. At this time, the bias power at the time of forming the HDP film is adjusted to 2000 to 3000W.
또한, 상기 HDP막(33)의 형성 전, 금속배선(31) 상에 응력완화막(37)을 형성한다. 이때, 상기 응력완화막(37)의 응력은 -1.0∼+3.0dyn/m2 범위를 갖도록 하며, 그 두께는 100∼1000Å 정도로 한다. 그리고, 상기 응력완화막(37)으로서는 TEOS, SiON, TiCl4 또는 TiN 중에서 어는 하나를 선택하여 사용한다.In addition, before the HDP film 33 is formed, a stress relaxation film 37 is formed on the metal wiring 31. At this time, the stress of the stress relaxation film 37 is to be in the range of -1.0 ~ + 3.0dyn / m2, the thickness is about 100 ~ 1000 Pa. As the stress relaxation film 37, any one of TEOS, SiON, TiCl 4 or TiN is selected and used.
한편, 본 발명은 금속배선(31)의 상부 모서리부에 응력집중이 일어나는 것을 방지할 목적으로 상기 금속배선(31)의 상부 모서리부를 라운드지게 형성할 수 있다. On the other hand, the present invention may be formed to round the upper edge of the metal wiring 31 for the purpose of preventing stress concentration on the upper edge of the metal wiring 31.
그 다음, 상기 응력완화막(37)이 형성된 금속배선(33)에 대해 열처리 공정을 추가로 진행한다. 이때, 상기 열처리 공정은 300∼420℃의 온도에서 10∼100분 동안 실시하며, 바람직하게는, 350∼400℃의 온도에서 20∼60분 동안 실시한다. 또한, 상기 열처리 공정은 N2, H2 또는 Ar을 단일 또는 혼합하여 사용한다.Next, a heat treatment process is further performed on the metal wiring 33 on which the stress relaxation film 37 is formed. At this time, the heat treatment process is carried out for 10 to 100 minutes at a temperature of 300 to 420 ℃, preferably, it is carried out for 20 to 60 minutes at a temperature of 350 to 400 ℃. In addition, the heat treatment process uses a single or mixed N 2 , H 2 or Ar.
그리고, 상기 금속배선(31)은 Al을 사용하여 형성하며, 이때, 상기 Al 내부에 Al2O3, W이 포함되도록 한다. 그리고, 상기 Al2O3 및 W을 포함하는 Al막은 그 증착시에 코-스퍼터링(co-sputter) 방법을 사용하여 2상을 동시에 증착한다.The metal wiring 31 is formed using Al, and in this case, Al 2 O 3 and W are included in the Al. In addition, the Al film including Al 2 O 3 and W is deposited at the same time by using a co-sputtering method at the time of deposition.
본 발명에서 제안하는 방법은, 도 4의 "A"인 균열취약 부분, 즉, 금속배선 상부 모서리부의 HDP막의 증착 두께를 증가시키므로써, 이 부위에서의 균열(crack) 발생을 억제할 수 있다. The method proposed in the present invention increases the deposition thickness of the HDP film in the crack-vulnerable portion, ie, the upper edge portion of the metal wiring, which is "A" in FIG. 4, thereby suppressing the occurrence of cracking at this portion.
상기와 같은 조건의 결과를 보면, 도 5의 "B"에서와 같이, 크랙 억제에 대한 실험은 HDP막의 응력/모서리부 두께의 절대값이 5.4E14N/m3이하를 만족해야 된다.As a result of the above conditions, as in " B " of FIG. 5, in the experiment for crack suppression, the absolute value of the stress / edge thickness of the HDP film should satisfy 5.4E14N / m3 or less.
또한, 도 6 및 도 7에 도시된 바와같이, HDP 두께가 증가하면서 HDP 응력이 감소할수록 크랙이 감소된다는 것을 알 수 있다. 특히, HDP 두께가 11,300Å 이상으로 증가하거나 응력/증착 두께 비가 1.5E14(N/m3)이하일 때 크랙이 억제됨을 알 수 있다. 6 and 7, it can be seen that as the HDP thickness increases, the crack decreases as the HDP stress decreases. In particular, it can be seen that the crack is suppressed when the HDP thickness is increased to 11,300 GPa or more or the stress / deposit thickness ratio is 1.5E14 (N / m 3) or less.
한편, 금속막의 열팽창도에 기인한 절연막의 크랙을 억제하는 방법으로 압축응력/인장응력과 같이 반대응력의 스택(stack)을 모든 기술에 가능하다. 즉, 인장/인장/압축을 인장/압축/인장으로 변화시키거나 압축/압축/압축을 압축/인장/압축으로 변화시키는 경우에 가능하다.On the other hand, a stack of counter stresses such as compressive stress / tensile stress can be applied to all techniques in a manner to suppress cracking of the insulating film due to thermal expansion of the metal film. That is, it is possible to change tension / tension / compression to tension / compression / tension or to change compression / compression / compression to compression / tension / compression.
이상에서와 같이, 본 발명은 HDP막의 균열취약부위(crack weak point)의 두께를 증가시키므로써 HDP막의 크랙 발생을 방지할 수 있으며, 이에 따라, 상기 크랙을 통한 금속배선간 브릿지 발생을 를 억제할 수 있다. 즉, 패시베이션 크랙(passivation crack)을 통한 Al 브릿지는 HDP막의 두께를 증가시키거나, 응력를 낮추어 주므로써 억제된다. 특히, 응력/금속막의 모서리부(stress/corner)의 두께비가 5.4E14(N/m3)보다 작거나, 응력/증착두께비가 1.5E14(N/m3)보다 작을 때 크랙발생이 억제된다.As described above, the present invention can prevent the occurrence of cracks in the HDP film by increasing the thickness of the crack weak point of the HDP film, thereby suppressing the occurrence of bridges between the metal wires through the cracks. Can be. That is, the Al bridge through the passivation crack is suppressed by increasing the thickness of the HDP film or lowering the stress. In particular, cracking is suppressed when the thickness ratio of the stress / corner of the stress / metal film is smaller than 5.4E14 (N / m 3) or when the stress / deposition thickness ratio is smaller than 1.5E14 (N / m 3).
따라서, 본 발명은 금속막과 절연막을 사용하여 발생되는 크랙에 대한 억제기술로서 모든 반도체소자에 사용할 수 있다.Therefore, the present invention can be used for all semiconductor devices as a suppression technique for cracks generated by using a metal film and an insulating film.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
도 1은 기존의 HDP크랙에 의한 Al배선의 브릿지 양상을 보여 주기 위한 사진,1 is a photograph showing the bridge aspect of the Al wiring by the conventional HDP crack,
도 2는 기존의 Al막과 HDP막 및 질화막의 응력 히스테리시스에 대해 나타낸 그래프로서, 도 2a는 Al막의 경우이고, 도 2b는 HDP막의 경우이며, 도 2c는 PE 질화막의 경우,FIG. 2 is a graph showing stress hysteresis of a conventional Al film, an HDP film, and a nitride film. FIG. 2A is an Al film, FIG. 2B is a HDP film, and FIG. 2C is a PE nitride film.
도 3a 내지 도 3c는 종래기술에 따른 금속막과 HDP막 및 질화막에서의 응력 현상이 나타난 소자의 단면도,3A to 3C are cross-sectional views of a device in which a stress phenomenon occurs in a metal film, an HDP film, and a nitride film according to the prior art;
도 4는 본 발명에 따른 반도체소자의 절연막 크랙 억제방법에 있어서의 금속막과 HDP막 및 질화막에서의 응력 현상이 나타난 소자의 단면도,4 is a cross-sectional view of a device in which a stress phenomenon occurs in a metal film, an HDP film, and a nitride film in the method for suppressing insulation cracks of a semiconductor device according to the present invention;
도 5은 본 발명에 따른 HDP막의 응력/모서리부 두께비에 따른 크랙 억제값을 비교한 그래프,5 is a graph comparing the crack suppression value according to the stress / edge portion thickness ratio of the HDP film according to the present invention;
도 6은 본 발명에 따른 HDP두께에 따른 크랙의 변화를 나타낸 그래프, 도 7은 HDP 응력에 따른 크랙의 변화를 나타낸 그래프.6 is a graph showing a change in crack according to the HDP thickness according to the present invention, Figure 7 is a graph showing a change in crack according to the HDP stress.
* 도면의 주요 부분에 대한 부호의 설명 * Explanation of symbols on the main parts of the drawings
31 : 금속배선(Al) 33 : HDP막31: metal wiring (Al) 33: HDP film
35 : 질화막 37 : 응력완화막35 nitride film 37 stress relaxation film
A : 금속배선모서리부로부터 HDP막간 두께A: HDP interlayer thickness from metal wiring edge
B : 최적 영역B: optimal area
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