JP5037095B2 - Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a silicon carbide semiconductor device with good reproduction that may not bring about a large scale of the device and is less loss at the time of conduction. <P>SOLUTION: The device includes a semiconductor layer 20 where a first conductive region 4 and a second conductive region 5 are formed on a surface section thereof, and a composite alloy layer 9 that has a first alloy 9a where a first metal that forms an ohmic contact with the region 4 is alloyed with the layer 20 and a second alloy 9b where a second metal that forms an ohmic contact with the region 5 is alloyed with the layer 20 and where the alloy 9a and the alloy 9b are formed so as to be mixed on the surface of the layer 20. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

  In a MOSFET (field effect transistor) using a silicon carbide semiconductor, when forming a contact between a semiconductor element and an external circuit, an ohmic contact having a low contact resistance is provided between the first conductivity type region and the second conductivity type region. The metal to be formed is different. Therefore, in order to reduce the loss during conduction, it is desirable to form ohmic contacts using different metals for the first conductivity type region and the second conductivity type region. However, when an ohmic contact is formed using a different metal for each region, problems such as an increase in the size of the device due to the repetition pitch expansion of the unit transistors and an increase in the number of processes occur. Therefore, an ohmic contact has been proposed in which a plurality of metals are stacked in layers and a metal having a common composition is used for the first conductivity type region and the second conductivity type region. (For example, refer to Patent Document 1.)

Japanese Patent Laying-Open No. 2005-277240 (paragraph 0006, FIG. 1)

  In order to form a low resistance ohmic contact to both the first conductivity type region and the second conductivity type region using the layered metal as described above, the thickness of each metal, the heat treatment temperature, etc. are adjusted. However, the optimum range is narrow. On the other hand, in the actual process, conditions such as the surface roughness and impurity concentration of the first conductivity type region and the second conductivity type region vary, and the optimum range in which an ohmic contact can be formed changes depending on the conditions. Therefore, it has been difficult to manufacture a semiconductor device having uniform characteristics with good reproducibility.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a silicon carbide semiconductor device with low loss during conduction with good reproducibility without causing an increase in size of the device. .

The silicon carbide semiconductor device, the first conductivity type region and the silicon carbide semiconductor layer and a second conductivity type region formed in a surface portion, the first metal forming the first conductivity type region and the ohmic contact carbide A first alloy alloyed with a silicon semiconductor layer, and a second alloy obtained by alloying a second metal forming an ohmic contact with the second conductivity type region with the silicon carbide semiconductor layer, the first alloy And a composite alloy layer formed such that the second alloy is dispersed and arranged on the surface of the silicon carbide semiconductor layer without deviation .

  According to the above configuration, by the composite alloy layer formed in common to the first conductivity type region and the second conductivity type region, the first conductivity type region has an ohmic contact made of an alloy with the first metal, Since the ohmic contact made of an alloy with the second metal is formed in the second conductivity type region, a silicon carbide semiconductor device with low loss during conduction can be obtained with good reproducibility without causing an increase in size of the device.

Embodiment 1 FIG.
FIG. 1 shows an element structure of a silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device of the first embodiment of the present invention. As an example of a silicon carbide semiconductor device, a cross-sectional structure of a silicon carbide MOSFET in which a first conductivity type region is n-type and a second conductivity type region is p-type is shown. 2 shows a method for manufacturing the silicon carbide semiconductor device of the first embodiment of the present invention.

In the figure, 1 is a high concentration n-type (hereinafter referred to as n ⁺ type) silicon carbide substrate (first conductivity type silicon carbide substrate), and 2 is a low concentration n-type (hereinafter referred to as n ⁻ type) drift. Region (first conductivity type silicon carbide drift region), 3 is a p-type base region (second conductivity type silicon carbide base region), 4 is an n ⁺ type source region (first conductivity type silicon carbide source region), 5 is a p ⁺ -type contact region (second conductivity type silicon carbide contact region), 6 is a gate oxide film, 7 is a gate electrode, 8 is an interlayer insulating film, 9 is a composite alloy layer, 10 is a wiring layer, and 11 is a drain. An electrode, 12 is a back surface wiring layer, and 20 is a semiconductor layer.

A method for manufacturing the silicon carbide semiconductor device of the first embodiment of the present invention will be described based on FIGS. 2 (a) to 2 (d).
First, the process up to the step of forming the contact hole 30 in the upper part as shown in FIG. A drift region 2 made of n-type silicon carbide is formed by epitaxial crystal growth on a wafer of n ⁺ -type silicon carbide substrate 1 shown in the lowermost layer in the drawing. After epitaxial crystal growth, impurity ions are implanted into a predetermined region of the surface layer portion of the drift region 2 using a resist as a mask to form the p-type base region 3. Examples of the p-type impurity include aluminum (Al).

Next, impurity ions are implanted into the p-type base region 3 using a resist as a mask to form an n ⁺ -type source region 4 in the surface layer portion of the p-type base region 3. The n ⁺ -type source region 4 has a depth of 0.1 to 1 μm, and as an n-type impurity, for example, nitrogen (N) can be cited, which falls within a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ^−3. It is desirable. The impurity concentration may be uniform in the depth direction or may be distributed so as to increase in the vicinity of the surface. By controlling the impurity concentration at a high concentration in this way, the n ⁺ type source region 4 becomes the first metal. It is possible to form an ohmic contact having a low contact resistance with nickel (Ni).

Further, impurity ions are implanted into the p-type base region 3 using a resist as a mask, and a p ⁺ -type contact region 5 is formed in the central portion of the n ⁺ -type source region 4 in the surface layer portion of the p-type base region 3. . The concentration of the impurity is preferably in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and may be uniform in the depth direction or distributed so as to increase in the vicinity of the surface. By controlling the impurity concentration at a high concentration in this way, the p ⁺ -type contact region 5 has an ohmic contact with a low contact resistance with aluminum (Al), titanium (Ti), cobalt (Co), or the like as the second metal. Can be formed. As a result, both the first conductivity type region (n-type) and the second conductivity type region (p-type) are formed in the surface layer portion of the semiconductor layer 20.

  Thereafter, an annealing process is performed at a high temperature of 1500 ° C. or higher to activate the implanted ions.

Next, a gate oxide film 6 made of SiO _{2 is formed on the} entire upper surface of the semiconductor layer 20 by thermal oxidation, and a polysilicon gate electrode 7 is formed thereon. Thereafter, the gate oxide film 6 and the gate electrode 7 covering the surfaces of the source region 4 and the contact region 5 are removed by etching, and an interlayer insulating film 8 is formed thereon.

  Next, the interlayer insulating film 8 on the source region 4 and the contact region 5 is removed by etching to open a contact hole 30. Then, the source region 4 and the contact region 5 are exposed from the bottom of the contact hole 30 in the semiconductor layer 20 as shown in FIG.

  Next, as shown in FIG. 2B, as a second metal film forming step, a second metal film 22 </ b> M is formed on the surface of the semiconductor layer 20 exposed from the bottom of the contact hole 30. As the second metal, since the second conductivity type region is p-type, the above-described aluminum (Al), titanium (Ti), or cobalt (Co) is used. In the present embodiment, aluminum is deposited on the surface of the semiconductor layer 20 by vapor deposition so that the film thickness falls within the range of 1 to 100 nm, and more desirably within the range of 1 to 10 nm.

  Thereafter, as the second metal placement step, heat treatment is performed by raising the temperature to 200 to 700 ° C. (first treatment temperature), which is not higher than the temperature at which aluminum reacts with the semiconductor layer 20 in vacuum or in an inert gas. Then, as shown in FIG. 2 (c), the second metal film 22M condenses on the surface of the semiconductor layer 20, and becomes an aggregate of several nm to several hundred nm whose diameter is several times the thickness of the film, The second metal aggregates 22 </ b> C are dispersed and arranged on the surface of the semiconductor layer 20.

  The diameter of the second metal aggregate 22 </ b> C is preferably a size of several tens to one hundredth of the size of the contact hole 30 in order to disperse the surface of the source region 4 and the contact region 5 without deviation. . The size of the opening of the contact hole 30 of the MOSFET in this embodiment is about several μm square, and the diameter of the aggregate is preferably adjusted to several hundred nm or less, and more preferably several tens of nm or less. Further, the lower limit of the diameter of the aggregate is desirably kept at several nm or more so that the aggregation control is easy and the influence with the first metal disposed in the process described later is reduced. Since the diameter of the aggregate is about several times the film thickness before aggregation as described above, the film thickness of the second metal film 22M is further in the range of 1 to 10 nm so as to fall within the range of 1 to 100 nm. It is desirable to form so that it may enter.

  Further, a Ni film 31 which is a first metal is formed on the back side of the n-type silicon carbide substrate 1. In the present embodiment, the Ni film 31 is formed by sputtering.

  In addition, when the second metal is disposed on the surface of the semiconductor layer 20, the wafer may be deposited in the state of an aggregate directly by raising the temperature of the wafer in the range of 200 to 700 ° C. in advance. Is possible.

  Next, as a first metal film formation step, as shown in FIG. 2D, a first metal film 21M is formed on the surface of the wafer by vapor deposition. As the first metal, since the first conductivity type region is n-type (the second conductivity type region is p-type), nickel (Ni) is used. At this time, the first metal film 21M is The portion of the surface of the semiconductor layer 20 where the second metal aggregate 22C is not disposed is directly formed on the surface of the semiconductor layer 20, and the second metal aggregate 22C is disposed. The portion is formed on the second metal aggregate 22C. In other words, the first metal film 22M is formed on the surface of the semiconductor layer 20 and on the second metal aggregate 22C so as to fill the gap between the second metal aggregates 22C, and the contact hole. 30 is formed on the entire upper surface of the wafer including the inside.

  The first metal film 21M and the second metal film 22M can be formed by sputtering, ICB (Ion Cluster Beam), MBE (Molecular Beam Epitaxy), CBE (Chemical) in addition to vapor deposition. Beam Epitaxy), CVD (Chemical Vapor Deposition), etc. can be used.

  In addition, during the formation of the first metal film 21M from the formation of the second metal film 22M, the first metal, the second metal, or the semiconductor layer 20 is oxidized by moisture or oxygen in the air, or It is desirable to prevent the wafer from being exposed to the outside air so that moisture and oxygen are not adsorbed.

  Next, as a composite alloy layer forming step, the entire wafer is set at a set temperature (second processing temperature) of about 600 ° C. to 1200 ° C. higher than the first processing temperature in vacuum or in an inert gas for 10 seconds to 30 minutes. Heat treatment. By performing heat treatment at this temperature, Ni, which is the first metal in contact with the wafer, reacts with the silicon carbide portion to form an alloy (nickel silicide), and the second metal in contact with the wafer also reacts with the silicon carbide portion. Thus, an alloy (each metal silicide) is formed. In the present embodiment, the second metal aggregate 22b reacts with the second metal aggregate 22C in direct contact with the semiconductor layer 20 and the semiconductor layer 20 to form the first alloy in direct contact with the semiconductor layer 20. The metal film 21M and the semiconductor layer 20 react to generate the first alloy 9a, and the composite alloy layer 9 in which the first alloy 9a and the second alloy 9b are mixed in the surface of the semiconductor layer 20 is formed. . Also, an alloy layer is formed on the surface of silicon carbide substrate 1 (lower side in the figure) by reaction with Ni film 31.

  The first alloy 9a and the second alloy 9b only have to be mixed in the plane direction of the semiconductor layer 20, and the conditions for forming the second metal aggregate 22C are changed, The alloy may be dispersed in stripes or lattices.

  Of the first alloy 9a, a portion formed in the n-type source region 4 portion of the first conductivity type forms an ohmic contact. And the part formed in the p-type contact region 5 part which is a 2nd conductivity type area | region among the said 2nd alloys 9b forms an ohmic contact. The alloy layer formed by the reaction between the n-type silicon carbide substrate 1 and the first metal Ni film 31 forms an ohmic contact over the entire surface and functions as the drain electrode 11.

  Then, the wafer is washed with an acid such as sulfuric acid or phosphoric acid to remove the unreacted second metal aggregate 22C that has not contacted the silicon carbide portion and has not been alloyed, and the first metal film 21M. After that, if the graphite layer precipitated with the heat treatment is removed by a dry process such as oxygen plasma, a more reliable ohmic contact can be formed.

  Finally, as a wiring layer forming step, the wiring layer 10 connected to the external circuit is formed on the upper portion of the wafer, and the back surface connecting wiring 12 is formed on the drain electrode 11 on the lower portion of the wafer, thereby obtaining the silicon carbide semiconductor device shown in FIG. . The wiring layer 10 is formed so as to fill the upper surface of the wafer so as to obtain a sufficient cross-sectional area for patterning and sputtering an aluminum film, and is directly connected to the composite alloy layer 9. That is, the wiring layer 10 is connected to the n-type source region 4 which is the first conductivity type and the p-type contact region 5 which is the second conductivity type via the composite alloy layer 9. The back connection wiring 12 can be formed by sputtering Ni, gold (Au), or the like.

Next, the operation of the silicon carbide semiconductor obtained by the manufacturing method according to the above embodiment will be described.
When no voltage is applied to the gate electrode 7, a channel is not formed in the base region 3 immediately below the gate electrode 7, so even if a high voltage is applied between the wiring layer 10 and the back surface connection wiring 12, the wiring layer A current does not flow between 10 and the back surface connection wiring 12, and a so-called OFF state is obtained.

  On the other hand, when a positive voltage is applied to the gate electrode 7, a channel is formed in the base region 3 immediately below the gate electrode 7, and a so-called ON state is established so that electrons flow from the source region 4 to the drift region 2. When a voltage is applied between the wiring layer 10 and the back surface connection wiring 12, a current flows through the path of the composite alloy layer 9 -source region 4 -base region 3 -drift region 2 -silicon carbide substrate 1 -drain electrode 11. .

  At this time, the ON resistance between the wiring layer 10 and the back surface connection wiring 12 is the contact resistance between the wiring layer 10 and the semiconductor element (between the wiring layer 10 and the source region 4, between the silicon carbide semiconductor substrate 1 and the back surface connection wiring 12). , It is defined by the resistance inside the semiconductor element (source region 4-base region 3-drift region 2-silicon carbide substrate 1).

  As for the resistance inside the semiconductor element, by using a silicon carbide semiconductor, a low resistance can be realized as compared with a silicon semiconductor.

  As described above, the contact resistance between wiring layer 10 and the semiconductor element varies depending on the metal in contact with the silicon carbide semiconductor. According to the present embodiment, since the source region 4 and the wiring layer 10 of the first conductivity type are connected via the composite alloy layer 9, the first conductivity type is mixed at the interface between the source region 4 and the wiring layer 10. By the ohmic contact by the 1 alloy 9a, the contact resistance between the source region 4 and the wiring layer 10 is reduced, and the loss during conduction can be kept low.

  On the other hand, since the contact region 5 of the second conductivity type and the wiring layer 10 are also connected through the composite alloy layer 9, ohmic contact by the second alloy 9b mixed at the interface between the contact region 5 and the wiring layer 10 is performed. The contact resistance between the contact region 5 and the wiring layer 10 is also reduced, and the loss during conduction can be kept low.

  Further, according to the present embodiment, the first metal capable of forming an ohmic contact with the n-type silicon carbide is directly n-type at the interface between the n-type source region 4 and the wiring layer 10 which are the first conductivity type. A second metal that is in contact with the source region 4 and can form an ohmic contact with p-type silicon carbide at the interface between the p-type contact region 5 and the wiring layer 10 of the second conductivity type is in direct contact with the p-type contact region. is doing. For this reason, the allowable ranges such as heat treatment conditions and alloy layer thickness for forming ohmic contacts are widened, the roughness of the surface state of the wafer processed in the actual process (roughness) and the residue state of contact inhibition films such as oxide films Even if there is a variation, uniform ohmic contact can be formed, so that stable low resistance can be realized, and yield and quality stability can be improved.

  Further, since the ohmic contact between the wiring layer, the first conductivity type region and the second conductivity type region can be formed by a composite alloy layer formed by a common process, the unit element is made small and the apparatus is increased in size. Therefore, it is easy to reduce loss during conduction.

  Note that the lower the contact resistance between the first conductivity type region and the second conductivity type region, the better. However, in an actual semiconductor device, the contribution of the resistance in each region may be different. It does not have to be low resistance. For example, in the MOSFET according to the present embodiment, the contact resistance to the source region 4 affects the loss at the time of conduction, so the effect when the contact resistance is reduced is great. On the other hand, the contact region 5 may be an ohmic contact that fixes the potential of the base region 3 to ground. In such a case, according to the present embodiment, the ratio of the area of the first alloy 9a and the area of the second alloy 9b is controlled, and the resistance between the source region 4 and the wiring layer 10 is preferentially reduced to be conductive. It becomes possible to reduce time loss more efficiently.

  In the present embodiment, after the second metal aggregate 22C capable of forming an ohmic contact with the second conductivity type region is disposed, the first ohmic contact can be formed with respect to the first conductivity type region. Although the metal film 21M is formed, the reverse may be possible. In other words, after the first metal aggregate capable of forming an ohmic contact with respect to the first conductivity type region is disposed, a second metal film capable of forming an ohmic contact with respect to the second conductivity type region is formed. The same effect can be obtained.

  Also, after the second metal aggregate 22C is disposed, heat treatment is performed to react the second metal with the semiconductor layer 20 to form the second alloy 9b on the surface of the semiconductor layer 20, and then the first metal The composite alloy layer 9 may be formed by forming the metal film 21M and performing heat treatment again.

  In each of the above embodiments, an example in which n-type is used as the first conductivity type region and p-type is used as the second conductivity type region has been described. Conversely, p-type is used as the first conductivity type region and Even if n-type is used, the same effect can be obtained.

3 is a cross sectional view of a silicon carbide semiconductor device obtained by the manufacturing method of the first embodiment. FIG. 3 is a diagram showing a method for manufacturing the silicon carbide semiconductor device of the first embodiment. FIG.

Explanation of symbols

1 silicon carbide semiconductor substrate, 2 drift region, 3 base region, 4 source region (first conductivity type), 5 contact region (second conductivity type), 9 composite alloy layer, 9a first alloy, 9b second alloy, 10 Wiring layer, 20 semiconductor layer, 21M first metal film, 22M second metal film, 22C second metal aggregate,

Claims (7)

A silicon carbide semiconductor layer in which a first conductivity type region and a second conductivity type region are formed in a surface layer portion;
Said first and alloy the first metal and the silicon carbide semiconductor layer and alloying of forming said first conductivity type region and the ohmic contact, the second metal forming the second conductivity type region and the ohmic contact carbide and a second alloy silicon semiconductor layer alloyed with said first alloy and said second alloy and said silicon carbide semiconductor layer composite alloy layer formed so as to disperse to arranged evenly on the surface of the ,
A silicon carbide semiconductor device comprising: 2. The silicon carbide semiconductor device according to claim 1, wherein one of the first metal and the second metal is an agglomerated metal. When the first conductivity type region is n-type silicon carbide and the second conductivity type region is p-type silicon carbide, the first metal is Ni, and the second metal is any one of Al, Ti, and Co. The silicon carbide semiconductor device according to claim 1 , wherein the silicon carbide semiconductor device is a silicon carbide semiconductor device. A method for manufacturing a silicon carbide semiconductor device having a silicon carbide semiconductor layer in which a first conductivity type region and a second conductivity type region are formed in a surface layer portion,
And the second metal film forming step of forming a second metal film forming the second conductivity type region and the ohmic contact on the surface of the silicon carbide semiconductor layer,
Heat-treated at a first treatment temperature, the second to form aggregates of the second metal to coagulate the second metal film arranged distributed evenly on the surface of the silicon carbide semiconductor layer A metal placement process;
The first metal film forming the first conductivity type region and the ohmic contact, a first metal film forming step of forming on the surface of the silicon carbide semiconductor layer,
Higher than said first processing temperature and heat-treated at a second treatment temperature, with the first metal in contact with the silicon carbide semiconductor layer to generate a first alloy is reacted with the silicon carbide semiconductor layer, said silicon carbide The second metal in contact with the semiconductor layer reacts with the silicon carbide semiconductor layer to form a second alloy, and the first alloy and the second alloy are uniformly distributed on the surface of the silicon carbide semiconductor layer. A composite alloy layer forming step of forming a composite alloy layer to be disposed ; and
A method for manufacturing a silicon carbide semiconductor device comprising: When the first conductivity type region is n-type silicon carbide and the second conductivity type region is p-type silicon carbide, the first metal is Ni, and the second metal is any one of Al, Ti, and Co. The method for manufacturing a silicon carbide semiconductor device according to claim 4 , wherein: 6. The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein the first processing temperature is in a range of 200 to 700 ° C. 6. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 4 to 6, wherein the second processing temperature is in a range of 600 to 1200 ° C.

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