JP5014749B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

  In a MOSFET (field effect transistor) using a silicon carbide semiconductor, when forming a contact between a semiconductor element and an external circuit, an ohmic contact having a low contact resistance is provided between the first conductivity type region and the second conductivity type region. The metal to be formed is different. Therefore, in order to reduce the loss during conduction, it is desirable to form ohmic contacts using different metals for the first conductivity type region and the second conductivity type region. However, when an ohmic contact is formed using a different metal for each region, problems such as an increase in the size of the device due to the repetition pitch expansion of the unit transistors and an increase in the number of processes occur. Therefore, a method has been proposed in which a plurality of metals are stacked in layers and an ohmic contact is formed using a metal having a common composition in the first conductivity type region and the second conductivity type region. (For example, refer to Patent Document 1.)

Japanese Patent Laying-Open No. 2005-277240 (paragraph 0006, FIG. 1)

  In the method of forming a low-resistance ohmic contact to both the first conductivity type region and the second conductivity type region using the layered metal as described above, the film thickness of each metal, the heat treatment temperature, etc. are adjusted. However, the optimum range is narrow. On the other hand, in the actual process, conditions such as the surface roughness and impurity concentration of the first conductivity type region and the second conductivity type region vary, and the optimum range in which an ohmic contact can be formed changes depending on the conditions. Therefore, it has been difficult to manufacture a semiconductor device having uniform characteristics with good reproducibility.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a silicon carbide semiconductor device with low loss during conduction with good reproducibility without causing an increase in size of the device. .

The method for manufacturing the silicon carbide semiconductor device includes a first metal particle arrangement step in which to place the surface of the semiconductor layer by a first metal particles forming the first conductivity type region and the ohmic contact with a gap to each other, the first A first metal alloying step in which a first metal is reacted with the semiconductor layer to form a first alloy, and a second metal film forming an ohmic contact with the second conductivity type region is formed on the surface of the semiconductor layer and the second metal film forming step you, the second metal to produce a second alloy is reacted with the semiconductor layer, the first alloy and the second alloy are mixed in the surface of the semiconductor layer composite a composite alloy layer forming step of forming an alloy layer, ing contains.

  According to the manufacturing method described above, the first metal that forms an ohmic contact with the first conductivity type region, the second conductivity type region, and the second conductivity type region through a process common to the first conductivity type region and the second conductivity type region. Since the ohmic contact can be formed by directly contacting the second metal that forms the ohmic contact, a silicon carbide semiconductor device with little loss during conduction can be obtained with good reproducibility without causing an increase in size of the device.

Embodiment 1 FIG.
FIG. 1 shows an element structure of a silicon carbide semiconductor device manufactured by the method for manufacturing a silicon carbide semiconductor device of the first embodiment of the present invention. As an example of a silicon carbide semiconductor device, a cross-sectional structure of a silicon carbide MOSFET in which a first conductivity type region is n-type and a second conductivity type region is p-type is shown. 2 shows a method for manufacturing the silicon carbide semiconductor device of the first embodiment of the present invention.

In the figure, 1 is a high concentration n-type (hereinafter referred to as n ⁺ type) silicon carbide substrate (first conductivity type silicon carbide substrate), and 2 is a low concentration n-type (hereinafter referred to as n ⁻ type) drift. Region (first conductivity type silicon carbide drift region), 3 is a p-type base region (second conductivity type silicon carbide base region), 4 is an n ⁺ type source region (first conductivity type silicon carbide source region), 5 is a p ⁺ -type contact region (second conductivity type silicon carbide contact region), 6 is a gate oxide film, 7 is a gate electrode, 8 is an interlayer insulating film, 9 is a composite alloy layer, 10 is a wiring layer, and 11 is a drain. An electrode, 12 is a back surface wiring layer, 20 is a semiconductor layer, and 22M is a second metal film.

A method for manufacturing the silicon carbide semiconductor device of the first embodiment of the present invention will be described with reference to FIGS. 2 (a) to 2 (c).
First, the process up to the step of forming the contact hole 30 in the upper part as shown in FIG. A drift region 2 made of n-type silicon carbide is formed by epitaxial crystal growth on a wafer of n ⁺ -type silicon carbide substrate 1 shown in the lowermost layer in the drawing. After epitaxial crystal growth, impurity ions are implanted into a predetermined region of the surface layer portion of the drift region 2 using a resist as a mask to form the p-type base region 3. Examples of the p-type impurity include aluminum (Al).

Next, impurity ions are implanted into the p-type base region 3 using a resist as a mask to form an n ⁺ -type source region 4 in the surface layer portion of the p-type base region 3. The n ⁺ -type source region 4 has a depth of 0.1 to 1 μm, and as an n-type impurity, for example, nitrogen (N) can be cited, which falls within a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ^−3. It is desirable. The impurity concentration may be uniform in the depth direction or may be distributed so as to increase in the vicinity of the surface. By controlling the impurity concentration at a high concentration in this way, the n ⁺ type source region 4 becomes the first metal. It is possible to form an ohmic contact having a low contact resistance with nickel (Ni).

Further, impurity ions are implanted into the p-type base region 3 using a resist as a mask, and a p ⁺ -type contact region 5 is formed in the central portion of the n ⁺ -type source region 4 in the surface layer portion of the p-type base region 3. . The concentration of the impurity is preferably in the range of 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ , and may be uniform in the depth direction or distributed so as to increase in the vicinity of the surface. By controlling the impurity concentration at a high concentration in this way, the p ⁺ -type contact region 5 has an ohmic contact with a low contact resistance with aluminum (Al), titanium (Ti), cobalt (Co), or the like as the second metal. Can be formed. As a result, both the first conductivity type region (n-type) and the second conductivity type region (p-type) are formed in the surface layer portion of the semiconductor layer 20.

  Thereafter, an annealing process is performed at a high temperature of 1500 ° C. or higher to activate the implanted ions.

Next, a gate oxide film 6 made of SiO _{2 is formed on the} entire upper surface of the semiconductor layer 20 by thermal oxidation, and a polysilicon gate electrode 7 is formed thereon. Thereafter, the gate oxide film 6 and the gate electrode 7 covering the surfaces of the source region 4 and the contact region 5 are removed by etching, and an interlayer insulating film 8 is formed thereon.

  Next, the interlayer insulating film 8 on the source region 4 and the contact region 5 is removed by etching to open a contact hole 30. Then, the source region 4 and the contact region 5 are exposed from the bottom of the contact hole 30 in the semiconductor layer 20 as shown in FIG.

  Next, as shown in FIG. 2B, as the first metal arranging step, first metal particles 21 </ b> P are arranged on the surface of the semiconductor layer 20 exposed from the bottom of the contact hole 30. As the first metal, since the first conductivity type region is n-type (the second conductivity type region is p-type), the above-described nickel (Ni) is used, and in this embodiment, the diameter is several hundreds. nm Ni particles are used. As a method for arranging the particles, a liquid in which Ni particles are dispersed can be arranged on the surface of the semiconductor layer 20 by applying the liquid on a wafer using, for example, spin coating and then drying. In this case, it is desirable that the Ni particles 21P, which are the first metal, do not completely cover the surface of the semiconductor layer 20, and are arranged with a certain amount of gaps when viewed from above. The diameter of the first metal particle 21 </ b> P is preferably a size of several tens to one hundredths of the size of the contact hole 30 in order to disperse the surface of the source region 4 and the contact region 5 without deviation. The size of the opening of the contact hole 30 of the MOSFET in this embodiment is about several μm square, and the desired particle size is several hundred nm or less. Further, the lower limit of the diameter of the particles is desirably kept at several nm or more so that the influence of the second metal disposed in the process described below can be easily dispersed in the liquid and the influence of the second metal is reduced. Further, since there is a step of removing unreacted Ni described later, there is no problem even if Ni particles adhere to the interlayer insulating film 8 other than the semiconductor layer 20.

  Further, a Ni film 31 which is a first metal is formed on the back side of the n-type silicon carbide substrate 1. In the present embodiment, the Ni film 31 is formed by sputtering.

  Next, as the first metal alloying step, the entire wafer is heat-treated at a processing temperature of about 600 ° C. to 1200 ° C. in vacuum or in an inert gas for 10 seconds to 30 minutes. By performing the heat treatment at this temperature, Ni in contact with the wafer reacts with the silicon carbide portion to form an alloy (nickel silicide). In the present embodiment, a first alloy 9a made of an alloy of the semiconductor layer 20 and the first metal is formed on the surface of the semiconductor layer 20 where Ni particles are in contact, and the silicon carbide An alloy layer formed by reaction with the Ni film 31 is also formed on the surface of the substrate 1 (lower side in the figure).

  Of the first alloy 9a, a portion formed in the n-type source region 4 portion of the first conductivity type forms an ohmic contact. At the same time, the alloy layer formed by the reaction between the n-type silicon carbide substrate 1 and the Ni film 31 as the first metal forms an ohmic contact over the entire surface and functions as the drain electrode 11.

  Then, the wafer is washed with an acid such as sulfuric acid or phosphoric acid to remove unreacted Ni particles 21P that have not contacted the silicon carbide portion and have not been alloyed.

  Next, as a second metal film forming step, as shown in FIG. 2C, a second metal film 22M is formed on the surface of the wafer by vapor deposition. As the second metal, since the second conductivity type region is p-type, aluminum (Al), titanium (Ti), or cobalt (Co) is used as described above. At this time, the second metal film 22M is directly formed on the surface of the semiconductor layer 20 in the portion of the surface of the semiconductor layer 20 where the first alloy 9a is not formed, and the first alloy 9a. The portion where is formed is formed on the first alloy 9a. That is, the second metal film 22M is formed on the surface of the semiconductor layer 20 and the first alloy 9a so as to fill the gap portion of the first alloy 9a, and the entire upper surface of the wafer including the inside of the contact hole 30. Formed.

  The second metal film 22M can be formed by sputtering, ICB (Ion Cluster Beam), MBE (Molecular Beam Epitaxy), CBE (Chemical Beam Epitaxy), CVD (Chemical) in addition to vapor deposition. Vapor Deposition) method or the like can be used.

  Next, as a composite alloy layer forming step, the entire wafer is again heat-treated at a processing temperature of about 600 ° C. to 1200 ° C. in vacuum or in an inert gas for 10 seconds to 30 minutes. By heat treatment at this temperature, aluminum, titanium, or cobalt in contact with the silicon carbide portion of the wafer reacts with silicon carbide to form an alloy (metal silicide). At this time, the second metal is not alloyed in the portion where the first alloy 9a is already formed, and the portion of the surface of the semiconductor layer 20 where the second metal film 22M is in direct contact, that is, the first metal A second alloy 9b made of an alloy of the semiconductor layer 20 and the second metal is formed in the gap portion of the alloy 9a, and is formed in the p-type contact region 5 portion which is the second conductivity type region in the second alloy 9b. The formed part forms an ohmic contact. Then, the composite alloy layer 9 in which the first alloy 9 a and the second alloy 9 b are mixed in the surface of the semiconductor layer 20 is formed on the surface of the semiconductor layer 20 exposed from the bottom of the contact hole 30. . The unreacted portion of the second metal film 22M may be removed by acid after the heat treatment for forming the second alloy 9b, or may be left as it is.

  The first alloy 9a and the second alloy 9b only have to be mixed in the plane direction of the semiconductor layer 20, and the conditions for arranging the first metal are changed so that each alloy is striped. Alternatively, it may be dispersed in a grid pattern.

  Between the formation of the second metal film 22M and the heat treatment, the first metal, the second metal, or the semiconductor layer 20 is not oxidized by moisture or oxygen in the air or adsorbed by moisture or oxygen. It is desirable to prevent the wafer from being exposed to the outside air. After that, if the graphite layer precipitated with the heat treatment is removed by a dry process such as oxygen plasma, a more reliable ohmic contact can be formed.

  Finally, as a wiring layer forming step, the wiring layer 10 connected to the external circuit is formed on the upper portion of the wafer, and the back surface connecting wiring 12 is formed on the drain electrode 11 on the lower portion of the wafer, thereby obtaining the silicon carbide semiconductor device shown in FIG. It is done. The wiring layer 10 is formed by sputtering and patterning an aluminum film so as to fill the upper surface of the wafer so as to obtain a sufficient cross-sectional area for taking out current, and is directly connected to the composite alloy layer 9. That is, the wiring layer 10 is connected to the n-type source region 4 which is the first conductivity type and the p-type contact region 5 which is the second conductivity type via the composite alloy layer 9. The back connection wiring 12 can be formed by sputtering Ni, gold (Au), or the like.

Next, the operation of the silicon carbide semiconductor obtained by the manufacturing method according to the above embodiment will be described.
When no voltage is applied to the gate electrode 7, a channel is not formed in the base region 3 immediately below the gate electrode 7, so even if a high voltage is applied between the wiring layer 10 and the back surface connection wiring 12, the wiring layer A current does not flow between 10 and the back surface connection wiring 12, and a so-called OFF state is obtained.

  On the other hand, when a positive voltage is applied to the gate electrode 7, a channel is formed in the base region 3 immediately below the gate electrode 7, and a so-called ON state is established so that electrons flow from the source region 4 to the drift region 2. When a voltage is applied between the wiring layer 10 and the back surface connection wiring 12, a current flows through the path of the composite alloy layer 9 -source region 4 -base region 3 -drift region 2 -silicon carbide substrate 1 -drain electrode 11. .

  At this time, the ON resistance between the wiring layer 10 and the back surface connection wiring 12 is the contact resistance between the wiring layer 10 and the semiconductor element (between the wiring layer 10 and the source region 4, between the silicon carbide semiconductor substrate 1 and the back surface connection wiring 12). , It is defined by the resistance inside the semiconductor element (source region 4-base region 3-drift region 2-silicon carbide substrate 1).

  As for the resistance inside the semiconductor element, by using a silicon carbide semiconductor, a low resistance can be realized as compared with a silicon semiconductor.

  As described above, the contact resistance between wiring layer 10 and the semiconductor element varies depending on the metal in contact with the silicon carbide semiconductor. According to the present embodiment, since the source region 4 and the wiring layer 10 of the first conductivity type are connected via the composite alloy layer 9, the first conductivity type is mixed at the interface between the source region 4 and the wiring layer 10. By the ohmic contact by the 1 alloy 9a, the contact resistance between the source region 4 and the wiring layer 10 is reduced, and the loss during conduction can be kept low.

  On the other hand, since the contact region 5 of the second conductivity type and the wiring layer 10 are also connected through the composite alloy layer 9, ohmic contact by the second alloy 9b mixed at the interface between the contact region 5 and the wiring layer 10 is performed. The contact resistance between the contact region 5 and the wiring layer 10 is also reduced, and the loss during conduction can be kept low.

  Further, according to the present embodiment, the first metal capable of forming an ohmic contact with the n-type silicon carbide is directly n-type at the interface between the n-type source region 4 and the wiring layer 10 which are the first conductivity type. A second metal that is in contact with the source region 4 and can form an ohmic contact with p-type silicon carbide at the interface between the p-type contact region 5 and the wiring layer 10 of the second conductivity type is in direct contact with the p-type contact region. is doing. For this reason, the allowable ranges such as heat treatment conditions and alloy layer thickness for forming ohmic contacts are widened, the roughness of the surface state of the wafer processed in the actual process (roughness) and the residue state of contact inhibition films such as oxide films Even if there is a variation, uniform ohmic contact can be formed, so that stable low resistance can be realized, and yield and quality stability can be improved.

  In addition, since the ohmic contact between the wiring layer 10 connected to the external circuit and the first conductivity type region and the second conductivity type region can be formed by a common process, the unit element is made small, resulting in an increase in size of the device. It becomes easy to reduce the loss at the time of conduction.

  In the present embodiment, the second metal film 22M formed in a film shape may remain unreacted, but it functions as a simple conductor film with the wiring layer 10 and operates as described above. Will not be disturbed. Further, after the first metal particles 21P capable of forming an ohmic contact with respect to the first conductivity type region are disposed, the second metal film 22M capable of forming an ohmic contact with respect to the second conductivity type region is formed. However, the reverse is also possible. That is, after a second metal capable of forming an ohmic contact with respect to the second conductivity type region is arranged as particles, a first metal film capable of forming an ohmic contact with respect to the first conductivity type region is formed. The same effect can be obtained.

  Further, after the first metal is arranged as particles, a second metal film is formed without performing heat treatment, and the first metal and the second metal are simultaneously heat treated to form the composite alloy layer 9. You may do it.

Embodiment 2. FIG.
FIG. 3 shows an element structure of the silicon carbide semiconductor device manufactured by the method for manufacturing the silicon carbide semiconductor device of the second embodiment of the present invention. This embodiment also shows a cross-sectional structure of a silicon carbide MOSFET in which the first conductivity type region is n-type and the second conductivity type region is p-type. FIG. 4 shows a method for manufacturing the silicon carbide semiconductor device of the second embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 1 or 2 denote the same or corresponding parts.

  The method for manufacturing the silicon carbide semiconductor device of the second embodiment of the present invention differs from the method of forming the composite alloy layer 9 in the manufacturing method of the first embodiment, and forms the contact hole 30 shown in FIG. Since it is the same up to the process to perform, description is abbreviate | omitted and it demonstrates based on FIG.4 (b)-FIG.4 (c).

  After the contact hole 30 is formed as shown in FIG. 4A, as shown in FIG. 4B, as the metal particle arranging step, the first surface is formed on the surface of the semiconductor layer 20 exposed from the bottom of the contact hole 30. The metal particles 21P and the second metal particles 22P are arranged. As in the first embodiment, nickel (Ni) is used as the first metal, and aluminum (Al), titanium (Ti), or cobalt (Co) is used as the second metal. Similarly to the first embodiment, the first metal particle 21P and the second metal particle 22P are particles having a diameter of several hundred nm.

  As a method for arranging the particles, the liquid in which the first metal particles 21P and the second metal particles 22P are dispersed is applied onto the wafer by spin coating and then dried. In this case, since there is a step of removing unreacted metal, which will be described later, there is no problem even if each metal particle adheres to the interlayer insulating film 8 or the like other than the semiconductor layer 20.

  Further, a Ni film 31 which is a first metal is formed on the back side of the n-type silicon carbide substrate 1. In the present embodiment, the Ni film 31 is formed by sputtering.

  Next, as a composite alloy layer forming step, the entire wafer is heat-treated at a processing temperature of about 600 ° C. to 1200 ° C. in vacuum or in an inert gas for 10 seconds to 30 minutes. By performing heat treatment at this temperature, Ni, which is the first metal in contact with the wafer, reacts with the silicon carbide portion to form an alloy (nickel silicide), and the second metal in contact with the wafer also reacts with the silicon carbide portion. Thus, an alloy (each metal silicide) is formed. In the present embodiment, the first metal particles 21P in direct contact with the semiconductor layer 20 react with the semiconductor layer 20 to form the first alloy 9a, and the second metal particles in direct contact with the semiconductor layer 20 are formed. The particles 22P react with the semiconductor layer 20 to generate the second alloy 9b, and the composite alloy layer 9 in which the first alloy 9a and the second alloy 9b are mixed in the surface of the semiconductor layer 20 is formed. An alloy layer with the Ni film 31 is also formed on the surface (lower side in the figure) of the silicon carbide substrate 1.

  In the present embodiment, the first alloy 9a and the second alloy 9b only have to be mixed in the plane direction of the semiconductor layer 20, and each alloy is striped by changing the particle application conditions and the like. Alternatively, it may be dispersed in a grid pattern.

  Of the first alloy 9a, a portion formed in the n-type source region 4 portion of the first conductivity type forms an ohmic contact. And the part formed in the p-type contact region 5 part which is a 2nd conductivity type area | region among the said 2nd alloys 9b forms an ohmic contact. The alloy layer formed of the n-type silicon carbide substrate 1 and the first metal Ni film 31 forms an ohmic contact over the entire surface and functions as the drain electrode 11.

  Then, the wafer is washed with an acid such as sulfuric acid or phosphoric acid to remove the unreacted particles 21P and 22P that have not contacted the silicon carbide portion and have not been alloyed. Furthermore, a highly reliable ohmic contact can be formed by removing the graphite layer that precipitates with heat treatment by a dry process such as oxygen plasma.

  Finally, as a wiring layer forming step, the wiring layer 10 connected to the external circuit is formed on the upper portion of the wafer, and the back surface connecting wiring 12 is formed on the drain electrode 11 on the lower portion of the wafer, thereby obtaining the silicon carbide semiconductor device shown in FIG. It is done. In the present embodiment, since particles 22P are also used for the second metal, this is the same as in the first embodiment except that the unreacted metal film 22M does not remain in the obtained silicon carbide semiconductor device. .

  As described in the first embodiment, the remaining metal film 22M does not greatly affect the operation and effect of the silicon carbide semiconductor device. Therefore, the silicon carbide semiconductor device obtained by the manufacturing method of the second embodiment also operates in the same manner as the silicon carbide semiconductor device obtained by the manufacturing method of the first embodiment.

  That is, according to the present embodiment, the first metal capable of forming an ohmic contact with the n-type silicon carbide is directly n-type at the interface between the n-type source region 4 and the wiring layer 10 which are the first conductivity type. A second metal that is in contact with the source region 4 and can form an ohmic contact with p-type silicon carbide at the interface between the p-type contact region 5 and the wiring layer 10 of the second conductivity type is in direct contact with the p-type contact region. is doing. For this reason, the allowable ranges such as heat treatment conditions and alloy layer thickness for forming ohmic contacts are widened, the roughness of the surface state of the wafer processed in the actual process (roughness) and the residue state of contact inhibition films such as oxide films Even if there is a variation, uniform ohmic contact can be formed, so that stable low resistance can be realized, and yield and quality stability can be improved.

  In addition, since the ohmic contact between the wiring layer 10 connected to the external circuit and the first conductivity type region and the second conductivity type region can be formed by a common process, the unit element can be formed small and the device can be downsized. Becomes easy.

  In each of the above embodiments, the lower the contact resistance with the first conductivity type region and the second conductivity type region, the better. However, in an actual semiconductor device, the contribution of the resistance in each region may be different. Both resistances do not necessarily have the same low resistance. For example, in the MOSFET according to the present embodiment, the contact resistance to the source region 4 affects the loss at the time of conduction, so the effect when the contact resistance is reduced is great. On the other hand, the contact region 5 may be an ohmic contact that fixes the potential of the base region 3 to ground. In such a case, according to the present embodiment, the ratio of the area of the first alloy 9a and the area of the second alloy 9b is controlled, and the resistance between the source region 4 and the wiring layer 10 is preferentially reduced to be conductive. It becomes possible to reduce time loss more efficiently.

  In each of the above embodiments, an example in which n-type is used as the first conductivity type region and p-type is used as the second conductivity type region has been described. Conversely, p-type is used as the first conductivity type region and Even if n-type is used, the same effect can be obtained.

3 is a cross sectional view of a silicon carbide semiconductor device obtained by the manufacturing method of the first embodiment. FIG. 3 is a diagram showing a method for manufacturing the silicon carbide semiconductor device of the first embodiment. FIG. FIG. 6 is a cross sectional view of a silicon carbide semiconductor device obtained by the manufacturing method of Embodiment 2 It is a figure which shows the manufacturing method of the silicon carbide semiconductor device of Embodiment 2. FIG.

Explanation of symbols

1 silicon carbide semiconductor substrate, 2 drift region, 3 base region, 4 source region (first conductivity type), 5 contact region (second conductivity type), 9 composite alloy layer, 9a first alloy, 9b second alloy, 10 Wiring layer, 20 semiconductor layer, 21P first metal particles, 22M second metal film, 22P second metal particles,

Claims (6)

A method of manufacturing a silicon carbide semiconductor device having a semiconductor layer in which a first conductivity type region and a second conductivity type region are formed in a surface layer portion,
A first metal particle disposing step of disposing a first metal particle forming an ohmic contact with the first conductivity type region on the surface of the semiconductor layer with a gap therebetween;
A first metal alloying step of heat-treating at a predetermined temperature and reacting the first metal in contact with the semiconductor layer with the semiconductor layer to form a first alloy;
A second metal film forming step of forming, on the surface of the semiconductor layer, a second metal film that forms an ohmic contact with the second conductivity type region;
Heat treatment is performed at a predetermined temperature, the second metal in contact with the semiconductor layer is reacted with the semiconductor layer to form a second alloy, and the first alloy and the second alloy are mixed on the surface of the semiconductor layer. A composite alloy layer forming step of forming a composite alloy layer;
A method for manufacturing a silicon carbide semiconductor device comprising: A method of manufacturing a silicon carbide semiconductor device having a semiconductor layer in which a first conductivity type region and a second conductivity type region are formed in a surface layer portion,
A first metal particle disposing step of disposing a first metal particle forming an ohmic contact with the first conductivity type region on the surface of the semiconductor layer with a gap therebetween;
A second metal film forming step of forming, on the surface of the semiconductor layer, a second metal film that forms an ohmic contact with the second conductivity type region;
Heat-treating at a predetermined temperature, reacting the first metal in contact with the semiconductor layer with the semiconductor layer to form a first alloy, and reacting the second metal in contact with the semiconductor layer with the semiconductor layer. A composite alloy layer forming step of forming a second alloy and forming a composite alloy layer in which the first alloy and the second alloy are mixed on the surface of the semiconductor layer;
A method for manufacturing a silicon carbide semiconductor device comprising: A method of manufacturing a silicon carbide semiconductor device having a semiconductor layer in which a first conductivity type region and a second conductivity type region are formed in a surface layer portion,
A first metal particle that forms an ohmic contact with the first conductivity type region is disposed on the surface of the semiconductor layer with a gap therebetween, and a second metal that forms an ohmic contact with the second conductivity type region A metal particle disposing step of disposing the particles on the surface of the semiconductor layer;
Heat-treating at a predetermined temperature, reacting the first metal in contact with the semiconductor layer with the semiconductor layer to form a first alloy, and reacting the second metal in contact with the semiconductor layer with the semiconductor layer. A composite alloy layer forming step of forming a second alloy and forming a composite alloy layer in which the first alloy and the second alloy are mixed on the surface of the semiconductor layer;
A method for manufacturing a silicon carbide semiconductor device comprising: 4. The method according to claim 1, wherein the metal particle arranging step includes a step of applying a liquid in which the first metal particles are dispersed on the semiconductor layer and drying the liquid. A method for manufacturing the silicon carbide semiconductor device according to claim 1. When the first conductivity type region is n-type silicon carbide and the second conductivity type region is p-type silicon carbide, the first metal is Ni, and the second metal is any one of Al, Ti, and Co. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein: The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the predetermined temperature is in a range of 600 to 1200 ° C.

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