JP5028811B2 - Method for fabricating compound semiconductor optical device - Google Patents

Description

  The present invention relates to a method of manufacturing a compound semiconductor optical device.

Patent Document 1 describes a compound semiconductor etching method and a semiconductor laser device manufacturing method. According to this etching method, a vertical and smooth etching surface is provided in dry etching of a compound semiconductor. Specifically, a group III-V compound semiconductor or a group II-VI compound semiconductor includes a gas containing a halogen element in a dry etching apparatus including a plasma source that generates plasma having a density of about 10 ¹⁰ cm ⁻³ or more. Dry etching is performed by supplying a mixed gas with nitrogen gas. (Flow rate of gas containing halogen element) / (Flow rate of nitrogen gas) is 1 or more, and the pressure during the etching reaction is about 1 mTorr or 1 mTorr or more.

Non-Patent Document 1 describes a method for obtaining a mesa shape by dry etching in manufacturing a compound semiconductor device. Two methods have been described as methods for obtaining a mesa shape. In one method, a thin film mask made of an insulating film such as SiN or SiO ₂ having a thickness of 0.3 μm is used for dry etching. Another method uses a multilayer mask for dry etching. The multilayer mask includes, for example, a 1.5 μm thick resist (lower layer) cured by heat treatment at 200 to 300 ° C., and a 0.1 μm thick metal mask (intermediate layer) made of Ti or the like.
JP-A-9-283505 Semiconductor dry etching technology, industrial books, pages 155-158

In the etching method using the thin film mask described in Non-Patent Document 1, not only the semiconductor region is processed by etching but also the shape of the mask changes with the progress of etching. For this reason, the shape of the etched semiconductor region becomes a ridge shape with a skirt. In this etching, reactive ion etching (RIE) is performed using an insulating film such as SiN or SiO ₂ having a thickness of about 0.3 μm as an etching mask. In the RIE method, as etching progresses, it proceeds from an edge formed by the mask side surface and the mask upper surface (mask edge deformation). This deformation is caused by the sputter component and proceeds in an angle direction of 45 degrees from the edge of the upper part of the mask, thereby forming an inclined surface having an angle of about 135 degrees with the upper and side surfaces of the mask. The deformation of the mask proceeds at a disappearance rate that is 8 to 10 times the vertical etching rate. After the side surface disappears due to the deformation of the mask, the mask width decreases as the etching progresses (mask width receding). When the mask width is reduced during dry etching, the mesa side surface becomes skirted, and as a result, the mesa width increases as it approaches the substrate. Dry etching cannot be performed while maintaining the mesa etching angle substantially vertical. In other words, a step near a right angle cannot be formed by dry etching.

  Etching is performed using a composite mask of a hard mask having a thickness of about 1.5 μm and a metal mask such as Ti having a thickness of about 0.1 μm as an etching mask. In this method, the lower layer resist used as a mask is polymerized by etching and adheres to the side surface of the mesa. The attached polymer causes organic contamination in the buried epi growth process. The attached organic matter cannot be easily removed because it has undergone a high temperature baking step and a reactive ion etching step. Further, according to the inventor's knowledge, the attached organic matter causes deterioration of the embedded morphology. Therefore, this method cannot be used in a process where a clean surface with little contamination is required, for example, a process of forming a mesa including an active layer of a semiconductor laser by dry etching.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a method of manufacturing a compound semiconductor optical device that does not cause a large change in mask width during etching.

  One aspect of the present invention relates to a method of fabricating a compound semiconductor optical device. In this method, (a) a film forming gas containing an organosilane source material and an oxygen source material is supplied, and a dielectric mask film made of a silicon compound is deposited on the compound semiconductor region by inductively coupled plasma-chemical vapor deposition. (B) forming a dielectric mask by forming a pattern on the dielectric mask film; and (c) performing dry etching on the compound semiconductor region using the dielectric mask to increase the mesa height. Forming a mesa-shaped compound semiconductor region having a thickness h of 3.5 μm or more, and the dielectric mask is made of a single-layer silicon compound.

  According to the present invention, since the silicon compound for the dielectric mask is formed by inductively coupled plasma-chemical vapor deposition, a thick dielectric film having a thickness of, for example, 1 micrometer or more is formed. Obtainable. Since the compound semiconductor region is dry-etched using a thick dielectric mask, even if a deep mesa with a mesa height of 3.5 μm or more is processed, the mask width can be increased even if the mask edge disappears during etching. It will never get smaller. Therefore, a desired mesa-shaped compound semiconductor region can be formed.

In the method according to the present invention, the thickness H of the dielectric mask is between the mesa height h of the mesa-shaped processed compound semiconductor,
H ≧ h / 3
A dielectric mask film satisfying the above relationship is formed.

According to the present invention, as the dry etching progresses in the step of forming the mesa-shaped compound semiconductor region, the dielectric mask recedes from the edge of the upper surface of the mask, and the side surface of the mask accompanies the receding. Even when the height _HM is small, a mesa shape having a large etching amount and a high etching amount can be produced.

  In the method according to the present invention, it is preferable that the organosilane-based material includes TEOS (tetraethoxysilane), the oxygen material includes oxygen molecules, and the dielectric mask material includes silicon oxide.

  According to this method, even if the film thickness is increased, silicon oxide having a small stress in the film can be formed for the dielectric mask.

  In the method according to the present invention, the dry etching gas preferably contains a hydrocarbon. According to this method, the compound semiconductor can be dry-etched, and a desired mesa-shaped compound semiconductor region can be formed.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, a method for producing a compound semiconductor optical device that does not cause a large change in mask width during etching is provided.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, an embodiment relating to a method for producing a compound semiconductor optical device of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

  FIG. 1A is a schematic view showing a crystal growth step in a method for producing a compound semiconductor optical device. A substrate 11 having a surface 11a made of an InP semiconductor is prepared. The substrate 11 exhibits conductivity, and can be made of, for example, an n-type InP semiconductor. An active region 13 made of a III-V compound semiconductor is grown on the substrate 11. The active region 13 can have a structure such as a bulk structure, a single quantum well structure, or a multiple quantum well structure, for example. Next, a III-V compound semiconductor film 15 is grown on the active region 13. The III-V compound semiconductor film 15 can be made of, for example, a p-type InP semiconductor. The growth of the active region 13 and the III-V compound semiconductor film 15 is performed using, for example, a metal organic vapor phase growth furnace.

FIG. 1B is a drawing showing a mask manufacturing process for forming a multilayer structure for a dielectric mask and a dielectric mask film. A dielectric mask film 17 is formed on the III-V compound semiconductor film 15. The dielectric mask film 17 is formed using an inductively coupled plasma vapor deposition (ICP-CVD) apparatus by supplying a film forming gas containing an organosilane-based material and an oxygen material. Preferably, the dielectric mask film 17 is made of a silicon compound, and the silicon compound can contain, for example, silicon oxide. The thickness H _FILM of the dielectric mask film 17 is 1 micrometer or more. Next, a pattern is formed on the dielectric mask film 17 to form a dielectric mask. For example, TEOS or the like can be used as the organic silane-based material, and O ₂ or the like can be used as the oxygen material.

Since an SiN film by plasma enhanced vapor deposition (PE-CVD) using a silane-based gas such as SiH ₄ and an SiO ₂ film by thermal vapor deposition (thermal CVD) cannot be stress-controlled, the films It is impossible to increase the thickness. Cracks occur in the thick SiN film and SiO ₂ film. However, since the dielectric mask film 17 is formed using an ICP-CVD apparatus, the stress of the film can be controlled. Therefore, for example, a thick mask film having a thickness of 1 micrometer or more can be used. The mask film capable of controlling the stress is a silicon oxide film that can be formed by an ICP-CVD method using an organic silane-based material such as TEOS. Therefore, no contamination occurs in the production of the semiconductor device.

  An example for forming this dielectric mask will be described. First, a first etching mask material 19 is formed on the dielectric mask film 17. In a preferred example, the first etchant 19 can have a multilayer structure 21. The multilayer structure 21 includes first to third layers. The first layer is, for example, a cured resist film 23. Specifically, the cured resist film 23 is formed at a temperature of 100 degrees Celsius or higher after applying a resist to form a resist film of 1 micrometer or more. It is formed by heat treatment. The second film is, for example, a silicon compound film 25, a metal film such as Ti or Cr, specifically a metal thin film that can be formed at a low temperature such as sputtering, and more specifically, 0.1 micron by spin coating. A silicon oxide thin film of about a meter is formed. The third film 27 is, for example, a photosensitive resist film. Specifically, the third film 27 is formed by applying a photosensitive resist on the silicon compound film 25.

  FIG. 2A illustrates a step of forming a resist mask using a photolithography method. After exposing the photosensitive resist film 27 using an optical mask for a compound semiconductor optical device, the exposed resist film is developed. Referring to FIG. 2A, a resist mask 27a is formed by photolithography. In this embodiment, a mask having a pattern for producing a mesa stripe of a semiconductor laser is formed.

As shown in FIG. 2B, the silicon oxide thin film is etched using the resist mask 27a to form a silicon oxide mask 25a. In this embodiment, this etching is performed using, for example, an RIE etching apparatus. For example, CF ₄ gas can be used as the etching gas. Thereby, a sufficient selectivity can be maintained during etching. As a result, a silicon oxide mask 25a to which a pattern for producing a mesa stripe is transferred is obtained. Thereafter, the resist mask 27a is removed. This removal is performed by, for example, plasma ashing using O ₂ gas.

FIG. 3A is a diagram illustrating a process of forming a cured resist mask using a silicon oxide mask. The cured resist film 23 is etched using the silicon oxide mask 25a to form a cured resist mask 23a. In this embodiment, this etching is performed using, for example, an RIE etching apparatus. As the etching gas, for example, O ₂ gas can be used. Thereby, a sufficient selection ratio can be maintained. As a result, a cured resist mask 23a to which a pattern for producing a mesa stripe is transferred is obtained. Thereafter, the silicon oxide mask 25a is removed. This removal is performed by, for example, RIE etching using CHF ₃ gas.

FIG. 3B is a drawing showing a process of forming a dielectric mask by forming a pattern on the dielectric mask film. The dielectric mask film 17 is etched using the cured resist mask 23a. In this embodiment, this etching is performed using, for example, an RIE etching apparatus. For example, CHF ₃ gas can be used as the etching gas. Thereby, a sufficient selection ratio can be maintained. As a result, the dielectric mask 17a to which the pattern for producing the mesa stripe is transferred is obtained. The thickness H _MASK of the dielectric mask 17a is 1 micrometer or more. Thereafter, the cured resist mask 23a is removed. This removal is performed by, for example, an RIE etching apparatus using O ₂ gas. The resist mask 27a and the silicon oxide mask 25a can be removed at the same time when the cured resist mask 23a is removed. Therefore, the resist mask 27a is removed, and the silicon oxide mask is removed. The removal process of 25a can also be omitted.

  When a photosensitive resist mask is formed directly on the dielectric mask film, the cross-sectional shape of the stripe pattern of the photosensitive resist mask becomes a trapezoid. An error in the accuracy of the width of the transferred stripe pattern increases. When a three-layer mask is used, the cross-sectional shape of the stripe pattern of the photosensitive resist mask becomes rectangular, and when reactive ion etching is used, the pattern transfer accuracy can be improved.

4A and 4B are diagrams illustrating a process of forming a mesa-shaped compound semiconductor region by performing dry etching of the compound semiconductor region using a dielectric mask. Using the dielectric mask 17a, the compound semiconductor regions 15, 13, and 11 are dry etched. In this embodiment, this etching is performed using, for example, an ECR-RIE etching apparatus. As the etching gas, for example, a hydrocarbon such as CH ₄ gas can be used, and hydrogen can be added if necessary. An example of the ECR-RIE etching conditions at this time is as follows:
ECR high frequency power: 50-300 (W)
Bias power: 50 to 300 (W)
Etching pressure: 0.5-5 (Pa)
CH ₄ gas flow rate: 20 to 50 (sccm)
H ₂ gas flow rate: 0 to 50 (sccm)
It is.

  Referring to FIG. 4A, the etching of the III-V compound semiconductor film 15 in the compound semiconductor region 10 proceeds, and the etched III-V compound semiconductor film 15a is formed. During the progress of this etching, the edges 18a and 18b of the dielectric mask 17 shown in FIG. That is, during etching, not only the semiconductor regions 11, 13, and 15 are processed by etching, but also the shape of the dielectric mask 17 changes with the progress of etching. In this ECR-RIE method, as shown in FIG. 5A, deformation progresses from the mask edges 18a and 18b as etching progresses. This deformation is caused by the sputter component, and the deformation of the dielectric mask proceeds at a rate of 8 to 10 times the vertical etching rate. The deformation of the mask proceeds in an angular direction of approximately 45 degrees from the edge of the upper part of the mask, thereby forming inclined surfaces 18c and 18d that form an angle of approximately 135 degrees with the upper and side surfaces of the mask.

On the other hand, if the SiN film by the PE-CVD method and the SiO ₂ film by the thermal CVD method are thickened, cracks occur, so that a thick mask film cannot be obtained. Even in the etching method using the dielectric mask 20 formed from these films, not only the semiconductor region is processed by etching during etching, but also the shape of the mask changes with the progress of etching. In this etching, an RIE method is used using an insulating film such as SiN or SiO ₂ having a thickness of about 0.3 μm as an etching mask. In the RIE method, as etching progresses, it proceeds from edges 20a and 20b composed of a mask side surface and a mask upper surface (mask edge deformation). As shown in FIG. 5B, this deformation is caused by the sputter component and proceeds in an angle direction of 45 degrees from the edge of the upper part of the mask, thereby forming an inclined surface 20c that forms an angle of about 135 degrees with the upper and side surfaces of the mask. 20d is formed. The deformation of the mask proceeds at a disappearance rate that is 8 to 10 times the vertical etching rate. The inclined surface 20e and side surface is lost by deformation of the mask, the 20f is formed, the mask width W _S with the progress of etching is reduced (recession mask width). When the mask width is reduced during dry etching, the mesa side surface becomes skirted, and as a result, the mesa width becomes narrower as it approaches the top of the mesa. For this reason, as shown in FIG. 6B, the shape of the etched semiconductor region 12 becomes a ridge shape with a skirt. Therefore, dry etching cannot be performed while maintaining the mesa etching angle vertical. In other words, a step near a right angle cannot be formed by dry etching.

Referring to FIG. 4B, the etching of the III-V compound semiconductor films 15a, 13, and 11 in the compound semiconductor region 10 is completed, and the etched III-V compound semiconductor regions 15b, 13b, and 11b are formed. . On the other hand, the dielectric mask 17b is deformed by etching to become the dielectric mask 17c. However, since the dielectric mask 17a is thick, the mask width does not decrease (the mask width recedes) as the etching progresses. For this reason, the shape of the semiconductor regions 11b, 13b, and 15b becomes a ridge shape etched almost vertically. Therefore, dry etching can be performed while maintaining the mesa etching angle vertical. That is, as shown in FIG. 6A, as the etching progresses 10a, 10b, and 10c, the dielectric masks disappear and the inclined surfaces 18c and 18d are deformed into the inclined surfaces 18e and 18f. However, since the bottom of the width W _B of the dielectric mask is not substantially changed, it forms a step closer to a right angle by dry etching. As already described, since the dielectric mask 17a is thick, the mask width does not decrease (the mask width recedes) as the etching progresses. Therefore, dry etching can be performed while maintaining the mesa etching angle vertical. That is, a step close to a right angle can be formed by dry etching.

  Subsequently, a method for producing a compound semiconductor optical device will be described. FIG. 7A is a drawing showing a buried regrowth step in a method of manufacturing a compound semiconductor optical device. Also in this step, the dielectric mask 17c is left without being removed. A current blocking region 29 is grown on the semiconductor region 10c etched using the dielectric mask 17c. The compound semiconductor is not deposited on the mesa provided with the dielectric mask 17c. The current blocking region 29 can be made of, for example, iron-doped InP, or a p-type InP layer and an n-type InP layer. The growth of the current block region 29 is performed using, for example, a metal organic chemical vapor deposition furnace. After the current block region 29 is formed, the dielectric mask 17c is removed.

  FIG. 7B is a drawing showing a crystal growth step in a method for manufacturing a compound semiconductor optical device. A p-type III-V compound semiconductor film 31 and a p-type III-V compound semiconductor contact film 33 are grown on the mesa and the current block region 29 in the semiconductor region 10c. After these steps, an anode electrode and a cathode electrode are formed. This explained the main steps of the method of fabricating a compound semiconductor optical device.

An example of a compound semiconductor optical device such as a buried semiconductor laser is substrate 11: n-type InP substrate n-type III-V compound semiconductor film 13: Si-doped InP (n-type cladding)
Active region 15: buried region of quantum well structure 29 made of InGaAsP: Fe-doped InP (current block)
p-type III-V compound semiconductor film 31: Zn-doped InP (p-type cladding)
p-type III-V compound semiconductor contact film 33: Zn-doped InGaAs
It is.

In the method according to the present embodiment, during the etching for forming the mesa-shaped compound semiconductor region, the dielectric mask 17 gradually recedes from the edges 18a and 18b on the upper surface of the mask 17, and the receding with, as shown in FIG. 5 (a) and FIG. 6 (a), the height H _M of the side surface of the mask gradually decreases. For the height H _M of the side surface at the time of dry etching termination does not become zero or less, the thickness H of the dielectric mask 17,
H ≧ h / 3
It is preferable to satisfy the relationship. According to this method, a mesa shape with a large etching amount can be produced. For example, when the height of the dielectric mask made of SiO ₂ is about 1 μm, the InP semiconductor can be etched to a depth of about 3.5 μm while maintaining the mesa side surface perpendicularity. The thickness H of the dielectric mask is preferably about three times the depth h of the mesa to be produced by etching. This eliminates the lateral mask reduction during dry etching, so that a mesa having a vertical etching side surface can be produced. Further, since the mask reduction in the horizontal direction can be prevented, an etching shape according to the mask width can be realized, and the controllability of the etching width is improved.

  As described above, according to the etching method according to the present embodiment, since the silicon compound for the dielectric mask 17a is formed by inductively coupled plasma-chemical vapor deposition, 1 micron due to low stress. A dielectric mask 17a having a thickness of at least meters can be obtained. Since the compound semiconductor region is dry etched using the thick dielectric mask 17a, the mask width is not reduced even if the mask edge disappears during the etching. Therefore, a desired mesa-shaped compound semiconductor region can be formed. A low-stress and thick dielectric mask film is obtained, for example, by supplying a TEOS raw material to a plasma CVD apparatus using ICP discharge and depositing silicon oxide while applying a bias on a heated substrate. It is done.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. In the present embodiment, for example, a method of manufacturing a compound semiconductor optical device such as a buried semiconductor laser has been described. However, the present invention is not limited to the specific configuration disclosed in the present embodiment. In the present embodiment, an InP embedded semiconductor laser using an InP semiconductor as a substrate has been described as an example, but a GaAs embedded semiconductor laser using a GaAs semiconductor as a substrate can also be used. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

FIG. 1A is a schematic view showing a crystal growth step in a method for producing a compound semiconductor optical device. FIG. 1B is a drawing showing a mask manufacturing process for forming a multilayer structure for a dielectric mask and a dielectric mask film. FIG. 2A illustrates a step of forming a resist mask using a photolithography method. FIG. 2B is a diagram illustrating a process of forming a silicon oxide mask using a resist mask. FIG. 3A is a diagram illustrating a process of forming a cured resist mask using a silicon oxide mask. FIG. 3B is a drawing showing a process of forming a dielectric mask by forming a pattern on the dielectric mask film. 4A and 4B are diagrams illustrating a process of forming a mesa-shaped compound semiconductor region by performing dry etching of the compound semiconductor region using a dielectric mask. FIG. 5A is a schematic diagram showing a deformation of the dielectric mask in the present embodiment. FIG. 5B is a schematic diagram showing deformation of a dielectric mask using a dielectric film formed by PE-CVD or thermal CVD. FIG. 6A is a schematic diagram showing etching using a dielectric mask in the present embodiment. FIG. 6B is a schematic diagram showing etching using a dielectric mask using a dielectric film formed by PE-CVD or thermal CVD. FIG. 7A is a drawing showing a buried regrowth step in a method of manufacturing a compound semiconductor optical device. FIG. 7B is a drawing showing a crystal growth step in a method for manufacturing a compound semiconductor optical device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Substrate, 10 ... Compound semiconductor region, 10a, 10b, 10c ... Etched compound semiconductor region, 11a ... InP semiconductor surface, 11b ... III-V compound semiconductor region, 13 ... Active region, 13b ... III-V compound semiconductor 15 ... III-V compound semiconductor film, 15a ... III-V compound semiconductor film, 15b ... III-V compound semiconductor film, 17 ... dielectric mask film, 17a ... dielectric mask, 17b, 17c ... deformed dielectric Body mask, H _FILM ... dielectric mask film thickness, H _MASK ... dielectric mask thickness, 19 ... first etching mask material, 21 ... multilayer structure, 23 ... cured resist film, 23a ... cured resist mask, 25 ... Silicon compound film, 25a ... silicon oxide mask, 27 ... photosensitive resist film, 27a ... resist mask, 18a, 18b ... dielectric Mask edge, 18c, 18d ... mask inclined surface, 18e, 18f ... mask inclined surface, 10 ... compound semiconductor region, 29 ... current blocking region, 31 ... p-type III-V compound semiconductor film, 33 ... p-type III-V compound Semiconductor contact film

Claims (4)

A method for producing a compound semiconductor optical device, comprising:
Forming a compound semiconductor region including an active region made of a III-V compound semiconductor on a substrate;
Depositing by chemical vapor deposition, - an organic silane material and the film forming gas containing an oxygen source are supplied inductively coupled plasma dielectric mask film made of a silicon compound to the compound semiconductor region
Forming a dielectric mask by forming a pattern on the dielectric mask film;
Using the dielectric mask to dry-etch the compound semiconductor region to form a mesa-shaped compound semiconductor region having a mesa height h of 3.5 μm or more,
The dry etching is RIE etching using a mixed gas of hydrocarbon and hydrogen by supplying bias power.
The dielectric mask film satisfies the relationship H ≧ h / 3 between the thickness H of the dielectric mask and the mesa height h of the compound semiconductor after the step of forming the mesa-shaped compound semiconductor region. And
In the etching, the deformation of the mask edge due to the side surface and the upper surface of the dielectric mask is caused by the sputter component of the etching, and an inclined surface is formed on the mask edge,
The dielectric mask is made of a single layer of silicon compound. The bias power is 50 to 300 W,
The method according to claim 1, wherein the RIE etching is an ECR-RIE etching . The organosilane material includes TEOS,
The oxygen source contains oxygen molecules;
The method according to claim 1, wherein the material of the dielectric mask is made of silicon oxide. The hydrocarbon includes CH _4, the method according to any one of claims 1 to 3.

Images