JP5076713B2 - Method for fabricating compound semiconductor optical device - Google Patents

Description

  The present invention relates to a method of manufacturing a compound semiconductor optical device.

Patent Document 1 describes a method of forming a vertical and smooth etching surface in dry etching of a compound semiconductor. This etching method uses a SiO ₂ mask with a dry etching apparatus equipped with a plasma source that generates plasma having a density of about 10 ¹⁰ cm ⁻³ or more, using a mixed gas of a halogen element-containing gas and nitrogen gas, The III-V compound semiconductor is dry etched. In the etching method, (flow rate of gas containing halogen element) / (flow rate of nitrogen gas) ≧ 1, and the pressure during the etching reaction is about 1 mTorr or 1 mTorr or more.
JP-A-9-283505

  When a dielectric (for example, silicon oxide) for a dielectric mask is formed on a lower semiconductor film with an organic silane-based material (for example, TEOS) by a vapor phase growth apparatus, special temperature control is performed for the substrate temperature. Since the deposition for the dielectric mask is sufficiently possible without it, the dielectric has been deposited at room temperature.

  The mask may not be completely removed by a normal mask removing method (for example, hydrofluoric acid-based wet etching), and remains as a residue after the dielectric mask is removed. Even if the substrate is not heated during the deposition of the mask film, the substrate is heated to some extent by the heat generated in the plasma generation. For this reason, the residue was considered to have almost no influence on the performance of the semiconductor optical device. In the removal process, the residue remains that is not removed but should be dissolved and decomposed if the original mask component alone.

According to the study by the inventors, the organosilane-based raw material (for example, TEOS) is partially unreacted on the substrate only by heating with heat from plasma. The unreacted organic silane-based raw material is not completely consumed due to the generation of CO ₂ , CO, O _2, etc. during the formation of the dielectric mask (for example, silicon oxide), and most of it is released by exhaust. However, a small amount of raw material remains on the substrate and is adsorbed. The remaining carbon and oxygen bonds in the remaining raw material are bonded to the substrate material, and a substrate component, carbide, and oxide are generated.

  Although these carbides and oxides are in very small amounts, they may cause poor conduction and poor light emission when the final device form is reached. However, in high-performance devices with low resistance and high operating speed, these are performance factors. The effect of demonstrating is no longer negligible.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a method for producing a compound semiconductor optical device capable of reducing residues in removing a dielectric mask.

  One aspect of the present invention is a method of making a compound semiconductor optical device. This method includes (a) a step of forming a compound semiconductor region on a substrate, and (b) inductively coupling a dielectric mask film made of a silicon compound on the compound semiconductor region while heating the substrate using a heater. Depositing by plasma-chemical vapor deposition, (c) forming a dielectric mask by forming a pattern on the dielectric mask film, and (d) using the dielectric mask, the compound Performing a dry etching of the semiconductor region to form a mesa compound semiconductor region; and (e) removing the dielectric mask after the dry etching, wherein the dielectric mask film is an organosilane The dielectric mask is made of a single-layer silicon compound, and is performed by supplying a film forming gas containing a raw material and an oxygen raw material.

  According to this method, during deposition by inductively coupled plasma-chemical vapor deposition, a dielectric mask film made of a silicon compound is formed while heating the substrate using a heater as well as by heating with plasma. Therefore, consumption of the organosilane-based raw material is promoted, and as a result, the residue is reduced.

  In the method according to the present invention, it is preferable that the dielectric mask film is deposited at a temperature of 200 degrees Celsius or more. According to this method, a mask film capable of reducing the generation of residues can be formed.

  In the method according to the present invention, the deposition of the dielectric mask film can be performed at a temperature exceeding 250 degrees Celsius. If the temperature exceeds 250 degrees Celsius, substantially no residue is produced. If the temperature is 280 degrees Celsius or higher, the residue is zero.

  In the method according to the present invention, the dielectric mask film is preferably deposited at a temperature of 300 degrees Celsius or less. If the temperature is 300 degrees Celsius or lower, alteration of the compound semiconductor region can be avoided.

  In the method according to the present invention, the organosilane-based material may include TEOS, the oxygen material may include oxygen molecules, and the dielectric mask material may be made of silicon oxide. According to this method, even if the film thickness is increased, silicon oxide having a small stress in the film can be formed for the dielectric mask.

  In the method according to the present invention, the dry etching gas may include a hydrocarbon. According to this method, the compound semiconductor can be dry-etched, and a desired mesa-shaped compound semiconductor region can be formed.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, there is provided a method for manufacturing a compound semiconductor optical device capable of reducing a residue in removing a dielectric mask.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, an embodiment relating to a method for producing a compound semiconductor optical device of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

  FIG. 1A is a schematic view showing a crystal growth step in a method for producing a compound semiconductor optical device. A substrate 11 having a surface 11a made of an InP semiconductor is prepared. The substrate 11 exhibits conductivity, and can be made of, for example, an n-type InP semiconductor. An active region 13 made of a III-V compound semiconductor is grown on the substrate 11. The active region 13 can have a structure such as a bulk structure, a single quantum well structure, or a multiple quantum well structure, for example. Next, an III-V compound semiconductor film 15 is grown on the active region 13 to form an epitaxial wafer E1. The III-V compound semiconductor film 15 can be made of, for example, a p-type InP semiconductor. The growth of the active region 13 and the III-V compound semiconductor film 15 is performed using, for example, a metal organic vapor phase growth furnace.

FIG. 1B is a drawing showing a mask manufacturing process for forming a dielectric mask film. A dielectric mask film 17 is formed on the III-V compound semiconductor film 15. The dielectric mask film 17 is formed using an inductively coupled plasma vapor deposition (ICP-CVD) apparatus by supplying a film forming gas containing an organosilane-based material and an oxygen material. Preferably, the dielectric mask film 17 is made of a silicon compound, and the silicon compound can contain, for example, silicon oxide. The thickness H _FILM of the dielectric mask film 17 is 1 micrometer or more. Next, a pattern is formed on the dielectric mask film 17 to form a dielectric mask. For example, TEOS or the like can be used as the organic silane-based material, and O ₂ or the like can be used as the oxygen material.

As shown in FIG. 1B, an epitaxial wafer E1 is mounted on the stage of the ICP-CVD apparatus. The stage 1 has a heater 3 for adjusting the temperature of the substrate. Since the SiN film by plasma enhanced vapor deposition (PE-CVD) using a silane-based gas such as SiH ₄ and the SiO 2 film by thermal vapor deposition (thermal CVD) cannot be stress-controlled, It is impossible to increase the thickness. Cracks occur in the thick SiN film and SiO ₂ film. However, since the dielectric mask film 17 is formed using an ICP-CVD apparatus, the stress of the film can be controlled. Therefore, for example, a thick mask film having a thickness of 1 micrometer or more can be used. The mask film capable of controlling the stress is a silicon oxide film that can be formed by an ICP-CVD method using an organic silane-based material such as TEOS. Therefore, no contamination occurs in the production of the semiconductor device.

  As already described, the dielectric mask film 17 is deposited on the compound semiconductor region while heating the substrate 11 using a heater. In the deposition by inductively coupled plasma-chemical vapor deposition method, the dielectric mask film 17 made of a silicon compound is formed while heating the substrate 11 using a heater as well as by heating with plasma. The consumption of the system raw material is promoted, and as a result, the residue is reduced.

  As shown below, the dielectric mask film 17 is preferably deposited at a substrate temperature of 200 degrees Celsius or higher. According to this method, a mask film capable of reducing the generation of residues can be formed. Further, when the temperature exceeds 250 degrees Celsius, no residue is substantially generated, and when the temperature is 280 degrees Celsius or higher, no residue is observed. Further, the deposition of the dielectric mask film 17 is preferably performed at a temperature of 300 degrees Celsius or less. When the dielectric mask 17 is deposited at a temperature of 300 degrees Celsius or higher, the film stress increases due to thermal deformation of the dielectric film, resulting in distortion, cracks in the dielectric mask, or peeling of the dielectric mask. Occurs. If the temperature is not more than 300 degrees Celsius, alteration of certain compound semiconductor regions can be avoided. For example, when the compound semiconductor region contains phosphorus as a group III, if the temperature is not higher than 300 degrees Celsius, even in the compound semiconductor region containing phosphorus as a group V element, phosphorus removal hardly occurs.

The result of the composition ratio (C, O) analysis of the residue after removing the substrate temperature and the mask is shown. The presence or absence of residue was determined using a scanning electron microscope. Further, the chemical analysis used the μ Auger method. The contents of carbon (C) and oxygen (O) in the residue were analyzed.
Substrate temperature during mask formation Carbon Oxygen Residue presence 25 degrees Celsius 15% 9% Yes 100 degrees Celsius 10% 4% Yes 200 degrees Celsius 5% 3% None Level that does not affect semiconductor performance 250 degrees Celsius 1% 1% None Semiconductor Level that does not affect performance 280 degrees Celsius 0% 0% None Level that does not affect semiconductor performance 300 degrees Celsius 0% 0% None This is a level that does not affect semiconductor performance. At a temperature exceeding 300 degrees Celsius, when a semiconductor surface containing phosphorus (P) as a group III is exposed when depositing a mask film, surface roughness (fine holes) is observed on the semiconductor surface. .

  FIG. 2B is a drawing showing a mask manufacturing process for forming a multilayer structure for a dielectric mask and a dielectric mask film. An example for forming this dielectric mask will be described. First, a first etching mask material 19 is formed on the dielectric mask film 17. In a preferred example, the first etchant 19 can have a multilayer structure 21. The multilayer structure 21 includes first to third layers. The first layer is, for example, a cured resist film 23. Specifically, the cured resist film 23 is formed at a temperature of 100 degrees Celsius or higher after applying a resist to form a resist film of 1 micrometer or more. It is formed by heat treatment. The second film is, for example, a silicon compound film 25, a metal film such as Ti or Cr, specifically a metal thin film that can be formed at a low temperature such as sputtering, and more specifically, 0.1 micron by spin coating. A silicon oxide thin film of about a meter is formed. The third film 27 is, for example, a photosensitive resist film. Specifically, the third film 27 is formed by applying a photosensitive resist on the silicon compound film 25.

  FIG. 3A illustrates a step of forming a resist mask using a photolithography method. After exposing the photosensitive resist film 27 using an optical mask for a compound semiconductor optical device, the exposed resist film is developed. Referring to FIG. 3A, a resist mask 27a is formed by photolithography. In this embodiment, a mask having a pattern for producing a mesa stripe of a semiconductor laser is formed.

As shown in FIG. 3B, the silicon oxide thin film is etched using the resist mask 27a to produce a silicon oxide mask 25a. In this embodiment, this etching is performed using, for example, an RIE etching apparatus. For example, CF ₄ gas can be used as the etching gas. Thereby, a sufficient selectivity can be maintained during etching. As a result, a silicon oxide mask 25a to which a pattern for producing a mesa stripe is transferred is obtained. Thereafter, the resist mask 27a is removed. This removal is performed by, for example, plasma ashing using O ₂ gas.

FIG. 4A is a diagram illustrating a process of forming a cured resist mask using a silicon oxide mask. The cured resist film 23 is etched using the silicon oxide mask 25a to form a cured resist mask 23a. In this embodiment, the etching is performed using, for example, an RIE etching apparatus. As the etching gas, for example, O ₂ gas can be used. Thereby, a sufficient selection ratio can be maintained. As a result, a cured resist mask 23a to which a pattern for producing a mesa stripe is transferred is obtained. Thereafter, the silicon oxide mask 25a is removed. This removal is performed by, for example, RIE etching using CHF ₃ gas.

FIG. 4B is a drawing showing a process of forming a dielectric mask by forming a pattern on the dielectric mask film. The dielectric mask film 17 is etched using the cured resist mask 23a. In this embodiment, this etching is performed using, for example, an RIE etching apparatus. For example, CHF ₃ gas can be used as the etching gas. Thereby, a sufficient selection ratio can be maintained. As a result, the dielectric mask 17a to which the pattern for producing the mesa stripe is transferred is obtained. The thickness H _MASK of the dielectric mask 17a is 1 micrometer or more. Thereafter, the cured resist mask 23a is removed. This removal is performed by, for example, an RIE etching apparatus using O ₂ gas. The resist mask 27a and the silicon oxide mask 25a can be removed at the same time when the cured resist mask 23a is removed. Therefore, the resist mask 27a is removed, and the silicon oxide mask is removed. The removal process of 25a can also be omitted.

  When a photosensitive resist mask is formed directly on the dielectric mask film, the cross-sectional shape of the stripe pattern of the photosensitive resist mask becomes a trapezoid. An error in the accuracy of the width of the transferred stripe pattern increases. When a three-layer mask is used, the cross-sectional shape of the stripe pattern of the photosensitive resist mask becomes rectangular, and when reactive ion etching is used, the pattern transfer accuracy can be improved.

FIGS. 5A and 5B are diagrams illustrating a process of forming a mesa-shaped compound semiconductor region by performing dry etching of the compound semiconductor region using a dielectric mask. Using the dielectric mask 17a, the compound semiconductor regions 15, 13, and 11 are dry etched. In this embodiment, this etching is performed using, for example, an ECR-RIE etching apparatus. As the etching gas, for example, a hydrocarbon such as CH ₄ gas can be used, and hydrogen can be added if necessary. An example of the ECR-RIE etching conditions at this time is as follows:
ECR high frequency power: 50-300 (W)
Bias power: 50 to 300 (W)
Etching pressure: 0.5-5 (Pa)
CH ₄ gas flow rate: 20 to 50 (sccm)
H ₂ gas flow rate: 0 to 50 (sccm)
It is.

Referring to FIG. 5A, the etching of the III-V compound semiconductor film 15 in the compound semiconductor region 10 proceeds, and an etched III-V compound semiconductor film 15a is formed. During the progress of this etching, the edges 18a and 18b of the dielectric mask 17 shown in FIG. 4B disappear. That is, during etching, not only the semiconductor regions 11, 13, and 15 are processed by etching, but also the shape of the dielectric mask 17 changes with the progress of etching. In this ECR-RIE method, as shown in FIG. 6A, deformation progresses from the mask edges 18a and 18b as etching progresses. This deformation is caused by the sputter component, and the deformation of the dielectric mask proceeds at a rate of 8 to 10 times the vertical etching rate. The deformation of the mask proceeds in an angular direction of approximately 45 degrees from the edge of the upper part of the mask, thereby forming inclined surfaces 18c and 18d that form an angle of approximately 135 degrees with the upper and side surfaces of the mask.

On the other hand, if the SiN film by the PE-CVD method and the SiO2 film by the thermal CVD method are thickened, cracks occur, so that a thick mask film cannot be obtained. Even in the etching method using the dielectric mask 20 formed from these films, not only the semiconductor region is processed by etching during etching, but also the shape of the mask changes with the progress of etching. In this etching, an RIE method is used using an insulating film such as SiN or SiO ₂ having a thickness of about 0.3 μm as an etching mask. In the RIE method, as etching progresses, it proceeds from edges 20a and 20b composed of a mask side surface and a mask upper surface (mask edge deformation). As shown in FIG. 6B, this deformation is caused by the sputter component and proceeds in an angle direction of 45 degrees from the upper edge of the mask, thereby forming an inclined surface 20c that forms an angle of about 135 degrees with the upper and side surfaces of the mask. 20d is formed. The deformation of the mask proceeds at a disappearance rate that is 8 to 10 times the etching rate in the vertical direction. When the side surfaces disappear due to the deformation of the mask and the inclined surfaces 20e and 20f are formed, the mask width WS decreases as the etching progresses (retraction of the mask width). When the mask width is reduced during dry etching, the mesa side surface becomes skirted, and as a result, the mesa width becomes narrower as it approaches the top of the mesa. For this reason, as shown in FIG. 7B, the shape of the etched semiconductor region 12 becomes a ridge shape with a skirt. Therefore, dry etching cannot be performed while maintaining the mesa etching angle vertical. In other words, a step near a right angle cannot be formed by dry etching.

Referring to FIG. 5B, the etching of the III-V compound semiconductor films 15a, 13, 11 in the compound semiconductor region 10 is completed, and etched III-V compound semiconductor regions 15b, 13b, 11b are formed. . On the other hand, the dielectric mask 17b is deformed by etching to become the dielectric mask 17c. However, since the dielectric mask 17a is thick, the mask width does not decrease (the mask width recedes) as the etching progresses. For this reason, the shape of the semiconductor regions 11b, 13b, and 15b becomes a ridge shape etched almost vertically. Therefore, dry etching can be performed while maintaining the mesa etching angle vertical. In other words, as shown in FIG. 7A, as the etching progresses 10a, 10b, and 10c, the dielectric masks disappear and the inclined surfaces 18c and 18d are deformed into the inclined surfaces 18e and 18f. However, since the bottom of the width W _B of the dielectric mask is not substantially changed, it forms a step closer to a right angle by dry etching. As already described, since the dielectric mask 17a is thick, the mask width does not decrease (the mask width recedes) as the etching progresses. Therefore, dry etching can be performed while maintaining the mesa etching angle vertical. That is, a step close to a right angle can be formed by dry etching.

  Subsequently, a method for producing a compound semiconductor optical device will be described. FIG. 8A is a drawing showing a burying regrowth step in a method of manufacturing a compound semiconductor optical device. Also in this step, the dielectric mask 17c is left without being removed. A current blocking region 29 is grown on the semiconductor region 10c etched using the dielectric mask 17c. The compound semiconductor is not deposited on the mesa provided with the dielectric mask 17c. The current blocking region 29 can be made of, for example, iron-doped InP, or a p-type InP layer and an n-type InP layer. The growth of the current block region 29 is performed using, for example, a metal organic chemical vapor deposition furnace. After the current block region 29 is formed, the dielectric mask 17c is removed.

  FIG. 8B is a drawing showing a crystal growth step in a method for manufacturing a compound semiconductor optical device. A p-type III-V compound semiconductor film 31 and a p-type III-V compound semiconductor contact film 33 are grown on the mesa and the current block region 29 in the semiconductor region 10c. After these steps, an anode electrode and a cathode electrode are formed. This explained the main steps of the method of fabricating a compound semiconductor optical device.

An example of a compound semiconductor optical device such as a buried semiconductor laser is substrate 11: n-type InP substrate n-type III-V compound semiconductor film 13: Si-doped InP (n-type cladding)
Active region 15: buried region of quantum well structure 29 made of InGaAsP: Fe-doped InP (current block)
p-type III-V compound semiconductor film 31: Zn-doped InP (p-type cladding)
p-type III-V compound semiconductor contact film 33: Zn-doped InGaAs
It is.

In the method according to the present embodiment, during the etching for forming the mesa-shaped compound semiconductor region, the dielectric mask 17 gradually recedes from the edges 18a and 18b on the upper surface of the mask 17, and the receding with, as shown in FIG. 6 (a) and FIG. 7 (a), the height H _M of the side surface of the mask gradually decreases. For the height H _M of the side surface at the time of dry etching termination does not become zero or less, the thickness H of the dielectric mask 17,
H ≧ h / 3
It is preferable to satisfy the relationship. According to this method, a mesa shape with a large etching amount can be produced. For example, when the height of the dielectric mask made of SiO ₂ is about 1 μm, the InP semiconductor can be etched to a depth of about 3.5 μm while maintaining the mesa side surface perpendicularity. The thickness H of the dielectric mask is preferably about three times the depth h of the mesa to be produced by etching. This eliminates the lateral mask reduction during dry etching, so that a mesa having a vertical etching side surface can be produced. Further, since the mask reduction in the horizontal direction can be prevented, an etching shape according to the mask width can be realized, and the controllability of the etching width is improved.

  As described above, according to the etching method according to the present embodiment, when forming a dielectric mask with a vapor phase growth apparatus using an organic silane-based material, if the substrate temperature is heated, carbides and oxides on the substrate The residue by can be reduced. Therefore, no residue is observed after removal of the dielectric mask, as shown in FIG. Further, since the silicon compound for the dielectric mask 17a is formed by inductively coupled plasma-chemical vapor deposition, the dielectric mask 17a having a thickness of 1 micrometer or more can be obtained due to low stress. Since the compound semiconductor region is dry etched using the thick dielectric mask 17a, the mask width is not reduced even if the mask edge disappears during the etching. Therefore, a desired mesa-shaped compound semiconductor region can be formed. A low-stress and thick dielectric mask film is obtained, for example, by supplying a TEOS raw material to a plasma CVD apparatus using ICP discharge and depositing silicon oxide while applying a bias on a heated substrate. It is done.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. In the present embodiment, for example, a method of manufacturing a compound semiconductor optical device such as a buried semiconductor laser has been described. However, the present invention is not limited to the specific configuration disclosed in the present embodiment. In the present embodiment, an InP embedded semiconductor laser using an InP semiconductor as a substrate has been described as an example, but a GaAs embedded semiconductor laser using a GaAs semiconductor as a substrate can also be used. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

FIG. 1A is a schematic view showing a crystal growth step in a method for producing a compound semiconductor optical device. FIG. 1B is a drawing showing a mask manufacturing process for forming a dielectric mask film. FIG. 2A is a drawing showing a substrate product having a dielectric mask film formed in a mask manufacturing process. FIG. 2B is a drawing showing a mask manufacturing process for forming a multilayer structure for a dielectric mask. FIG. 3A illustrates a step of forming a resist mask using a photolithography method. FIG. 3B is a diagram illustrating a process of forming a silicon oxide mask using a resist mask. FIG. 4A is a diagram illustrating a process of forming a cured resist mask using a silicon oxide mask. FIG. 4B is a drawing showing a process of forming a dielectric mask by forming a pattern on the dielectric mask film. FIGS. 5A and 5B are diagrams illustrating a process of forming a mesa-shaped compound semiconductor region by performing dry etching of the compound semiconductor region using a dielectric mask. FIG. 6A is a schematic diagram showing deformation of the dielectric mask in the present embodiment. FIG. 6B is a schematic diagram showing deformation of a dielectric mask using a dielectric film formed by PE-CVD or thermal CVD. FIG. 7A is a schematic diagram showing etching using a dielectric mask in the present embodiment. FIG. 7B is a schematic diagram showing etching using a dielectric mask using a dielectric film formed by PE-CVD or thermal CVD. FIG. 8A is a drawing showing a burying regrowth step in a method of manufacturing a compound semiconductor optical device. FIG. 8B is a drawing showing a crystal growth step in a method for manufacturing a compound semiconductor optical device. FIG. 9 is a drawing schematically showing the semiconductor surface after removal of the dielectric mask in the method of manufacturing the compound semiconductor optical device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Stage, 3 ... Heater, 11 ... Substrate, 10 ... Compound semiconductor region, 10a, 10b, 10c ... Etched compound semiconductor region, 11a ... InP semiconductor surface, 11b ... III-V compound semiconductor region, 13 ... Active region , 13b ... III-V compound semiconductor region, 15 ... III-V compound semiconductor film, 15a ... III-V compound semiconductor film, 15b ... III-V compound semiconductor region, 17 ... dielectric mask film, 17a ... dielectric mask, 17b, 17c: Deformed dielectric mask, H _FILM : Dielectric mask film thickness, H _MASK : Dielectric mask thickness, 19 ... First etching mask material, 21 ... Multilayer structure, 23 ... Hardened resist film, 23a ... cured resist mask, 25 ... silicon compound film, 25a ... silicon oxide mask, 27 ... photosensitive resist film, 27a ... resist mass 18a, 18b ... Dielectric mask edge, 18c, 18d ... Mask inclined surface, 18e, 18f ... Mask inclined surface, 10 ... Compound semiconductor region, 29 ... Current blocking region, 31 ... P-type III-V compound semiconductor film, 33 ... p-type III-V compound semiconductor contact film

Claims (6)

A method for producing a compound semiconductor optical device, comprising:
Forming a compound semiconductor region on the InP substrate;
Depositing a dielectric mask film made of a silicon compound on the compound semiconductor region by inductively coupled plasma-chemical vapor deposition while heating the InP substrate using a heater;
Forming a dielectric mask by forming a pattern on the dielectric mask film;
Performing a dry etching of the compound semiconductor region using the dielectric mask to form a mesa compound semiconductor region;
A step of removing the dielectric mask after the dry etching;
The dielectric mask film is in contact with the compound semiconductor region,
The dielectric mask film is formed by supplying a film forming gas containing an organosilane-based material and an oxygen material, the organosilane-based material includes TEOS, the oxygen material includes oxygen molecules,
The dielectric mask is Ri Do a silicon compound of the monolayer, the material of the dielectric mask is made of silicon oxide,
The dielectric mask film is deposited at a temperature of 200 degrees Celsius or higher,
The method of depositing the dielectric mask film is performed at a temperature of 300 degrees Celsius or less . In the step of depositing the dielectric mask film on the compound semiconductor region by inductively coupled plasma-chemical vapor deposition, the organic silane-based material is adsorbed on the surface of the compound semiconductor region. Including a process of forming a carbide and oxide with a component of the compound semiconductor region,
In the step of depositing the dielectric mask film on the compound semiconductor region by inductively coupled plasma-chemical vapor deposition, forming the dielectric mask film made of silicon oxide while heating the substrate. 2. The method according to claim 1 , wherein generation of carbides and oxides with components of the compound semiconductor region is suppressed . The method according to claim 1 or 2, wherein the deposition of the dielectric mask film is performed at a temperature exceeding 250 degrees Celsius. Using said dielectric mask, further comprising the step of growing a current blocking layer on the mesa compound semiconductor region which has been dry-etched, as claimed in any one of claims 1 to 3, characterized in that Method. 5. The method according to claim 1 , further comprising a step of growing a III-V compound semiconductor layer on the mesa compound semiconductor region and the current blocking region after removing the dielectric mask. 6. Method.   The method according to claim 1, wherein the dry etching gas includes a hydrocarbon.

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