JP5027557B2 - Memory device for gaming machine - Google Patents

Description

  The present invention relates to a memory device for a gaming machine used in a gaming machine such as a pachinko gaming machine, a coin gaming machine, or a slot machine.

  In the above-described gaming machines, various improvements have been made to increase the interest of the player, and these improvements enable more complex operations by controlling various operations using a computer. . In recent years, video technology has been introduced to devise ways to further enhance the player's interest through the effect of using video.

  When performing an effect using a video, it is necessary to store a large amount of image data in advance, and thus a large-capacity storage device is required. As a large-capacity storage device, there are storage media such as HD and DVD, but in gaming machines, a nonvolatile memory with high security is used from the viewpoint of compactness of the device and countermeasures against unauthorized modification.

  In addition, various countermeasures have been proposed for the purpose of preventing unauthorized modification accompanying the digitization of gaming machines. For example, Patent Document 1 describes that unique identification information assigned to the gaming machine control means is stored in a security memory that is non-rewritable and nonvolatilely stored. Further, Patent Document 2 describes a gaming machine including an abnormality detection unit in which an output of an inspection ROM changes when an unused area of a memory unit that stores a control program for realizing a gaming operation is accessed. . Patent Document 3 describes a gaming machine control chip that uses a random number generation circuit to prevent unauthorized access.

On the other hand, examples of the non-volatile memory include mask ROM, EPROM, EEPROM, flash memory, and FRAM. However, in recent years, the capacity of flash memory has been increased, and the cost has been reduced by mass production. It is supposed to be. In addition, a flash memory that is packaged with a controller has been proposed (see Patent Documents 4 and 5).
JP 2001-87522 A JP 2002-253823 A JP 2003-299862 A JP 2006-309361 A Japanese Patent No. 3747213

  As a storage device used for gaming machines, it is preferable to use a flash memory with a large capacity and a low cost. However, since the flash memory is non-volatile, it can be rewritten so that it cannot be physically written. It is necessary to keep.

  There are two types of flash memory, NOR type and NAND type. As shown in FIG. 7, when the NOR flash memory 400 is connected to the microcomputer 300, the CE (CHIP ENABLE) terminal, the WE (WRITE ENABLE) terminal, the OE (OUTPUT ENABLE) terminal, the ADDR (ADDRESS) terminal, and the DATA Connect each terminal to the corresponding terminal.

  When data is read from the NOR flash memory 400, as shown in FIG. 8, a read command signal is input to the OE terminal, address data to be read is sent to the ADDR terminal, and the read data is sent from the DATA terminal. Receive.

  When writing data, a write command signal is input to the WE terminal, address data to be written to the ADDR terminal is transmitted, and the data to be written is transmitted to the DATA terminal. As shown in FIG. 7, the WE terminal of the NOR flash memory 400 is transmitted. If the power supply voltage Vcc is always applied to the pull-up state, writing to the NOR flash memory 400 can be prohibited.

  On the other hand, as shown in FIG. 9, when the NAND flash memory 500 is connected to the microcomputer 300, the CE terminal and the WE terminal are connected to the corresponding terminals, and the OE terminal of the microcomputer 300 is connected to the NAND flash memory 500. 2 of the ADDR terminals of the microcomputer 300 are connected to the CLE (COMMAND LATCH ENABLE) terminal and the ALE (ADDRESS LATCH ENABLE) terminal of the NAND flash memory 500, and the microcomputer 300 is connected to the RE (READ ENABLE) terminal of the microcomputer 300. The DATA terminal is connected to the I / O (INPUT / OUTPUT) terminal of the NAND flash memory 500.

  When data is read from the NAND flash memory 500, as shown in FIG. 10, a write command signal is input to the WE terminal, command data and address data are transmitted from the DATA terminal to the I / O terminal, and the ALE terminal. When the latch signal is input to the memory, command data and address data are stored in the NAND flash memory 500, and a read operation is performed in the memory. Next, a read signal is input from the OE terminal to the RE terminal, and the data read from the I / O terminal to the DATA terminal is output.

  The present invention relates to a memory for a gaming machine capable of providing sufficient security against unauthorized modification by prohibiting writing in a NAND flash memory that needs to receive a write command signal even during read processing. The object is to provide an apparatus.

  As described above, when used for a gaming machine, the NOR flash memory is easier to take measures against unauthorized modification, but the NOR flash memory needs to increase the ADDR terminal as the capacity increases. There is a demerit that the manufacturing cost is higher than that of the NAND type. In that respect, the NAND flash memory does not increase the number of terminals even if the capacity is increased, and the manufacturing cost can be kept low. Therefore, a large amount of image data that is expected to increase in the future development of gaming machines It is required to use a NAND flash memory as a memory for storing the memory.

A memory device for gaming machine according to the present invention is a NAND flash memory that stores information for controlling a gaming machine and information from the NAND flash memory based on a read command signal from a main body control circuit that controls the gaming machine. a gaming machine memory device and a controller for reading, the controller transmits the data read from the NAND type flash memory which receives the read command signal from the main control circuit to the main control circuit NAND type transmits the main body side interface unit, a buffer memory unit for storing data to be transmitted to the read command signal and the main body control circuit receives from the main control circuit, a NAND-type flash memory write command signal and read command signal Memory that transmits / receives data to / from flash memory An interface unit; a control unit that writes data to a block area that replaces the defective block area based on information on the defective block area in the NAND flash memory and creates an address management table that associates the defective block area with the alternative block area; An error correction circuit for detecting an error of data read from the NAND flash memory and correcting the detected error, and the control unit receives the read command from the main body control circuit via the main body side interface unit. Upon receiving an output signal for reading including command data and address data as signals, reads the address data of the block area corresponding to the address data received on the basis of the address management table, the memory side to the NAND-type flash memory The write command signal, the command data, and the read address data are transmitted via the interface unit, and the data read from the NAND flash memory via the memory side interface unit is stored in the buffer memory unit and read. The output data is checked for errors by the error correction circuit, and stored in the buffer memory unit based on the read command signal for the buffer memory unit received as the read command signal from the main unit control circuit via the main unit side interface unit The transmitted data is transmitted to the main body control circuit via the main body side interface section. Further, a predetermined voltage is constantly applied to the write command signal input terminal of the main body side interface section. Further, the NAND flash memory and the controller are packaged in one package.

  A gaming machine according to the present invention includes the above gaming machine memory device.

  The memory device for gaming machines according to the present invention has the above-described configuration, so that the NAND flash memory can be connected via the controller without inputting a write command signal from the main body control circuit as in the conventional NAND flash memory. Since data can be read from the memory, it becomes difficult to rewrite information by illegally accessing the memory. Therefore, it is possible to use a NAND memory that is inexpensive and easy to increase in capacity as a memory device for gaming machines.

  Since the read process is performed through the controller, it is possible to set arbitrary command data and set the controller to input a write command signal to the NAND flash memory in accordance with the command data. It is also possible to take measures to prevent unauthorized modification such as setting command data for each machine.

  Also, command data and address data can be input to the main body side interface unit as in the conventional NAND flash memory, and even if the capacity of the memory is increased, there is no need to increase the address terminals and the packaging can be made compactly. it can.

  Further, when a write command signal input terminal is provided in the main body side interface unit, writing can be reliably prohibited by always applying a predetermined voltage to the input terminal, for example, in a pull-up or pull-down state.

  Further, by making the NAND flash memory and the controller into one package, a more compact gaming machine memory device can be obtained. Here, the one-packaging means that one or a plurality of circuit systems are combined into one in terms of appearance and configuration. For example, one or a plurality of semiconductor elements cut out from a silicon wafer can be combined with ceramic or resin. The whole is sealed using a material such as, and can be mounted on a substrate or the like by a terminal connected to a semiconductor element.

  Hereinafter, embodiments according to the present invention will be described in detail. The embodiments described below are preferable specific examples for carrying out the present invention, and thus various technical limitations are made. However, the present invention is particularly limited in the following description. Unless otherwise specified, the present invention is not limited to these forms.

  FIG. 1 shows a front view of the entire pachinko gaming machine as an example of the gaming machine. A glass door 1 is provided on the front surface, and a glass plate 1b is fitted into the glass door frame 1a so that a game board to be described later can be seen. A game ball supply unit 2 is disposed below the glass door 1, and when a game ball supplied by winning overflows from the game ball supply unit 2, the game ball is further disposed below. It is moved to the receiving tray 3. The game ball supplied from the game ball supply unit 2 is fired by a launching device (not shown) by rotating the operation handle 4 and guided to the upper side of the game board through the launch path. A speaker 5 is attached in the vicinity of the upper part of the saucer 3, and sound effects such as voice and music are played according to the progress of the game, and various information is notified to excite the game.

  FIG. 2 shows the game board 10. An image display device 20 having a liquid crystal display panel is disposed at the approximate center of the game board 10, and an outer rail 30 and an inner rail 31 are disposed around the periphery.

  The outer rail 30 and the inner rail 31 are configured by a substantially arc-shaped guide plate and are installed at a predetermined interval, and the game balls launched by the launching device are guided upward by the outer rail 30 and the inner rail 31. And enter the gaming area. The game ball that has entered the game area rolls while being guided by a guide member such as a nail on the way. In the game area, a symbol start port 40, an opening / closing operation port 41, a normal winning port 42, and a big winning port 43 are arranged, and it is set so that various benefits can be obtained when a game ball passes through these winning ports. The The symbol start opening 40, the opening / closing operation opening 41 and the normal winning opening 42 are always open to accept game balls, but the large winning opening 43 is always closed by a shutter (not shown). When the lottery result is a big hit, the shutter is fully opened. A pair of movable members 44 that open and close to the left and right are provided at the entrance portion of the symbol start opening 40, and when the movable member 44 is in a closed state, the opening of the entrance portion becomes small, making it difficult for a game ball to enter. In the open state, the entrance portion is fully opened and the movable member 44 spreads the wings so that the game ball can easily enter the symbol starting port 40.

  When a game ball wins the symbol start opening 40, the variation of the symbol displayed on the liquid crystal display panel of the image display device 20 is started. The display area of the liquid crystal display panel is a 3 × 3 matrix display as a whole, and various benefits can be obtained by combinations of symbols stopped and displayed in the display area. For example, when the combination is a big hit after the symbols are stopped, the big winning opening 44 is opened, and the winning becomes very easy. The combination of symbols to be stopped and displayed is determined in advance by the lottery result of the internal lottery executed in the main control device of the gaming machine, and various effects are displayed based on the combination so as to excite the player's interest. It has become.

  In addition, when a game ball enters the symbol start opening 40 during the rotation display on the image display device 20, the number of game balls that are on the four holding lamps 21 arranged on the upper part of the image display device 20 are turned on. Thus, the symbol scroll display operation start can be repeated up to four times as an upper limit. On the other hand, when the game ball passes through the opening / closing operation port 41, the movable member 44 arranged at the entrance portion of the symbol start port 40 is opened to the left and right. Then, in order to notify that the movable member 44 is open, the circle of the open / close lamp 22 is turned on. In this way, it is possible to enhance the interest by transmitting various information to the player using the display device.

  FIG. 3 is a block diagram illustrating an example of a circuit configuration of the gaming machine described above. The circuit configuration is roughly divided into a main control device 100 that controls the progress of a game, an image display device 20, and an image display control device 200 that controls image display. Although not shown in the figure, a sound control device that performs output control of sound effects using the speaker 5 is provided separately. The main controller 100 includes a control unit 101, a switch circuit 102, a solenoid circuit 103, a ramp circuit 104, and an input / output port 105. The control unit 101 includes a CPU 110, a RAM 111, and a ROM 112, and performs overall control of gaming machines such as winning management, payout management, and production management. The switch circuit 102 transmits detection signals from the gate sensor 51 and the start port sensor 52 that detect that the game ball has passed through the winning opening, and the count sensor 53 and the V count sensor 54 related to winning, to the control unit 101. The solenoid circuit 103 transmits a drive signal in response to the control signal from the control unit 101 to the open / close solenoid 55 that drives the movable member 44 disposed at the entrance portion of the symbol start port 40. The lamp circuit 104 transmits a display signal in response to the control signal from the control unit 101 to the display lamp 56 such as the hold lamp 21, the open / close lamp 22, and the decoration lamp. The input / output port 105 transmits a control signal from the control unit 101 to an input / output port of another control device, receives a signal from another control device, and transmits the signal to the control unit 101. As shown in the figure, the input / output port 105 is only transmitted to the image display control device 200 and does not receive a signal from the image display control device 200.

  The image display control apparatus 200 includes a CPU 201, a program ROM 202, a RAM 203, an input port 204, an image processing circuit 205, an image ROM 206, a RAM 207, a screen dividing circuit 208, and an output port 209. The input port 204 receives a signal from the input / output port 105 and transmits it to the CPU 201. The CPU 201 reads an image control program, a motor control program, and the like stored in the program ROM 202, temporarily stores data and the like in the RAM 203 as necessary, and performs arithmetic processing. The image ROM 206 stores image data related to a plurality of types of symbols displayed on the image display device 20 and image data such as a person image and a background. The RAM 207 stores image display data displayed on the image display device 20. It is memorized at any time. The image display data in the RAM 207 is divided into image display data corresponding to the display area by the screen dividing circuit 208 and transmitted to the image display device 20 via the output port 208. The image processing circuit 205 smoothly advances processing such as reading of image data from the image ROM 206, reading and writing to the RAM 207, image processing in the image dividing circuit 208, and output to the output port 209 based on a control signal from the CPU 201. The image display data is transmitted to the image display device 20 and controlled to be displayed in each display area at an appropriate timing.

  In the control device shown in FIG. 3, for example, when the start port sensor 52 detects the passage of a game ball, the detection signal is transmitted to the control unit 101 via the switch circuit 102, and the control unit 101 starts symbol variation processing. . First, an internal lottery is performed based on the result of random number processing, and a win or a miss is determined. Then, a symbol to be stopped and displayed in the display area of the image display device 20 is determined from the random number processing result. In the case of a loss, a decision is made as to whether or not to produce an effect that will reach a reach state (a state where two of the symbols are aligned on the active line) or to use a probable variation symbol. It is determined. When items related to winning are determined, display control command data for performing image display processing corresponding to the items is transmitted to the image display control device 200 via the input / output port 105. Further, when it is determined that the winning combination is made, the special winning opening 43 is opened.

  FIG. 4 is a configuration diagram when the memory device according to the present invention is used in the ROM 112 of the main controller 100. A memory device 600 is connected to a microcomputer 300, which is a main body control circuit that performs control processing of the main control device 100, and the memory device 600 is configured by packaging a controller 601 and a NAND flash memory 602 in one package. Here, as the NAND flash memory 602, a conventionally known one is used.

  The microcomputer 300 includes a CE terminal, a WE terminal, an OE terminal, an ADDR terminal, and a DATA terminal, and the NAND flash memory 602 includes a CE terminal, a WE terminal, an RE terminal, a CLE terminal, an ALE terminal, and an I / O terminal. I have.

  The controller 601 is provided with an HCE (HOST CHIP ENABLE) terminal, an HWE (HOST WRITE ENABLE) terminal, an HOE (HOST OUTPUT ENABLE) terminal, an ADDR terminal, and a DATA terminal on the microcomputer side. The HCE terminal is a CE terminal of the microcomputer 300. The HOE terminal is connected to the OE terminal of the microcomputer 300, and the ADDR terminal and the DATA terminal are connected to the ADDR terminal and the DATA terminal of the microcomputer 300, respectively. The HWE terminal is set in a state where the power supply voltage Vcc is constantly applied and pulled up. Also, the memory side has FCE (FLASH CHIP ENABLE) terminal, FWE (FLASH WRITE ENABLE) terminal, FRE (FLASH READ ENABLE) terminal, CLE terminal, ALE terminal and I / O terminal, and FCE terminal is NAND type The CE terminal of the flash memory 602, the FWE terminal to the WE terminal of the NAND flash memory 602, the FRE terminal to the RE terminal of the NAND flash memory 602, the CLE terminal to the CLE terminal of the NAND flash memory 602, and the ALE terminal to The NAND flash memory 602 is connected to the ALE terminal and the I / O terminal is connected to the I / O terminal of the NAND flash memory 602.

  FIG. 5 is a block diagram of the controller 601. The controller 601 includes a main body side interface unit 603 that transmits / receives data to / from the microcomputer 300, a memory side interface unit 604 that transmits / receives data to / from the NAND flash memory 602, data received from the microcomputer 300, and transmission to the microcomputer 300 Read from the CPU 606, ROM 607 and RAM 608, and NAND flash memory 602, which are control units that perform data control processing of the controller 601 and management of defective blocks of the NAND flash memory 602. An error correction circuit 609 is provided for detecting an error in the output data and correcting the detected error.

  FIG. 6 is a timing chart when reading data from the memory device 600. An output signal from the CE terminal of the microcomputer 300 becomes LOW, a signal is output from the OE terminal at a predetermined timing, and signal sequences CMD0 and ADDR0 to 4 corresponding to command data and address data are output from the ADDR terminal in synchronization with the timing. , CMD1 is output. When the controller 601 receives these signal sequences, it outputs a signal sequence DUMMY corresponding to dummy data from the DATA terminal correspondingly. The microcomputer 300 does not use the dummy data received at the DATA terminal because it is not read data.

  The controller 601 uses the command data and address data received via the ADDR terminal to output signals from the CLE terminal and the FCE terminal as shown in FIG. A signal is output at a predetermined timing. Then, the ALE terminal is set to HIGH, and the command data and address data received from the microcomputer 300 are transmitted from the I / O terminal in synchronization with the timing of the signal output from the FWE terminal.

  In this case, the CPU 606 performs processing so as to write data in a block area that replaces the defective block based on information related to the defective block area in the NAND flash memory 602 in advance, and creates an address management table for that purpose. . Therefore, when the address data is received from the microcomputer 300, the address data in the block area corresponding to the received address data is transmitted from the I / O terminal based on the address management table.

  When the NAND flash memory 602 receives command data and address data at the I / O terminal, it reads the data in the corresponding address area based on these data as in the conventional case. As shown in FIG. 10, the read data is output from the controller 601 to the FRE terminal at a predetermined timing and transmitted from the I / O terminal to the controller 601 in synchronization with the timing.

  When the controller 601 receives the data read to the I / O terminal, the controller 601 stores the data in the buffer memory unit 605 and checks the data error by the error correction circuit 609. If an error is detected, the error correction is performed. Process.

  Data for which a data error has been checked is stored in the buffer memory unit 605. As shown in FIG. 6, a signal is output from the OE terminal of the microcomputer 300 at a predetermined timing, and the data in the buffer memory unit 605 is read from the ADDR terminal. When the command signal READ is transmitted, the data DATAN to N + 1 stored in the buffer memory unit 605 is transmitted from the DATA terminal correspondingly.

  In this way, the data DATAN to N + 1 stored in the NAND flash memory 602 corresponding to the address data ADDR0 to ADDR4 is read out, and the stored data can be read out sequentially by repeating this readout process.

  As described above, the memory device 600 can perform data read processing without inputting a write command signal as in the conventional NAND flash memory, and the HWE terminal is connected to the memory device 600 as in the conventional NOR flash memory. If the pull-up state is set, writing can be prohibited, so that it is possible to have an effect of preventing unauthorized modification. Further, since command data and address data can be transmitted by a series of signal strings, the number of pins of the ADDR terminal need not be increased in proportion to the increase in memory capacity.

  In the example described above, the case where the memory device according to the present invention is used as the memory device on the main control device 100 side has been described, but it can also be used as the memory device on the image display control device 200 side. Further, the terminal names described in the above-described embodiments may use other terminal names that are generally used, and are not limited to the described terminal names.

It is a front view of the whole gaming machine using an embodiment according to the present invention. It is a front view of the game board of the gaming machine of FIG. It is a block diagram which shows the circuit structure regarding a gaming machine. It is a block diagram regarding embodiment which concerns on this invention. It is a block block diagram regarding a controller. It is a timing chart regarding a reading process. It is a block diagram regarding the conventional NOR type flash memory. It is a timing chart regarding the reading process of the conventional NOR type flash memory. It is a block diagram regarding a conventional NAND flash memory. It is a timing chart regarding the reading process of the conventional NAND flash memory.

Explanation of symbols

100 Main controller
200 Image display controller
300 microcomputer
600 memory devices
601 controller
602 NAND flash memory

Claims (4)

A gaming machine memory comprising: a NAND flash memory for storing information for controlling a gaming machine; and a controller for reading information from the NAND flash memory based on a readout command signal from a main body control circuit for controlling the gaming machine A device,
The controller is
A body-side interface unit for transmitting the data read from the NAND flash memory to the main control circuit which receives the read command signal from the main control circuit,
A buffer memory unit for storing data to be transmitted to the read command signal and the main body control circuit receives from the main control circuit,
A memory-side interface unit that transmits a write command signal and a read command signal to the NAND flash memory and transmits / receives data to / from the NAND flash memory;
A controller that writes data to a block area that replaces the defective block area based on information on the defective block area in the NAND flash memory and creates an address management table that associates the defective block area and the alternative block area;
An error correction circuit for detecting an error of data read from the NAND flash memory and correcting the detected error;
The controller is
When a read output signal including command data and address data is received as the read command signal from the main body control circuit via the main body side interface unit, the address of the block area corresponding to the address data received based on the address management table Read data, send a write command signal and the command data and read address data to the NAND flash memory via the memory side interface unit,
The data read from the NAND flash memory via the memory side interface unit is stored in the buffer memory unit and the read data is checked for errors by the error correction circuit,
Data stored in the buffer memory unit is controlled via the main body side interface unit based on a read command signal for the buffer memory unit received as the read command signal from the main body control circuit via the main body side interface unit A memory device for gaming machines, characterized by being transmitted to a circuit.   The memory device for gaming machines according to claim 1, wherein a predetermined voltage is constantly applied to a write command signal input terminal of the main body side interface unit.   3. The gaming machine memory device according to claim 1, wherein the NAND flash memory and the controller are packaged in one package.   A gaming machine comprising the gaming machine memory device according to any one of claims 1 to 3.

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