JP5026758B2 - Driving circuit for plasma display device - Google Patents

Description

  The present invention relates to a driving circuit for a plasma display device, and more particularly to a driving circuit for a plasma display device that performs screen display by generating a surface discharge between display electrodes arranged on one substrate of a panel.

  As a conventional PDP, an AC drive type three-electrode surface discharge type PDP is known. In this PDP, a large number of display electrodes capable of surface discharge are provided in the horizontal direction on the inner surface of one substrate (for example, the front substrate), and the address electrodes for selecting light emitting cells intersect the display electrodes on the inner surface of the other substrate. A large number are provided in the direction, and the intersection between the display line between the display electrodes and the address electrode is used as a cell.

  In a PDP having this structure, display is performed by a driving method generally called an address / display separation method for gradation display. That is, one frame is composed of a plurality of weighted subfields, and the period of each subfield is selected as a reset period for equalizing charges in the cells and an address period for selecting cells to emit light. And a sustain period in which the cell emits light.

  The display electrode has a configuration in which electrodes that commonly apply a sustain voltage during the sustain period and electrodes that are used as scan electrodes during the address period are alternately arranged. In the present specification, hereinafter, an electrode to which a sustain voltage is commonly applied in the sustain period is referred to as “display electrode X” or “X electrode”, and an electrode that is used as a scan electrode in the address period is referred to as “display electrode Y” or “Y Electrode ".

  In this PDP, during screen display, a voltage is applied to the X electrode and the Y electrode in the reset period to generate a reset discharge, thereby uniformizing the charge in the cell. In the next address period, the screen is scanned using the Y electrode as a scan electrode, and a voltage (generally referred to as an “address voltage”) is applied to the desired address electrode during that period, so that the Y electrode is located between the Y electrode and the address electrode. Then, an address discharge is generated to form a charge in the cell to emit light. In the next sustain period, a display voltage (generally called “sustain voltage”) is alternately applied to the X electrode and the Y electrode, and the sustain discharge is continued between the XY electrodes by the number of times of weighting. By doing so, the screen is displayed. Since the X electrode and the Y electrode are arranged in parallel, this sustain discharge is a surface discharge.

In general, a rectangular waveform is used as the voltage waveform to be applied during the sustain period, and the rectangular sustain voltage pulse is applied alternately to the X electrode and the Y electrode.
The application of the sustain voltage pulse is normally performed using inductance. Then, when the sustain voltage pulse is applied to the Y or X electrode in the next subfield from the state in which the sustain voltage pulse is applied to the X or Y electrode in the previous subfield, the applied voltage is maintained at a predetermined level via the inductance. Generally, a method of increasing the voltage to 50 to 90% and then increasing the voltage to a predetermined sustain voltage by adding a voltage from a constant voltage supply circuit (see Patent Document 1).

Japanese Patent No. 2746792

  In this PDP, different voltages are applied to the X electrode and the Y electrode during the reset period, so that the drive circuit for applying a voltage to the X electrode and the drive circuit for applying a voltage to the Y electrode have different circuit configurations. For this reason, the ultimate voltage due to the inductance when applying a voltage to the X electrode may differ from the ultimate voltage due to the inductance when applying a voltage to the Y electrode. Also, even if the element used for the drive circuit on the X electrode side and the element used for the drive circuit on the Y electrode side are the same, there is a difference in impedance due to the difference in circuit pattern routing, resulting in the application of voltage to the X electrode. In some cases, the ultimate voltage due to the inductance when the voltage is applied differs from the ultimate voltage due to the inductance when the voltage is applied to the Y electrode. When the voltage reached by the inductance is different, the amount of voltage overshoot when changing to a predetermined sustain voltage after that changes.

  If this overshoot amount differs between the drive circuit on the X electrode side and the drive circuit on the Y electrode side, the discharge state changes depending on the polarity of the pulse to be applied. Product life will be shortened due to different electrode.

  In addition, since this influence is more prominent as the circuit and the discharge location are closer, for example, when the ultimate voltage due to the inductance of the drive circuit on the Y electrode side is low, if the drive circuit on the Y electrode side is arranged on the right side of the screen, Since the overshoot on the right side of the screen close to the drive circuit on the Y electrode side is larger than the overshoot on the left side of the screen, the luminance is unbalanced on the left and right sides of the screen, causing uneven luminance.

  The present invention has been made in view of such circumstances, and by maintaining a balance between the sustain voltage applied to one of the pair of display electrodes that generate the sustain discharge and the sustain voltage applied to the other, the screen This prevents brightness imbalance and brightness unevenness.

  According to the present invention, one substrate provided with a plurality of display electrodes so that a display line is formed between adjacent electrodes, and the other substrate provided with a plurality of address electrodes in a direction intersecting the display electrodes are arranged to face each other. A driving circuit for driving a plasma display panel configured to emit light as a cell at an intersection between a display line and an address electrode between display electrodes, the driving circuit generating a sustain discharge in the display line In addition, an inductance circuit that applies up to a voltage of 50 to 90% of a predetermined sustain voltage to the display electrode via an inductance, and a constant voltage supply that applies the voltage up to the predetermined sustain voltage by adding to the voltage applied by the inductance circuit An inductor that applies a voltage to one of the pair of display electrodes that generate a sustain discharge. A circuit element for adjusting the applied voltage in one or both of the first circuit and the inductance circuit that applies a voltage to the other, thereby achieving a voltage reached by the inductance circuit applied to one of the display electrodes, It is a drive circuit for a plasma display device configured such that a difference from an ultimate voltage by an inductance circuit applied to the other is a predetermined value or less.

  According to the present invention, by providing a circuit element for adjusting the applied voltage in the inductance circuit, the difference between the reached voltage by the inductance circuit applied to one of the display electrodes and the reached voltage by the inductance circuit applied to the other is a predetermined value. As a result, the luminance unbalance and luminance unevenness of the screen are prevented.

  In the present invention, as one substrate and the other substrate, substrates such as glass, quartz, and ceramic, and desired components such as electrodes, insulating films, dielectric layers, and protective films are formed on these substrates. A substrate is included.

A plurality of display electrodes may be provided in a stripe shape on one substrate. Further, a plurality of address electrodes may be provided on the other substrate in a direction intersecting with the display electrodes. The display electrode and the address electrode can be formed using various materials and methods known in the art. Examples of the material used for the electrode include transparent conductive materials such as ITO and SnO ₂ and metal conductive materials such as Ag, Au, Al, Cu, and Cr. As a method for forming the electrode, various methods known in the art can be applied. For example, it may be formed using a thick film forming technique such as printing, or may be formed using a thin film forming technique including a physical deposition method or a chemical deposition method. Examples of the thick film forming technique include a screen printing method. Among thin film formation techniques, examples of physical deposition methods include vapor deposition and sputtering. Examples of the chemical deposition method include a thermal CVD method, a photo CVD method, and a plasma CVD method.

  In the present invention, the inductance circuit may be a circuit that can apply up to a voltage of 50 to 90% of a predetermined sustain voltage via the inductance to the display electrode during the sustain period. The predetermined sustain voltage means a voltage pulse capable of generating a sustain discharge between a pair of display electrodes, and is usually a voltage pulse value of about 180 to 200V. This inductance circuit can be constructed using various inductances known in the art.

  The constant voltage supply circuit may be any circuit that can apply a voltage up to a predetermined sustain voltage by adding to the voltage applied by the inductance circuit. As this constant voltage supply circuit, a constant voltage supply circuit configured using various circuit elements known in the art can be applied.

  In the above configuration, the inductance circuit is for adjusting applied voltage to one or both of an inductance circuit that applies voltage to one of the pair of display electrodes that generate sustain discharge and an inductance circuit that applies voltage to the other. It is only necessary to have the circuit element.

  In the circuit element for adjusting the applied voltage, the difference between the voltage reached by the inductance circuit applied to one of the display electrodes and the voltage reached by the inductance circuit applied to the other is 10 volts or less, more preferably 5 volts or less. It is desirable to set as follows.

  The applied voltage adjusting circuit element may be a resistor provided in an inductance circuit that applies a voltage to one of the display electrodes. Further, inductances having different values may be provided in both the inductance circuit that applies voltage to one of the display electrodes and the inductance circuit that applies voltage to the other.

  Further, the circuit element for adjusting the applied voltage is a switch element having impedances with different values provided in both the inductance circuit that applies a voltage to one of the display electrodes and the inductance circuit that applies a voltage to the other. May be. Further, different numbers of switch elements may be provided in both the inductance circuit that applies a voltage to one of the display electrodes and the inductance circuit that applies a voltage to the other.

  Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. In addition, this invention is not limited by this, A various deformation | transformation is possible.

  FIG. 1A and FIG. 1B are explanatory views showing the configuration of the PDP of the present invention. FIG. 1A is an overall view, and FIG. 1B is a partially exploded perspective view. This PDP is an AC drive type three-electrode surface discharge type PDP for color display.

  The PDP 10 includes a front substrate 11 and a rear substrate 21 on which components that function as a PDP are formed. Although glass substrates are used as the front substrate 11 and the rear substrate 21, a quartz substrate, a ceramic substrate, or the like can be used in addition to the glass substrate.

Display electrodes X (X electrodes) and display electrodes Y (Y electrodes) are arranged at equal intervals in the horizontal direction on the inner side surface of the substrate 11 on the front side. The display line L is entirely between the adjacent display electrode X and display electrode Y. Each of the display electrodes X and Y is made of a wide transparent electrode 12 such as ITO or SnO ₂ and, for example, Ag, Au, Al, Cu, Cr, and a laminated body thereof (for example, a laminated structure of Cr / Cu / Cr). And a narrow bus electrode 13 made of metal. For the display electrodes X and Y, a desired number and thickness can be obtained by using a thick film forming technique such as screen printing for Ag and Au, and using a thin film forming technique such as vapor deposition and sputtering and an etching technique for others. It can be formed with a width, width and spacing.

  In this PDP, the display electrode X and the display electrode Y are arranged at equal intervals, and the PDP has a so-called ALIS structure in which the display lines L are all between the adjacent display electrodes X and Y. The present invention can also be applied to a PDP having a structure in which the pair of display electrodes X and Y are arranged with an interval (non-discharge gap) where no discharge occurs.

A dielectric layer 17 is formed on the display electrodes X and Y so as to cover the display electrodes X and Y. The dielectric layer 17 is formed by applying a glass paste made of glass frit, a binder resin, and a solvent onto the front substrate 11 by a screen printing method and baking it. The dielectric layer 17 may be formed by forming a SiO ₂ film by plasma CVD.

  A protective film 18 is formed on the dielectric layer 17 to protect the dielectric layer 17 from damage caused by ion collision caused by discharge during display. This protective film is made of MgO. The protective film can be formed by a thin film forming process known in the art, such as an electron beam evaporation method or a sputtering method.

  On the inner side surface of the substrate 21 on the back side, a plurality of address electrodes A are formed in a direction intersecting the display electrodes X and Y in plan view, and a dielectric layer 24 is formed to cover the address electrodes A. . The address electrode A generates an address discharge for selecting a light emitting cell at the intersection with the display electrode Y, and has a three-layer structure of Cr / Cu / Cr. In addition, the address electrode A can be formed of Ag, Au, Al, Cu, Cr, or the like. As with the display electrodes X and Y, the address electrode A uses a thick film forming technique such as screen printing for Ag and Au, and a thin film forming technique such as vapor deposition and sputtering and an etching technique for the other. Thus, it can be formed with a desired number, thickness, width and interval. The dielectric layer 24 can be formed using the same material and the same method as the dielectric layer 17.

  On the dielectric layer 24 between the adjacent address electrodes A, lattice-shaped barrier ribs 29 for partitioning the discharge space for each cell are formed. The lattice-like partition walls 29 are also called box ribs, mesh ribs, waffle ribs, or the like. The partition walls 29 can be formed by a sand blast method, a photosensitive paste method, or the like. For example, in the sandblasting method, a glass paste made of glass frit, a binder resin, a solvent, and the like is applied on the dielectric layer 24 and dried, and then a cutting mask having a partition pattern opening is provided on the glass paste layer. It forms by spraying cutting particle | grains in the state, cutting the glass paste layer exposed to the opening of the mask, and also baking. Further, in the photosensitive paste method, instead of cutting with cutting particles, a photosensitive resin is used as a binder resin, and it is formed by baking after exposure and development using a mask.

  Phosphor layers 28R, 28G, and 28B of red (R), green (G), and blue (B) are formed on the side surface and the bottom surface of the rectangular cell in plan view surrounded by the lattice-shaped partition walls 29. For the phosphor layers 28R, 28G, and 28B, a phosphor paste containing phosphor powder, a binder resin, and a solvent is applied to the cells surrounded by the partition walls 29 by screen printing or a method using a dispenser. It is formed by firing after repeating for each color. The phosphor layers 28R, 28G, and 28B can be formed by a photolithography technique using a sheet-like phosphor layer material (so-called green sheet) containing phosphor powder, a photosensitive material, and a binder resin. In this case, a phosphor sheet of each color can be formed in the corresponding cell by applying a sheet of a desired color to the entire display area on the substrate, exposing and developing, and repeating this for each color. it can.

  In the PDP, the substrate 11 on the front side and the substrate 21 on the back side are arranged to face each other so that the display electrodes X, Y and the address electrodes A intersect, and the periphery is sealed and surrounded by the partition wall 29. It is manufactured by filling the discharge space 30 with a discharge gas in which Xe and Ne are mixed. In this PDP, the discharge space 30 at the intersection of the display electrodes X and Y and the address electrode A is one cell (unit light emitting region) which is the minimum unit of display. One pixel is composed of three cells, R, G, and B.

  In the above, an example of a PDP in which a grid-like partition wall is formed on the back substrate is shown, but the present invention is not limited to this, and a stripe-like partition wall (called stripe rib or the like) is formed only in the column direction of the screen. The present invention can be applied even to a PDP that has been made.

FIG. 2 is an explanatory diagram showing the field configuration, and FIG. 3 is an explanatory diagram showing an example of the field configuration and drive voltage pulses.
The PDP performs screen display by being driven by an address / display separation method. In this screen display, one frame F is divided into an arbitrary number of fields fj. Then, one field fj is divided into eight subfields sf1 to sf8 having different weights, and the period Tsfj of each subfield is selected as a reset period TR for equalizing charges in the cells and a cell to be emitted. An address period TA and a sustain period TS for causing the selected cell to emit light are configured.

In the reset period TR, the reset pulse Pr is applied to all the X electrodes to equalize the charges in the cells. In the next address period TA, using the Y electrode group as a scan electrode, the Y1... Yn electrodes are sequentially scanned (scan timing is indicated by Tc in FIG. 2) and a scan pulse Py is applied between them. By applying an address pulse Pa to the address electrode A and generating an address discharge between the address electrode A and the Y electrode, wall charges are accumulated in the cells to be lit. In the next sustain period TS, a sustain voltage pulse Ps is alternately applied between the X electrode group and the Y electrode group to generate a sustain discharge in the cell in which wall charges are accumulated, thereby causing the cell to emit light. . The cell emits light by exciting the phosphor with ultraviolet rays generated by the sustain discharge and generating visible light of a desired color from the phosphor. In this way, PDP screen display is performed by driving the address / display separation method.
Embodiment 1

FIG. 4 is a circuit configuration diagram showing Embodiment 1 of the present invention.
Hereinafter, embodiments of the driving circuit of the PDP will be described. In the following description, a drive circuit that applies a voltage pulse to the X electrode group is referred to as an X side circuit, and a drive circuit that applies a voltage pulse to the Y electrode group is referred to as a Y side circuit. Further, the sustain voltage pulse applied to the X electrode group will be described as an X pulse, and the sustain voltage pulse applied to the Y electrode group will be described as a Y pulse. Since the address circuit for applying a voltage to the address electrode is not directly related to the present invention, the description thereof is omitted.

  As for the X-side circuit, only the X-SUS circuit 41 that generates X pulses will be described. In addition to this, the X-side circuit includes a reset waveform generator for generating a reset pulse, but these are not shown.

  As for the Y-side circuit, only the Y-SUS circuit 42 that generates Y pulses will be described. In addition to this, the Y-side circuit is provided with a plus reset waveform generating unit 43 and a minus reset waveform generating unit 44 for applying a reset pulse to the Y electrode group in the reset period. In addition, a scan circuit 45 that sequentially applies a scan pulse to the Y electrode group in the address period is provided. A voltage is supplied to the scan circuit 45 from the scan selection potential generation unit 46 and the scan non-selection potential generation unit 47. The scan selection potential generator 46 generates a voltage to be applied to the currently selected Y electrode. The scan non-selection potential generation unit 47 generates a voltage to be applied to the Y electrodes other than the currently selected one. The scan circuit 45 is provided with a switch Sw9 and a switch Sw10, and a scan voltage is selected by these switches.

  The X-SUS circuit 41 has an inductance circuit that applies up to a voltage of 50 to 90% of a predetermined sustain voltage to the X electrode group via the inductance during the sustain period. This inductance circuit is supplied with a voltage that is ½ of the sustain voltage Vs. The inductance circuit has a switch Sw1, a resistor R1, a first inductance L1, and a first circuit connected in series with a diode, and a switch Sw2, a second inductance L2, and a second circuit connected in series with a diode connected in parallel. It has a configuration.

  The X-SUS circuit 41 also has a constant voltage supply circuit that applies a voltage up to a predetermined sustain voltage Vs by adding the voltage applied by the inductance circuit. The constant voltage supply circuit includes a switch Sw3 that controls application of the sustain voltage Vs and a switch Sw4 that sets the sustain voltage Vs to zero. By turning on and off these switches, the voltage applied by the inductance circuit is added to a predetermined sustain voltage Vs, and then the sustain voltage Vs is made zero.

  The Y-SUS circuit 42 is configured by removing the resistor R1 from the inductance circuit of the X-SUS circuit 41. That is, the Y-SUS circuit 42 also includes an inductance circuit that applies up to a voltage of 50 to 90% of a predetermined sustain voltage via the inductance to the Y electrode group during the sustain period. This inductance circuit is supplied with a voltage that is ½ of the sustain voltage Vs. The inductance circuit has a configuration in which a third circuit in which the switch Sw5, the third inductance L3, and the diode are connected in series, and a fourth circuit in which the switch Sw6, the fourth inductance L4, and the diode are connected in series are connected in parallel. ing.

  The Y-SUS circuit 42 also has a constant voltage supply circuit that applies a voltage up to a predetermined sustain voltage Vs by adding the voltage applied by the inductance circuit. This constant voltage supply circuit includes a switch Sw7 that controls application of the sustain voltage Vs and a switch Sw8 that sets the sustain voltage Vs to zero. By turning on and off these switches, the voltage applied by the inductance circuit is added to a predetermined sustain voltage Vs, and then the sustain voltage Vs is made zero.

  In the present embodiment, the resistor R1 is inserted into the inductance circuit of the X side circuit so that the ultimate voltage by the inductance circuit of the X side circuit is equal to the ultimate voltage by the inductance circuit of the Y side circuit. Specifically, a resistor R1 is inserted between the inductance L1 of the X-SUS circuit 41 and the switch Sw1.

  The resistor R1 has a role of reducing the difference between the ultimate voltage due to the inductance when the X pulse is raised and the ultimate voltage due to the inductance when the Y pulse is raised. The difference between the X side circuit and the Y side circuit becomes large. The difference between the X side circuit and the Y side circuit of the reached voltage due to the inductance is preferably within 10V, and more preferably within 5V. The resistance value of the resistor R1 is desirably about 0.02 to 2Ω in the 42 inch diagonal class.

FIG. 5 is an explanatory diagram showing switch timing when a sustain voltage pulse is applied during the sustain period.
First, at time t1, the switch Sw1 of the X side circuit is turned on, and the voltage of the X pulse applied to the X electrode group is changed to 50 to 90% of the sustain voltage Vs by the inductance circuit. Next, at time t2, the switch Sw1 is turned off and the switch Sw3 is turned on, and the voltage of the applied X pulse is raised to the sustain voltage Vs. When the switch Sw3 is turned off before the time t3 when the X pulse ends, and the switch Sw2 is turned on at the time t3, the voltage is dropped by the inductance circuit. Thereafter, the switch Sw3 is turned off and the switch Sw4 is turned on, whereby the voltage is pulled down to 0V.

  In the application of the next Y pulse, the same operation as that performed on the X side circuit is performed on the Y side circuit. The switches Sw9 and Sw10 are turned on throughout the sustain period. By turning these on, the operation of the Y-side circuit is transmitted to the Y electrode group through the scan LSI for scanning the Y electrode group during the address period. Depending on the circuit configuration, the switches Sw9 and Sw10 may be turned off during the sustain period.

  FIG. 6A to FIG. 6C are explanatory diagrams showing comparative examples of the reached voltage by the inductance circuit. FIG. 6A shows a case where the ultimate voltage Vt by the inductance circuit is an appropriate value. FIG. 6B shows a case where the reached voltage Vt is lower than the appropriate value. When the reached voltage Vt is lower than the appropriate value, the voltage overshoot amount Vos when the voltage is changed to the predetermined sustain voltage Vs is obtained. growing. FIG. 6C shows a case where the reached voltage Vt is higher than the appropriate value. When the reached voltage Vt is higher than the appropriate value, the voltage overshoot amount Vos when the voltage is changed to the predetermined sustain voltage Vs is obtained. Get smaller.

  If this overshoot amount Vos differs between the X-side circuit and the Y-side circuit, the discharge state changes depending on the polarity of the pulse to be applied, so the burn-in amount due to long-time driving differs between the X electrode and the Y electrode. Product life is shortened.

  In addition, this effect becomes more prominent as the circuit and the discharge location are closer. For example, when the voltage reached by the inductance of the Y-side circuit is low, if the Y-side circuit is arranged on the right side of the screen, the screen is closer to the Y-side circuit. Since the overshoot on the right side is larger than the overshoot on the left side of the screen, the luminance is unbalanced on the left and right sides of the screen, causing uneven luminance.

  FIG. 10 is an explanatory diagram showing a comparative example. In this comparative example, the resistor R1 is not inserted in the inductance circuit of the X-SUS circuit 41. Other parts are the same as those in the first embodiment. In the circuit of this comparative example, the X pulse applied to the X electrode group and the Y pulse applied to the Y electrode group are unbalanced, resulting in luminance imbalance and luminance unevenness on the screen.

On the other hand, in this embodiment, since the resistor R1 is inserted in the inductance circuit of the X-SUS circuit 41, the X pulse applied to the X electrode group and the Y pulse applied to the Y electrode group are balanced, As a result, the luminance imbalance of the screen can be eliminated and luminance unevenness can be eliminated.
Embodiment 2

FIG. 7 is a circuit configuration diagram showing Embodiment 2 of the present invention.
In the comparative example shown in FIG. 10, the value of the inductance L1 of the X-SUS circuit 41 is equal to the value of the inductance L3 of the Y-SUS circuit 42, and further, the value of the inductance L2 of the X-SUS circuit 41 and the Y-SUS circuit 42 The value of the inductance L4 is equal.

  On the other hand, in this embodiment, the inductance for applying a voltage is different from that of the X side circuit and the Y side circuit. That is, by using different values for the inductance L1 of the X-SUS circuit 41 and the inductance L3 of the Y-SUS circuit 42, the voltage reached by the inductance circuit of the X-SUS circuit 41 and the inductance of the Y-SUS circuit 42 are increased. The voltage reached by the circuit is made equal.

By varying the value of the inductance L1 of the X-SUS circuit 41 and the value of the inductance L3 of the Y-SUS circuit 42, the Q value (resonance sharpness) is changed, and the ultimate voltage due to the inductance is different between the X side circuit and the Y side circuit. Adjust to be equal.
Embodiment 3

FIG. 8 is a circuit configuration diagram showing Embodiment 3 of the present invention.
In the comparative example shown in FIG. 10, the on-resistance value of the switch Sw <b> 1 of the X-SUS circuit 41 is equal to the on-resistance value of the switch Sw <b> 5 of the Y-SUS circuit 42, and the on-resistance value of the switch Sw <b> 2 of the X-SUS circuit 41. And the on-resistance value of the switch Sw6 of the Y-SUS circuit 42 are equal.

  On the other hand, in the present embodiment, the switch element for applying a voltage via the inductance uses elements having different on-resistance values in the X side circuit and the Y side circuit, thereby changing the impedance, The voltage reached by the inductance circuit of the circuit is made equal to the voltage reached by the inductance circuit of the Y-side circuit.

  That is, by adopting different FETs for the switch Sw1 of the X-SUS circuit 41 and the switch Sw5 of the Y-SUS circuit 42, the on-resistance values are made different, and the ultimate voltage due to the inductance is equal between the X side circuit and the Y side circuit. Adjust so that

This can be adjusted by using, for example, 2SK3556 (manufactured by Fuji Electric Co., Ltd.) with an on-resistance value of 0.1Ω for the switch Sw1, and 2SK3594 (manufactured by Fuji Electric Co., Ltd.) with an on-resistance value of 0.05Ω for the switch Sw5. It is.
Embodiment 4

FIG. 9 is a circuit configuration diagram showing Embodiment 4 of the present invention.
In the present embodiment, the impedance is changed by changing the number of switch elements for applying a voltage via an inductance between the X-side circuit and the Y-side circuit, and the ultimate voltage due to the inductance of the X-side circuit and the Y The ultimate voltage due to the inductance of the side circuit is made equal.

  That is, by connecting the switch Sw11 in parallel with the switch Sw5 of the Y-SUS circuit 42 and lowering the resistance value of the Y-SUS circuit 42, the ultimate voltage due to the inductance is equalized between the X side circuit and the Y side circuit. adjust.

  As described above, according to the first to fourth embodiments of the present invention, the brightness of the screen is obtained by balancing the voltage reached by the inductance circuit applied to the X electrode and the voltage reached by the inductance circuit applied to the Y electrode. Unbalance and luminance unevenness can be prevented, and the quality of the PDP can be improved.

It is explanatory drawing which shows the structure of PDP of this invention. It is explanatory drawing which shows a field structure. It is explanatory drawing which shows an example of a field structure and a drive voltage pulse. It is a circuit block diagram which shows Embodiment 1 of this invention. It is explanatory drawing which shows the switch timing at the time of applying a sustain voltage pulse. It is explanatory drawing which shows the comparative example of the ultimate voltage by an inductance. It is a circuit block diagram which shows Embodiment 2 of this invention. It is a circuit block diagram which shows Embodiment 3 of this invention. It is a circuit block diagram which shows Embodiment 4 of this invention. It is explanatory drawing which shows a comparative example.

Explanation of symbols

10 PDP
DESCRIPTION OF SYMBOLS 11 Front side substrate 12 Transparent electrode 13 Bus electrode 17, 24 Dielectric layer 18 Protective film 21 Back side substrate 28R, 28G, 28B Phosphor layer 29 Bulkhead 30 Discharge space A Address electrode L Display line X, Y Display electrode

Claims (4)

One substrate provided so that a display line is formed between a pair of adjacent display electrodes with a plurality of display electrodes, and the other substrate provided with a plurality of address electrodes in a direction intersecting the display electrodes and, a drive circuit for driving a plasma display panel that is configured to emit light intersections as a cell of the display lines and address electrodes between the display electrodes,
The drive circuit includes a first display electrode drive circuit that drives one display electrode of the adjacent display electrodes that form the pair, and a second display electrode drive circuit that drives the other display electrode,
The first display electrode driving circuit includes:
At least the first switch and the first inductance are connected in series, and a voltage that is ½ of the sustain voltage Vs is supplied, and the first display electrode is turned on by the ON operation of the first switch . A first inductance circuit for applying up to a voltage of 50 to 90% of the sustain voltage Vs through an inductance of 1 ;
A first constant voltage supply for applying the sustain voltage Vs to the first display electrode to which one end has a switch connected to the power source of the sustain voltage Vs and to which the voltage by the first inductance circuit is applied With circuit,
The second display electrode driving circuit includes:
At least a second switch and a second inductance are connected in series, and a voltage that is ½ of the sustain voltage Vs is supplied, and the second display electrode is turned on by the ON operation of the second switch. A second inductance circuit for applying up to 50 to 90% of the sustain voltage Vs through a second inductance;
A second constant voltage supply for applying the sustain voltage Vs to the second display electrode to which one end has a switch connected to the power source of the sustain voltage Vs and to which the voltage by the second inductance circuit is applied With circuit,
Wherein the resistance value at the time of conduction of the first switch, said by making the resistance value at the time of conduction of the second switch, the ultimate voltage by the first inductance circuit for applying to said first display electrodes And a driving circuit for a plasma display device configured so that a difference between a voltage achieved by the second inductance circuit applied to the second display electrode and a voltage reached by the second inductance is equal to or less than a predetermined value.   2. The driving circuit for a plasma display device according to claim 1, wherein a difference between a voltage reached by the inductance circuit applied to one of the display electrodes and a voltage reached by the inductance circuit applied to the other is 10 volts or less. 3. The driving circuit of the plasma display device according to claim 1, wherein on-resistance values of the first switch and the second switch are made different from each other. 4. The first display electrode is an electrode to which a scan pulse is sequentially applied in an address period, wherein the first switch is composed of two switch elements, and the second switch is composed of one switch element. The drive circuit of the plasma display apparatus as described in any one of Claim 1 thru | or 3.

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