JP5024162B2 - Semiconductor device manufacturing method and semiconductor test apparatus - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor test apparatus.

  In a manufacturing process of a semiconductor device such as an LSI, after a plurality of chips are formed on a semiconductor wafer, an electrical test is performed on each chip at the wafer level, and non-defective chips and defective chips are selected. Chips determined to be defective in the electrical test are marked with ink so as not to be mistaken as good products, and then discarded.

  On the other hand, chips that are determined to be non-defective products are shipped to the market through subsequent processes such as a packaging process.

  However, in such good chips, there is a potential defective chip that becomes defective after it is put on the post-process or market because it has passed the electrical test. In order not to put such chips on the market, it may be possible to further tighten the acceptance criteria in the electrical test, but this reduces the number of non-defective chips obtained from a single semiconductor wafer. Yield decreases.

  Further, whether or not a non-defective chip is potentially defective can be grasped to some extent by a method of distribution of defective chips (AUF: Area Usage of Factor) in the wafer surface (Patent Document 1).

  For example, as disclosed in Patent Document 1, even if it is determined as a non-defective chip in the electrical test, if a defective chip exists next to the non-defective chip, the non-defective chip may be potentially defective. There is. Whether there is a high possibility of being defective depends on the distribution method of defective chips.

  However, since the determination of the possibility is performed based on the sense of the worker based on the distribution of defective chips, the determination result may be different depending on the worker, and the chip that may be potentially defective May be shipped to the market. In addition, depending on the worker, it may take a long time for the determination, and the flow of product shipment may be delayed.

In addition, techniques related to the present application are also disclosed in Patent Documents 2 to 5.
JP 2006-128251 A JP 59-231830 A JP 2003-59984 A JP 2001-308157 A JP 2004-96121 A

  In a semiconductor device manufacturing method and a semiconductor test apparatus, an object is to reduce the risk of putting out a chip that may possibly be defective into a subsequent process.

According to one aspect of the present invention, defective chips on a semiconductor wafer determined to be defective based on a predetermined test are classified into a first defective mode and a second defective mode, and based on the predetermined test. The distribution of defective chips belonging to the first failure mode adjacent to the non-defective chips on the semiconductor wafer determined to be non-defective is investigated, and based on the distribution, whether the non-defective chips are the first type non-defective chips. There line determines whether the second type of good chips, relative to the first type as determined by said non-defective chips, to add acceptance conditions severe test than the predetermined test, and pass in the additional test The semiconductor device manufacturing method is characterized in that the determined non-defective chip is determined as a true non-defective chip, and the non-defective chip determined to be unacceptable in the additional test is determined as a defective chip .

According to another aspect of the present invention, the calculation unit includes a calculation unit that inputs a test signal in a predetermined test to a semiconductor chip formed on a semiconductor wafer and determines whether the semiconductor chip is acceptable or not. Classify the defective chip determined to be defective in the pass / fail determination into a first defective mode and a second defective mode,
The distribution of defective chips belonging to the first failure mode adjacent to the non-defective chips determined as non-defective in the pass / fail determination is investigated, and based on the distribution, whether the non-defective chips are the first type non-defective chips or not. There line determines whether the two types of non-defective chip with respect to the first type as determined by said non-defective chip, performs the acceptance criteria stringent additional tests than the predetermined test, passing the decision in the additional test There is provided a semiconductor test apparatus characterized in that the determined good chip is determined as a true good chip, and the good chip determined to be unacceptable in the additional test is determined as a defective chip .

  According to the present invention, based on the distribution of defective chips belonging to the first failure mode existing around the non-defective chips, whether the non-defective chips are the first type good chips or the second type good chips. Make a decision.

  As the first type non-defective chip, for example, there is a non-defective chip that is likely to be defective due to the presence of many margin-type defective chips in the periphery. In that case, by classifying the non-defective chip according to the mode of the defective chip, for example, for the first type non-defective product, the shipment is reserved and the non-defective chip that may potentially become defective Can be prevented from entering the market.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(1) First Embodiment FIG. 1 is a configuration diagram of a semiconductor test apparatus according to this embodiment.

  The semiconductor test apparatus 1 includes a stage 2 on which a semiconductor wafer W is placed and movable in the horizontal direction, a probe card 3 facing the semiconductor wafer W, and a calculation unit 5 such as a personal computer.

Of these, the probe card 3, in correspondence with the terminal E of the semiconductor wafer W and the probes 4 are provided, the test signal S _in is input to the terminal E from the probe 4 during testing.

  Further, a heater (not shown) is incorporated in the stage 2, and the semiconductor wafer W can be heated to a desired test temperature under the control of the calculation unit 5.

The moving amount of the stage 2 in the horizontal plane, the test signal _{Sin, and the} like are controlled by the calculation unit 5. The output signal S _out output from the semiconductor wafer W by the input of the test signal S _in is input to the calculation unit 5, and the calculation unit 5 determines the quality of the chip formed on the semiconductor wafer W based on the output signal S _out. Do.

  The calculation unit 5 includes a storage unit 7, and the result of pass / fail determination is stored in the storage unit 7 as test result data.

  The test result data includes the position of the defective chip on the semiconductor wafer W and a defect mode described later, and is displayed on the display unit 8 such as a CRT in the form of a wafer map.

  Next, a method for manufacturing a semiconductor device using the semiconductor test apparatus 1 will be described.

  FIG. 2 is a flowchart showing the method for manufacturing the semiconductor device according to this embodiment.

  Unless otherwise specified, this flowchart is executed by the calculation unit 5.

  In the first step S1, the semiconductor wafer W is heated to about 90 ° C. by the stage 2, and a thermal load is applied to the semiconductor chip during the test.

  Next, the process proceeds to step S2, and it is confirmed whether or not the probe 4 and the terminal E are correctly conducted.

  Then, the process proceeds to step S3 to check whether or not the plurality of terminals E are electrically short-circuited.

  These steps S2 and S3 are basic confirmation items before the test. After these confirmations, a substantial test is performed as follows.

  First, in step S4, the margin of the circuit formed on the chip is measured.

  Margin measurement refers to measuring whether or not fluctuations in input / output signals of a chip are within an allowable range.

  If the input / output signal is not within the allowable range, the chip is determined to be defective, and if not, the chip is determined to be non-defective.

  There are various margins of the circuit to be measured, some of which are shown in FIG.

  In addition to the one shown in FIG. 3, the margin measurement also includes searching for a range of operating parameters in which the chip can operate normally by varying operating parameters such as operating voltage and operating current. In this case, if the range is narrower than the guaranteed range guaranteed by the product, the chip is determined to be defective, and if not, it is determined to be a non-defective product. For example, when the guaranteed range of power supply voltage is 2.7 to 3.3 V and the power supply voltage range in which the chip can operate normally is 2.9 to 3.1 V, the chip is defective. It is determined.

  The width of the circuit margin depends on the width of the device pattern such as the gate electrode. The width of the device pattern depends on process parameters such as the etching rate in the wafer surface, and the process parameter continuously varies in the wafer surface, and it takes a unique value only in a certain chip. It is rare. Therefore, when it is determined that a margin is narrow in a certain chip, there is a strong tendency that a chip adjacent to the chip is also determined to have a narrow margin.

  In this embodiment, what is determined to be defective in any of the circuit margin test items in FIG. 3 is referred to as “margin defect”.

  In addition, even if the result of exploring the range of operating parameters such as operating voltage and operating current that allow the chip to operate normally reveals that the range is narrower than the guaranteed range of the product, the chip It is determined as “margin defect”.

  Next, it moves to step S5 and performs a function test with respect to a semiconductor chip.

  In this functional test, a power supply voltage is supplied to a semiconductor chip, and an output voltage such as a HIGH level voltage or a LOW level voltage output from an output terminal by a logical operation performed by a circuit in the chip is measured. If the level of the output voltage is a predetermined value, the chip is determined to be non-defective, and if not, it is determined to be defective.

  The test result in the functional test depends on foreign matters such as particles that happen to adhere to the chip during the manufacturing, and does not depend much on the shape of the device pattern. Therefore, even if a certain chip fails in the functional test, it is rare that the adjacent chip becomes defective in the functional test. In the following, what becomes defective in the functional test due to the adhesion of foreign matter will be referred to as “sudden failure”.

  Next, the process proceeds to step S6, and a pass / fail judgment is made for the semiconductor chip to be tested. This determination is made by rejecting a chip determined to be defective in either step S4 or step S5 and accepting a chip determined to be non-defective in both steps S4 and S5.

  Subsequently, the process proceeds to step S7, and the result of the pass / fail judgment in step S6 is displayed in the form of a wafer map.

  FIG. 4 is a diagram showing an example of the wafer map.

  In the wafer map, non-defective chips and defective chips are displayed with different shades of color. In FIG. 4, shades of color are indicated by hatching.

  Next, the process proceeds to step S8, and the chips determined as defective chips are classified into marginal defects and sudden defects, and these are redisplayed in different colors on the wafer map. Such a failure classification is automatically performed by the calculation unit 5 based on whether the defective chip has become defective in the margin measurement in step S4 or the functional test in step S5.

  FIG. 5 is an enlarged view of this wafer map centering on the five non-defective chips 20 to be tested. However, in FIG. 5 and FIG. 6 and FIG. 7 described later, the color difference is indicated by hatching.

  By performing color-coded display in this way, the in-plane distribution of the marginal defective chip 22 and the sudden defective chip 23 can be grasped.

  Instead of color coding, the margin defective chip 22 and the sudden defective chip may be displayed by symbols such as alphabets and numerals.

  Next, the process proceeds to step S9, and the distribution of the margin defective chips 22 existing around the non-defective chip 20 is investigated.

  In the present embodiment, it is investigated whether or not the number of margin defective chips 22 existing adjacent to the target non-defective chip 20 is a predetermined number or more, for example, two or more.

  The chips adjacent to the non-defective chip 20 are a total of eight chips, that is, four chips adjacent to the four sides of the chip 20 and four chips adjacent to the chip 20 in the diagonal direction.

  As described above, when a circuit margin is narrow in a certain chip, the circuit margin tends to be narrow in a chip adjacent to the chip. Therefore, when there are a predetermined number (two in this example) of marginal defective chips 22 around the non-defective chips 20, the non-defective chips 20 adjacent to the defective chips 22 also have a narrow circuit margin, and are non-defective chips. 20 is likely to be potentially bad.

  Therefore, in the next step S10, when the number of margin defective chips 22 adjacent to the non-defective chip 20 is equal to or larger than a predetermined number, the non-defective chip (the first non-defective chip) that has a high possibility of becoming a non-defective chip 20 is determined. 1 type non-defective chip).

  On the other hand, when the number of margin defective chips 22 adjacent to the non-defective chips 20 is less than a predetermined number, the true non-defective chips (the second type non-defective chips) are less likely to become defective. ).

  If it is determined that the chip is a semi-defective chip (YES) in this step, the process proceeds to step S11, and the type of the non-defective chip 20 is stored in the storage unit 7 included in the semiconductor test apparatus 1 as a semi-defective product.

  On the other hand, if it is determined in step S10 that the chip is not a semi-defective chip (NO) but a true good chip, the process proceeds to step S12, and the type of the non-defective chip 20 is stored in the storage unit 7 as a true good chip. Let

  As shown in FIG. 6, the non-defective chip 20 determined to be a semi-defective product is displayed in a different color from the other chips on the display unit 8 of the semiconductor test apparatus.

  Instead of displaying in color in this way, the semi-defective chip 20 may be displayed by symbols such as alphabets and numbers.

  FIG. 6 is an enlarged view of a wafer map centering on the five non-defective chips 20 identical to FIG. In this example, since the second and third non-defective chips 20 from the right are adjacent to two or more margin defective chips, they are displayed in a color different from other non-defective chips.

  Subsequently, the process proceeds to step S13, where the calculation unit 5 refers to the storage unit 7 and determines whether the type of the non-defective chip 20 is a semi-defective product.

  If it is determined that the product is a semi-defective product (YES), the process proceeds to step S14, and a margin-type additional test with a more strict pass condition than that in step S4 is performed on the good product chip 20 determined to be a semi-good product. Do.

  As an additional test item in this case, there is a test shown in FIG. Then, in order to make the pass condition stricter, the margin width shown in FIG. 3 may be made narrower than in step S4.

  If the margin width is too narrow, almost all non-defective chips 20 may be defective. Therefore, in the additional test, it is preferable to narrow the margin within a range of 5% from the margin in step S4.

  Further, the pass condition of this additional test may be made stricter by making the guaranteed range of the operating parameters such as the operating voltage and the operating current wider than in step S4. In this case, if the chip operates within the extended warranty range, it will be accepted, otherwise it will be rejected.

  For example, when the guaranteed range of the power supply voltage in step S4 is 2.7 to 3.3 V, the guaranteed range is further expanded to 2.6 to 3.4 V, and the chip passes if it operates in this range.

  Alternatively, the test temperature may be higher than that in step S4. In this way, since the thermal load applied to the chip determined to be a non-defective product is greater than that in step S4, it is easier to determine that what has passed in step S4 is rejected, which is more than that in step S4. Conditions can be tightened.

  In this case, if the temperature rise is small compared to step S4, the thermal load applied to the chip becomes insufficient, and the pass condition may not be so strict. Therefore, it is preferable to increase the temperature by 3% or more as compared with the temperature in step S4 and apply a sufficient heat load to the chip.

  If the non-defective chip 20 that has been determined to be a semi-defective product is passed under stricter passing conditions than in step S4 as described above, it is considered that a marginal defect is unlikely to occur even if it is put on the market. It may be handled as a good chip.

  Therefore, in the next step S15, it is determined whether or not the non-defective chip 20 determined to be a semi-defective product passes the additional test. If it is determined to pass (YES), the non-defective chip 20 is determined to be true in step S17. Ship as non-defective chips.

  If it is determined in step S13 that the chip is not a near-defective chip (NO), it is automatically determined in step S15 that the chip has passed (YES), and the process proceeds to step S17.

  On the other hand, if it is determined in step S15 that it is not acceptable (NO), the non-defective chip 20 is handled as a defective product in step S16. Then, the non-defective chip 20 treated as a defective product in this way is marked with ink so that it is not mistaken for a non-defective product. Instead of marking with ink, data indicating that the non-defective chip 20 should be handled as a defective product is added to the test result data held by the semiconductor test apparatus 1 in the form of a wafer map. You may make it display with a different color from the chip | tip. Such a process is also called a data marking process.

  As shown in FIG. 7, the non-defective chip 20 to be handled as a defective product is displayed on the display unit 8 of the semiconductor test apparatus in a color different from that of the other chips. Instead of displaying in color in this way, symbols such as alphabets and numbers may be displayed.

  FIG. 7 is an enlarged view of the wafer map centering on the five non-defective chips 20 identical to those in FIG. In this example, since the chip 20 determined as the third semi-defective product from the right has failed in the additional test, it is displayed in a different color from the other chips by the data marking process.

  Thus, the main process of the semiconductor device manufacturing process according to this embodiment is completed.

  According to the above-described embodiment, as shown in FIG. 5, the defective chips around the non-defective chip 20 are classified into the marginal defective chip 22 and the sudden defective chip 23. As shown in FIG. 6, when the number of margin defective chips 22 adjacent to the non-defective chip 20 is a predetermined number or more, the non-defective chip 20 is determined as a semi-defective chip.

  By recognizing semi-good chips that can potentially be defective in this way, it is possible to reserve that semi-defective chips are put on the post-process or market, and become defective after they are put on the post-process or market. The number of chips can be reduced.

  Moreover, since the calculation unit 5 automatically determines whether or not the product is a semi-defective product, there is no room for individual differences of workers in the determination, and the determination can be performed in a very short time. Shipments can proceed without delay.

  Further, as shown in FIG. 7, a margin-type additional test with stricter pass conditions than in step S4 is performed on the non-defective product 20 determined to be a semi-defective product, and those that fail in this test are rejected. Treat it as a non-defective product, and treat it as a true good chip.

  As a result, chips that are potentially defective can be selected as defective products, and only genuine good chips can be put on the post-process or market, and there is a risk that a chip that may become defective can be put on the post-process etc. Further reduction can be achieved.

  By the way, in general, when there are many defective chips in a certain semiconductor wafer, even if there are good chips in the wafer, there is a risk that the good chips may become defective in subsequent processes. Semiconductor wafers are usually discarded.

  When this embodiment is applied to such a semiconductor wafer, it is possible to take out non-defective chips that are unlikely to become potentially defective without being disposed of. This will be described below.

  FIG. 8 is a graph showing the yield of the semiconductor wafer W in a certain product type. The horizontal axis of this graph indicates the number of the semiconductor wafer W, and the vertical axis indicates the yield of non-defective chips on the semiconductor wafer.

  As shown in this figure, the yield varies depending on the semiconductor wafer W even in the same type.

  In this example, wafer grades WG1 to WG3 are used as indices indicating the level of yield.

  When the standard deviation of the yield of all wafers is σ, a wafer of the wafer grade WG1 is defined as a wafer whose yield is higher than the sum of the average yields Y and 2σ of all wafers (Y + 2σ).

  A wafer of wafer grade WG2 is defined as a wafer whose yield is higher than the difference between the average yield Y of all wafers and 2σ (Y−2σ) and lower than Y + 2σ.

  A wafer of wafer grade WG3 is defined as a wafer whose yield is lower than the difference between the average yield Y of all wafers and 2σ (Y−2σ).

  FIG. 9 is a wafer map showing the distribution of defective chips of wafer grade WG2. FIG. 10 is a wafer map showing the distribution of defective chips of wafer grade WG3. As shown in these drawings, in a wafer in which many defective chips exist, even if there are good chips, it is doubtful whether or not they are really good chips.

  FIG. 11 shows the wafer grade WG3 wafer shown in FIG. 10 is subjected to an additional test (step S14) on the semi-defective chip by applying this embodiment. It is a wafer map which shows distribution of the determined chip | tip.

  As shown in this, by performing the additional test (step S14) of this embodiment, some chips that were originally determined to be non-defective are re-determined as defective. Although the defective chip is determined to be a non-defective product, there is a high possibility that the defective chip is potentially defective. Therefore, except for such defective chips, the remaining good chips are unlikely to become defective in the market or the like, and the good chips can be taken out without discarding the semiconductor wafer.

  As described above, by applying the present embodiment, it is possible to take out non-defective chips that are unlikely to be defective later from the wafer, and it is not necessary to dispose of the wafer, thereby increasing cost efficiency.

(2) Second Embodiment The present embodiment is different from the first embodiment in the processing contents of step S9 and step S10.

  12 and 13 are schematic diagrams for explaining the processing contents of steps S9 and S10 in the present embodiment.

  In the present embodiment, as shown in FIG. 12, a coefficient is given in advance to the chip 27 adjacent to the non-defective chip 20.

  There is no particular limitation on the method of applying the coefficient. However, since the chips 27 adjacent to the four sides of the non-defective chip 20 have a greater influence on the good / defective of the non-defective chip 20 than the chips 27 adjacent to the non-defective chip 20 in the diagonal direction, they are adjacent in the diagonal direction as illustrated. It is preferable that the value is higher than that of the chip 27 to be processed.

  FIG. 14 shows another example of how to assign coefficients.

  Then, as described in step S8 of the first embodiment, among the chips 27, those determined as defective chips are classified into marginal defects and sudden defects, and these are shown on the wafer map in FIG. In this way, the colors are displayed.

  In FIG. 13, only margin-related defects are shown in order to make the drawing easier to see. Further, instead of such color coding, marginal and sudden failure may be displayed separately by symbols such as alphabets and numerals.

Then, in the investigation of the distribution of margin defective chips in step S9, the sum S of coefficients of the chips 27 adjacent to the non-defective chips 20 that are margin defective chips is obtained, and the sum is equal to or greater than a predetermined value D _1. Investigate whether or not.

When the predetermined value D ₁ is 3, in the example of FIG. 13, the total sum S is 3.5 (= 1.0 + 1.0 + 1.0 + 0.5), so the total sum S is equal to or greater than the predetermined value D ₁ .

Determining Thereafter, in step S10, the total sum S is a good chip 20 determines that the quasi nondefective when less than a predetermined value D _1, the sum S is the true good chip non-defective chip 20 when less than the predetermined value D _1.

In this example, since the sum S (= 3.5) is equal to or greater than the predetermined value D ₁ (= 3), the non-defective chip 20 is determined as a semi-defective product.

  The subsequent steps are the same as in the first embodiment.

According to the present embodiment described above, a coefficient is given in advance to the chip 27 adjacent to the non-defective chip 20. If the sum S of the coefficients of the margin defective chips among the chips 27 is equal to or greater than the predetermined value D ₁ , a large number of margin defective chips exist around the good chips 20, and the good chips 20 Potentially bad. Therefore, in that case, by handling the non-defective chip 20 as a semi-defective product, it is possible to reserve the non-defective chip 20 on the market and the like, and it is possible to reduce the number of chips that are subsequently defective in the market.

  In addition, regarding the assignment of coefficients to the chip shown in FIG. 12, margin-related defects may be further divided into a plurality of categories, and the coefficient values may be changed according to the categories. The category in this case includes the test items shown in FIG.

  Among the test items shown in FIG. 3, the test target for the power supply terminal may potentially make the adjacent chip defective if it becomes defective compared to the test for other terminals. Is expensive.

  Therefore, for margin-type defective chips that have failed in test items that have power supply terminals as test targets, the coefficient should be higher than those that have failed in test items that have terminals other than power supply terminals as test targets. preferable. In this way, by changing the coefficient for each test item, it is possible to determine the effect of a marginal defective chip on the adjacent non-defective chip, taking into account the test item, and whether or not the non-defective chip is a semi-defective chip. Can be determined more accurately.

(3) Third Embodiment In the present embodiment, Step S9 and Step S10 are performed as follows using the coefficient of the chip described in the second embodiment (FIG. 12).

  FIG. 15 is a schematic diagram for explaining the processing contents of steps S9 and S10 in the present embodiment.

  In this embodiment, in step S9, among the chips 27 adjacent to the non-defective chip 20, the centers of the marginal defective ones are connected with line segments, and the number of line segments crossing the non-defective chip 20 and the weighting factor F Find the product P. The weighting factor F is not particularly limited, but is set to 0.2 in the present embodiment, for example.

Furthermore, among the chips 27 adjacent to the non-defective chip 20, the total sum S of the coefficients of those defective margin system, the sum of the sum S and the product P to investigate whether a predetermined value D ₂ or more.

  In the illustrated example, since the number of line segments crossing the non-defective chip is 2, the product P of the weighting factor F and the number of the line segments is 0.4 (= 2 × 0.2). Further, since the total sum S is 3.5 (= 1.0 + 1.0 + 1.0 + 0.5), the sum of the total sum S and the product P is 3.9.

The predetermined value D ₂ may be the same or different and the predetermined value D ₁ of the second embodiment, but in this embodiment a 3, for example. In this case, the sum (= 3.9) of the sum S and the product P is equal to or greater than a predetermined value D ₂ (= 3).

Thereafter, in step S10, the good chip 20 when the sum of the sum S and product P is equal to or greater than a predetermined value D ₂ determines a quasi non-defective, if the sum of the sum S and product P is less than the predetermined value D ₂ The non-defective chip 20 is determined as a true non-defective chip.

In this example, since the sum (= 3.9) of the sum S and the product P (= 3.9) is equal to or greater than the predetermined value D ₂ (= 3) as described above, the non-defective chip 20 is determined as a semi-defective product.

  The subsequent steps are the same as in the first embodiment.

  According to the present embodiment described above, the centers of marginal defective chips are connected by line segments as shown in FIG. At this time, as the number of line segments crossing the non-defective chip 20 increases, the non-defective chip 20 is predicted to exhibit the same tendency as the peripheral margin-type defective chip in its electrical characteristics. Can be guessed.

  Therefore, it is possible to determine whether or not the non-defective chip 20 is a semi-defective product by taking into account the number of line segments crossing the non-defective chip 20 in this way. The non-defective chips 20 determined to be semi-defective products can be kept out of the market and the like, and the number of chips that are subsequently defective in the market or the like can be reduced.

(4) 4th Embodiment In this embodiment, compared with 1st-3rd Embodiment, only the process after step S15 differs.

  FIG. 16 is a flowchart showing the method for manufacturing the semiconductor device according to this embodiment.

  In this embodiment, as shown in FIG. 16, when it is determined in step S15 that the non-defective chip is not passed in the additional test (NO), the process proceeds to step S20.

  In step S20, it is determined whether the quality required for the chip is high grade (first quality) or lower grade (second quality) lower than that.

  Here, the high-grade chip is used for a device related to human life such as in-vehicle use. On the other hand, low-grade chips, such as audio equipment and toys, do not affect human life even if they break down.

  If a high-grade quality is required for a chip that is determined not to pass the additional test, there is a risk that if the chip is put on the market, the chip will become defective later and cause a serious accident.

  Therefore, if it is determined in step S20 that it is a high grade, the chip is discarded without being put on the market.

  On the other hand, if it is determined that the grade is low grade in step S20, the risk of causing a serious accident is low even if the chip becomes defective later, so the chip is shipped as a low grade product.

  Thus, the basic steps of the semiconductor device according to this embodiment are completed.

  According to the above-described embodiment, for a chip that is determined not to pass in the additional test, it is determined in step S20 whether it is a high grade or a low grade. When the high grade is determined, the chip is discarded in step S22, so that the risk that the chip will be on the market and cause a serious accident can be reduced. If it is determined that the grade is low grade, the product is shipped as a low grade product in step S21. Therefore, it is possible to effectively use the chip that is judged not to pass the additional test.

  The features of the present invention are added below.

(Appendix 1) Classifying defective chips on a semiconductor wafer determined to be defective based on a predetermined test into a first defect mode and a second defect mode;
Investigating the distribution of defective chips belonging to the first defective mode existing around non-defective chips on the semiconductor wafer determined to be non-defective based on the predetermined test;
Based on the distribution, it is determined whether the non-defective chip is a first-type non-defective chip or a second-type non-defective chip.

(Supplementary Note 2) In the investigation, whether or not the number of the defective chips in the first defective mode existing adjacent to the non-defective chips is a predetermined number or more,
In the determination, when the number of the defective chips is equal to or greater than the predetermined number, the non-defective chip is determined as the first type non-defective chip, and when the number of the defective chips is less than the predetermined number, the good chip 2. The method for manufacturing a semiconductor device according to appendix 1, wherein the second type non-defective chip is determined.

(Supplementary Note 3) A coefficient is given in advance to a chip adjacent to the non-defective chip,
In the investigation, a total of the coefficients of defective chips belonging to the first defective mode among chips adjacent to the non-defective chip is obtained, and whether the total is equal to or greater than a predetermined value is investigated.
In the determination, when the total is equal to or greater than the predetermined value, the non-defective chips are determined as the first type non-defective chips, and when the total is less than the predetermined value, the non-defective chips are determined as the second type non-defective chips. The method of manufacturing a semiconductor device according to appendix 1, wherein the determination is made.

(Supplementary Note 4) In the investigation, among the chips adjacent to the non-defective chip, the centers of the defective chips belonging to the first defective mode are connected with line segments, and the number of the line segments crossing the non-defective chip and the weight coefficient , And investigate whether the sum of the product and the sum is greater than or equal to the predetermined value,
In the determination, when the sum is not less than the predetermined value, the non-defective chip is determined as the first type non-defective chip, and when the sum is less than the predetermined value, the non-defective chip is determined as the second type non-defective chip. The method of manufacturing a semiconductor device according to attachment 3, wherein the determination is made.

(Supplementary Note 5) When the defective chip is classified into the first defective mode and the second defective mode, the first defective mode is further divided into a plurality of categories,
4. The method of manufacturing a semiconductor device according to appendix 3, wherein the value of the coefficient is changed according to the category.

  (Additional remark 6) The manufacturing method of the semiconductor device of Additional remark 3 characterized by making the coefficient of the chip | tip adjacent to the four sides of the said non-defective chip higher than the coefficient of the chip adjacent to the diagonal direction of the said non-defective chip.

(Appendix 7) For the non-defective chip determined to be the first type, an additional test with a stricter pass condition than the predetermined test is performed,
Additional notes 1 to 6, wherein the non-defective chip determined to be acceptable in the additional test is determined to be a true non-defective chip, and the non-defective chip determined to be unacceptable in the additional test is determined to be a defective chip. The manufacturing method of the semiconductor device in any one.

  (Additional remark 8) In the said additional test, the said acceptance conditions are made severe by making test temperature higher than in the said predetermined test, The manufacturing method of the semiconductor device of Additional description 7 characterized by the above-mentioned.

  (Additional remark 9) In the said additional test, the said pass conditions are made severe by widening the guarantee range of an operating voltage or an operating current rather than in the said predetermined test, The semiconductor device of Additional remark 7 characterized by the above-mentioned. Production method.

  (Additional remark 10) It is judged whether the quality requested | required of the said non-defective chip | tip determined to be unacceptable by the said additional test is 1st quality or 2nd quality lower than it. The non-defective chip determined to be rejected is determined to be discarded when it is determined to be of the quality, and the non-defective chip determined to be rejected when determined to be of the second quality. 10. The method for manufacturing a semiconductor device according to any one of appendix 7 to appendix 9, wherein:

(Appendix 11) In the first failure mode,
Power supply current measurement,
Quiescent current measurement of power supply,
High level measurement of output terminal,
LOW level measurement of output terminal,
Input terminal leakage current measurement,
Leakage current measurement from input terminal to GND terminal,
Leakage current measurement from power supply terminal to input terminal,
Measurement of leakage current at the input and output terminals of the BUS circuit,
Appendices 1 to 10 including a defective chip that is determined to be a defective chip in any one of the measurement of leakage current from a measured terminal to a GND terminal and the measurement of leakage current from a power supply terminal to a measured terminal A method for manufacturing a semiconductor device according to any one of the above.

(Supplementary note 12) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 11, wherein the second failure mode includes a defective chip that is determined to be a defective chip due to adhesion of foreign matter.

(Additional remark 13) It has the calculation part which inputs the test signal in a predetermined | prescribed test to the semiconductor chip formed in the semiconductor wafer, and performs the pass / fail judgment of this semiconductor chip,
The calculation unit is
Classifying the defective chip determined to be defective in the pass / fail determination into a first defect mode and a second defect mode;
Investigate the distribution of defective chips belonging to the first defective mode existing around non-defective chips determined to be non-defective in the pass / fail determination,
Based on the distribution, it is determined whether the non-defective chip is a first-type non-defective chip or a second-type non-defective chip.

(Supplementary Note 14) The calculation unit
For the non-defective chip determined to be the first type, an additional test with a stricter pass condition than the predetermined test is performed,
Item 14. The supplementary note 13, wherein the non-defective chip determined to be acceptable in the additional test is determined to be a true non-defective chip, and the non-defective chip determined to be unacceptable in the additional test is determined to be a defective chip. Semiconductor test equipment.

(Supplementary Note 15) The stage has a function of heating the semiconductor wafer,
15. The semiconductor test apparatus according to appendix 14, wherein in the additional test, the pass condition is made stricter by controlling the stage to raise a test temperature higher than in the predetermined test. .

  (Additional remark 16) The said calculation part makes the said pass conditions severe by widening the guarantee range of an operating voltage or an operational current in the said additional test rather than in the said predetermined test, It is characterized by the above-mentioned. Semiconductor device testing equipment.

FIG. 1 is a configuration diagram of a semiconductor test apparatus according to the first embodiment of the present invention. FIG. 2 is a flowchart showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a diagram illustrating a circuit margin. FIG. 4 is a diagram showing an example of a wafer map in the first embodiment of the present invention. FIG. 5 is an enlarged view (No. 1) of a wafer map centering on five non-defective chips to be tested in the first embodiment of the present invention. FIG. 6 is an enlarged view (No. 2) of the wafer map centering on the five non-defective chips to be tested in the first embodiment of the present invention. FIG. 7 is an enlarged view (No. 3) of the wafer map centering on the five non-defective chips to be tested in the first embodiment of the present invention. FIG. 8 is a graph showing the yield of semiconductor wafers in a certain product type. FIG. 9 is a wafer map showing the distribution of defective chips of wafer grade WG2. FIG. 10 is a wafer map showing the distribution of defective chips of wafer grade WG3. FIG. 11 is a wafer map obtained by applying the first embodiment of the present invention to the wafer grade WG3 wafer of FIG. FIG. 12 is a schematic diagram (part 1) illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 13 is a schematic diagram (part 2) illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 14 is a diagram showing another example of how to assign coefficients in the second embodiment of the present invention. FIG. 15 is a schematic view showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention. FIG. 16 is a flowchart showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor test apparatus, 2 ... Stage, 3 ... Probe card, 4 ... Probe, 5 ... Calculation part, 7 ... Memory | storage part, 8 ... Display part, 20 ... Non-defective chip | tip, 22 ... Margin type defective chip, 23 ... Suddenly Defective chip of system, 27 ... adjacent chip of good chip, W ... semiconductor wafer, E ... terminal.

Claims (4)

Classifying defective chips on a semiconductor wafer determined to be defective based on a predetermined test into a first defect mode and a second defect mode;
Investigating the distribution of defective chips belonging to the first defective mode adjacent to non-defective chips on the semiconductor wafer determined to be non-defective based on the predetermined test,
On the basis of the distribution, have rows determines whether said non-defective second type of good chips or chip and the first type of good chips,
For the non-defective chip determined to be the first type, an additional test with a stricter pass condition than the predetermined test is performed,
A method of manufacturing a semiconductor device, wherein the non-defective chip determined to be acceptable in the additional test is determined as a true non-defective chip, and the non-defective chip determined to be unacceptable in the additional test is determined as a defective chip. . In the investigation, investigating whether the number of the defective chips in the first defective mode existing adjacent to the non-defective chips is a predetermined number or more,
In the determination, when the number of the defective chips is equal to or greater than the predetermined number, the non-defective chip is determined as the first type non-defective chip, and when the number of the defective chips is less than the predetermined number, the good chip 2. The method of manufacturing a semiconductor device according to claim 1, wherein the second type non-defective chip is determined. In the first failure mode,
Power supply current measurement,
Quiescent current measurement of power supply,
High level measurement of output terminal,
LOW level measurement of output terminal,
Input terminal leakage current measurement,
Leakage current measurement from input terminal to GND terminal,
Leakage current measurement from power supply terminal to input terminal,
Measurement of leakage current at the input and output terminals of the BUS circuit,
Leakage current measurement from the measured terminal to the GND terminal, and claim 1 or, characterized in that contains one defective chip is determined as defective chip in the test of the leak current measurements to be measured terminal from the power supply terminal 3. A method for manufacturing a semiconductor device according to any one of 2 above. The semiconductor chip formed on the semiconductor wafer has a calculation unit that inputs a test signal in a predetermined test and makes a pass / fail judgment on the semiconductor chip,
The calculation unit is
Classifying the defective chip determined to be defective in the pass / fail determination into a first defect mode and a second defect mode;
Investigate the distribution of defective chips belonging to the first defective mode adjacent to the non-defective chips determined to be non-defective in the acceptance / rejection determination,
On the basis of the distribution, have rows determines whether said non-defective second type of good chips or chip and the first type of good chips,
For the non-defective chip determined to be the first type, an additional test with a stricter pass condition than the predetermined test is performed,
A semiconductor test apparatus characterized in that the non-defective chip determined as acceptable in the additional test is determined as a true non-defective chip, and the non-defective chip determined as unacceptable in the additional test is determined as a defective chip .

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