JP3888938B2 - Chip quality judgment method, chip quality judgment program, marking mechanism using the same, and wafer abnormality analysis method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a chip quality determination method for determining the quality of a chip on a wafer in a manufacturing process of a semiconductor device (also referred to as a chip), a chip quality determination program, a marking mechanism using the program, and a wafer abnormality occurrence analysis method It is about.
[0002]
[Prior art]
In the semiconductor device manufacturing process, after pattern formation in each process, an electrical property test (wafer test) is performed for each chip in the wafer state to determine whether it is good or defective and to mark defective products (defective chips). There is a process. Of course, the chips that are marked as defective chips depend on the wafer test results. However, experience shows that if defective chips are concentrated on a part of the wafer, even if the chip is determined to be non-defective in the wafer test, the chip adjacent to the defective concentrated portion cannot guarantee sufficient quality. ing. Therefore, when defective chips are concentrated on a part of the wafer, such a wafer has been discarded in order to maintain the quality.
[0003]
However, depending on the distribution of defects, chips that can guarantee sufficient quality may exist on the same wafer. In order to relieve such a wafer, the wafer test result is visually confirmed, the non-defective chip adjacent to the defective concentration portion is regarded as a defective chip, and a mark for recognizing the defective chip is marked. Hereinafter, the work of marking a non-defective chip adjacent to the defective concentration portion as a defective chip and recognizing the defective chip is referred to as additional ink strike.
[0004]
There are two types of additional ink striking methods: a direct ink striking method and a wafer test result processing method. The former method is used when the inker function of the test prober is used, and the latter method is used when the ink probe is used with a dedicated prober (hereinafter referred to as a marking prober) without using the inker function of the test prober. Is used.
[0005]
In the method in which ink is directly applied to a wafer, an additional ink application operation is performed on a chip that may have a quality problem while observing the wafer test result or the inked wafer itself.
In the method of processing the wafer test result, additional ink is applied to the problematic chip by looking at the wafer test result data developed on the screen by dedicated software (program).
[0006]
However, although it is for guaranteeing quality, it is a drawback that both operations require a great amount of man-hours. In addition, since the selection of problematic chips is made based on sensory judgment based on experience, individual differences have occurred.
[0007]
As a result of investigating the prior art, there were JP-A-8-274139, JP-A-60-42664, JP-A-5-267417, JP-A-11-233581, etc. regarding the wafer test process. No. 1 relates to sampling inspection for increasing the throughput of the wafer test process, and there is nothing related to additional ink hitting.
[0008]
[Problems to be solved by the invention]
A semiconductor device becomes a product through various processes. Various abnormalities at the time of processing in the various processes are factors that cause yield reduction and quality reduction. There are various forms of abnormalities.For example, the effects of abnormalities depend on chip separation, such as insufficient exposure within the shot range by a stepper in the photoengraving process, but most are due to abnormal discharge in the etching process. It does not depend on the chip separation. Further, the influence of the abnormality tends to decrease as the majority of the abnormality that does not depend on the division of the chip is away from the abnormality center.
[0009]
Usually, after completion of processing in each process, a wafer test is performed to remove defective chips. The wafer test is performed in order to mark the chip affected by the abnormality generated in each process in order to remove it in the assembly process.
[0010]
If a wafer test determines that the chip is defective, the cause is an abnormality that depends on the chip separation described above. Quality is guaranteed because it is not affected by
[0011]
However, in the case of an abnormality that does not depend on the above-mentioned chip separation as described above, the quality of the adjacent good product chip may be affected by the abnormality and the quality cannot be guaranteed. Thus, it is unreasonable to ship only products that can guarantee quality based only on wafer test results.
[0012]
Therefore, conventionally, when an abnormality is found in the manufacturing process, depending on the degree of the abnormality, the entire wafer has been discarded in order to guarantee the quality as described above. In the wafer test process, the wafers on which defective chips are concentrated are discarded. This guarantees the quality of the product, but the loss due to the destruction of the wafer is inevitable. Further, this loss tends to increase as the wafer diameter increases in recent years.
[0013]
On the other hand, in situations where it is difficult to secure the number of orders if the wafers are discarded, if an abnormality is discovered during the manufacturing process, a report detailing the abnormal situation is created, and the wafer continues processing. Yes. After a wafer test, if a chip that is estimated to be likely to be affected by an abnormality is determined to be a non-defective chip by the wafer test, On the other hand, additional ink strikes are performed and removed. In addition, in a wafer test process, additional ink is applied to the non-defective chips adjacent to the defective chip concentration distribution and removed from the wafer in which the defective chips are determined to be concentrated distribution based on the operator's empirical determination. I am doing so.
[0014]
This guarantees quality, but there is a problem that individual differences occur because the selection of a chip that is likely to be a problem performed by the operator to perform additional ink strike is made based on sensory judgment based on experience. there were. Furthermore, a large number of man-hours are required to select a problem-prone chip, and this man-hour tends to increase as the wafer diameter increases.
[0015]
A first object of the present invention is to provide a chip quality determination method, a program thereof, and a marking mechanism capable of determining the quality of a chip while guaranteeing the quality in a wafer having a defective chip in part.
A second object of the present invention is to provide a method for analyzing the occurrence of an abnormality of a wafer using information obtained by the chip quality determination method of the present invention.
[0016]
[Means for Solving the Problems]
The first aspect of the chip quality determination method of the present invention is: Wafer test step for determining good and defective products of all chips in the wafer, and Based on wafer test results In the wafer test, each chip determined as a non-defective chip is used as a determination target chip. Multiple chips within the set range near the judgment target chip of The number of defective chips, number of non-defective chips, defect rate or non-defective rate For each chip to be judged A first index calculating step for calculating as a first index, and a determination target chip by comparing a first threshold value set in advance with the first index Every A determination step of determining the quality of the image.
[0017]
Experience has shown that the more defective chips in the vicinity of the determination target chip, the lower the quality of the determination target chip. When the number of defective chips or the defective rate is used as the first index, the first index increases as the number of defective chips in the set range near the determination target chip increases. When the number of non-defective chips or the non-defective product rate is used as the first index, the first index decreases as the number of defective chips within the set range near the determination target chip increases. In the determination step, the quality of the determination target chip can be determined by comparing the first threshold value set to an appropriate value with the first index obtained in the first index calculation step.
[0018]
In the first aspect of the chip quality determination method, examples of the setting range include eight chips surrounding the determination target chip. In addition, for example, 5 × 5 chips centering on the determination target chip can be used. However, the setting range is not limited to these.
[0019]
In the first aspect of the chip quality determination method, the determination target chip is preferably only a non-defective chip. As a result, the number of determination target chips can be reduced and the processing time can be shortened by calculating the first index and determining the quality only for chips determined as non-defective chips based on the wafer test result.
[0020]
The second aspect of the chip quality determination method of the present invention is: Wafer test step for determining good and defective products of all chips in the wafer, and A first index calculating step for calculating, as a first index, the number of defective chips, the number of non-defective chips, the defect rate, or the non-defective ratio for a plurality of chips within a set range near the determination target chip based on the wafer test result, the above setting When using the number of defective chips or the defective rate as the first index within the range or a setting range different from the setting range, when using the maximum number of the first index and the number of non-defective chips or the ratio of non-defective products as the first index Includes a second index calculating step for calculating the minimum first index as the second index, and a determination step for comparing the second threshold value set in advance with the second index to determine the quality of the determination target chip. Including.
[0021]
The second index represents the largest concentration failure distribution within the set range. When the number of defective chips or the defect rate is used as the first index, the first index increases as the number of defective chips in the set range near the determination target chip increases, and the second index also increases. When the number of non-defective chips or the non-defective product rate is used as the first index, the first index decreases as the number of defective chips in the set range near the determination target chip decreases, so the second index also decreases. In the determination step, the quality of the determination target chip can be determined by comparing the second threshold value set to an appropriate value with the second index obtained in the second index calculation step.
[0022]
In the second aspect of the chip quality determination method, the determination step compares a first threshold value set in advance with the first index, compares the first threshold value with the first index, and It is preferable to determine the quality of the determination target chip based on a comparison result between the second threshold value and the second index. As a result, the determination accuracy can be improved.
[0023]
In the first aspect and the second aspect of the chip quality determination method, when the number of defective chips is used as the first index in the first index calculation step and the virtual chip area is within the set range, a preset index Add the value for the number of virtual chip areas, or use the number of non-defective chips as the first index, and if there is a virtual chip area within the set range, set a preset index value for the number of virtual chip areas. It is preferable to calculate the first index by subtracting only. As a result, the determination accuracy can be improved.
In this specification, the virtual chip area refers to an area corresponding to a chip that is included in the setting range but does not exist in the layout.
[0024]
Furthermore, it is preferable that the first index calculating step calculates the first index with a chip within a defective chip frequent occurrence range where defective chips occur frequently on a plurality of wafers as non-defective chips or virtual chip regions. As a result, the determination accuracy can be improved.
[0025]
Further, before the first index calculating step, an adjacent defective chip detecting step for determining whether there is a defective chip adjacent to the target defective chip for each defective chip based on the wafer test result, In the 1-index calculation step, it is preferable to calculate the first index using the defective chip determined as having no adjacent defective chip in the adjacent defective chip detection step as a non-defective chip or a virtual chip area. As a result, the determination accuracy can be improved. In this specification, a chip adjacent to a specific chip refers to eight chips surrounding the specific chip.
[0026]
The third aspect of the chip quality determination method of the present invention is: Wafer test step for determining good and defective products of all chips in the wafer, and Based on the wafer test results Check for the presence of adjacent defective chips for each defective chip so that adjacent defective chips belong to the same group A defective chip sorting step for classifying defective chips into defective groups; for the defective group, the number of defective chips belonging to the defective group is compared with a preset number of defective chips, and the number of defective chips is the number of defective chips A concentration failure distribution determination step for determining the failure group as a concentration failure distribution when the threshold value is equal to or greater than the threshold value or greater than the threshold value of the number of failure chips, and within a predetermined range from the failure chips belonging to the concentration failure distribution. A determination step of determining a certain chip as a defective chip is included.
[0027]
Based on the continuity on the coordinates, the continuity on the coordinates of the defective chips when the defective chips are classified into defective groups is determined by whether or not there are defective chips in the eight chips surrounding a certain defective chip. . For example, in the case of a linear concentration failure distribution such as a scratch, the peeled pattern is often scattered around the scratch, and the peeled pattern may cause a reduction in chip quality. Therefore, the quality of non-defective chips can be guaranteed by determining a chip within a predetermined range from a defective chip belonging to the concentrated defect distribution as a defective chip. Here, examples of the predetermined range include a chip adjacent to any defective chip belonging to the concentrated defect distribution.
[0028]
In the third aspect of the quality determination method, the concentration failure distribution determination step obtains a rectangular range on the coordinates where defective chips are distributed for the defect group, and the number of chips on the longer side of the rectangular range is the rectangle. If the number of chips in the range is greater than a predetermined ratio, the number of chips on the shorter side in the rectangular range is less than the ratio determined in advance to the number of chips on the longer side. When the number of chips on the longer side in the range is larger than a predetermined ratio with respect to the number of chips on the shorter side, the ratio of defective chips within the rectangular range is smaller than a predetermined ratio, or When the ratio of non-defective chips in the square range is larger than a predetermined ratio, it is preferable to determine the defective group as a concentrated defect distribution. As a result, a linear concentration failure distribution can be detected. Since the linear concentration failure distribution is often caused by scratches, a chip that may be affected by quality degradation due to a pattern peeled off by scratches can be determined as a defective chip.
[0029]
Furthermore, it is preferable that the defective chip classification step performs defective group classification of defective chips by using, as non-defective chips, chips within a defective chip frequent occurrence range where defective chips occur frequently on a plurality of wafers. As a result, it is possible to prevent the defective chip frequent occurrence range from being erroneously detected as the concentration failure distribution, and to improve the determination accuracy.
[0030]
Further, before the defective chip classification step, an adjacent defective chip detection step for determining, for each defective chip, whether there is a defective chip adjacent to the target defective chip based on a wafer test result, the defective chip In the classification step, it is preferable to perform defective group classification of the defective chips by using the defective chip determined to have no adjacent defective chip in the adjacent defective chip detection step as a non-defective chip. As a result, the number of defective chips whose continuity should be determined in the defective chip sorting step can be reduced, and the processing time can be shortened.
[0031]
The fourth aspect of the chip quality determination method of the present invention is: Wafer test step for determining good and defective products of all chips in the wafer, and A third index for calculating, as a third index, the number of defective chips, the number of non-defective chips, the defect rate or the non-defective rate for a plurality of chips in the shot range for each shot range based on the wafer test result and the shot layout information in the photoengraving process. An index calculation step, and a determination step of comparing the third threshold value set in advance with the third index to determine the chip quality for each shot range.
[0032]
When defective chips are concentrated in one shot range, the cause of the failure is the exposure failure in the shot range in the photoengraving process or the adhesion of foreign matter to the backside of the wafer corresponding to the shot range. Often. In such a case, there is a high possibility that there is a problem in quality even if there is a non-defective chip within the same shot range. By calculating a third index such as the number of defective chips for a plurality of chips in the shot range for each shot range, and comparing the preset third threshold and the third index, the chip quality for each shot range Therefore, a good chip that is likely to have a quality problem due to an exposure failure or the like can be determined as a defective chip, and the quality of the chip can be guaranteed.
[0033]
In the fourth aspect of the chip quality determination method, the number of defective chips, the number of non-defective chips, the defect rate, or the non-defective rate is calculated as a fourth index for a plurality of chips adjacent to the shot range determined as the defective shot range in the determination step. Preferably, the method includes a fourth index calculating step and a determination step of comparing the fourth index with a preset fourth threshold value to determine the quality of a chip adjacent to the shot range. Here, the defective shot range refers to a shot range in which a certain number or more of defective chips are present in the shot range.
[0034]
A chip adjacent to the defective shot range may be affected by the cause of the defective shot. Therefore, a fourth index such as the number of defective chips is calculated for a plurality of chips adjacent to the defective shot range, and a plurality of chips adjacent to the defective shot range are compared with a preset fourth threshold value and the fourth index. By determining whether or not the chip is affected by the cause of the defective shot, it is possible to determine that a non-defective chip that is likely to be affected by the cause of the defective shot is defective, and to guarantee the quality of the chip be able to.
[0035]
The chip quality determination method of the present invention First reference example Calculates the number of defective chips, the number of non-defective chips, the defective rate or the non-defective rate as a fifth index for each layout position in the shot range in a plurality of shot ranges based on the wafer test result and shot layout information in the photoengraving process. A fifth index calculating step, and a determination step of comparing the fifth index with a preset fifth threshold and determining the chip quality for each layout position within the shot range. Here, the shot position layout position refers to a chip area within a shot range including a plurality of chip areas.
[0036]
A defective chip may occur at a layout position within a specific shot range in a plurality of shot ranges due to an exposure failure in a specific portion within the shot range in the photolithography process. In this case, there is a possibility that there is a problem in the quality even if it is determined as a non-defective chip in the wafer test at the layout position within the shot range where defective chips are generated at a ratio higher than a certain reference. Therefore, a fifth index such as the number of defective chips is calculated for each layout position in the shot range in a plurality of shot ranges, and a fifth threshold value set in advance for each layout position in the shot range is compared with the fifth index. By determining a defect at a layout position within a specific shot range due to an exposure defect or the like, a non-defective chip that is likely to have a quality problem due to an exposure defect at a specific portion within the shot range is determined as a defective chip. Can guarantee the quality of the chip.
[0037]
The chip quality determination method of the present invention Second reference example Is a sixth index for calculating, as a sixth index, the number of defective chips, the number of non-defective chips, the defect rate, or the non-defective product ratio for chips within the defective chip frequent occurrence range where defective chips occur frequently on a plurality of wafers based on the wafer test results. A calculation step and a determination step of comparing the sixth threshold value set in advance with the sixth index to determine the quality of the chip within the defective chip frequent occurrence range.
[0038]
In a specific product, defective chips may frequently occur within a specific range in each lot and each wafer. In this specification, such a specific range is referred to as a defective chip frequent occurrence range. If there is a defective chip exceeding a certain standard within the defective chip frequent occurrence range, there is a possibility that there is a problem in quality even if it is determined as a non-defective chip in the wafer test. Therefore, a sixth threshold value such as the number of defective chips is calculated for the chips within the defective chip frequent occurrence range, and the sixth threshold value set in advance is compared with the sixth index to obtain the defective chip frequent occurrence range. If there is a defective chip exceeding a certain standard, a good chip within the defective chip frequent occurrence range can be determined as a defective chip, and the quality of the chip can be guaranteed.
[0039]
In the first aspect and the second aspect of the chip quality determination method, in the first index calculation step, the fourth station of the chip quality determination method On the face It is preferable to calculate the first index using a non-defective chip determined as a defective chip and a defective chip used as a determination material as a non-defective chip or a virtual chip region. As a result, the determination accuracy can be improved in the first aspect and the second aspect of the chip quality determination method.
[0040]
In the third aspect of the chip quality determination method, in the defective chip classification step, the fourth station of the chip quality determination method On the face It is preferable to perform defective group classification of defective chips by using a non-defective chip determined as a defective chip and a defective chip used as a determination material as non-defective chips. As a result, in the third aspect of the chip quality determination method, the determination accuracy can be improved, and the processing time can be further shortened.
[0041]
In the first aspect, the second aspect, and the third aspect of the chip quality determining method including the adjacent defective chip detecting step, the fourth station of the chip quality determining method in the adjacent defective chip detecting step. On the face It is preferable to determine whether there is a defective chip adjacent to the target defective chip, with the non-defective chip determined as a defective chip and the defective chip used as the determination material as non-defective chips. As a result, in the adjacent defective chip detection step of the first aspect, the second aspect, and the third aspect of the chip quality determination method, the determination accuracy can be improved and the processing time can be further shortened.
[0042]
In the chip quality determination method of the present invention, the regions on the wafer are divided into regions, and the first threshold value, the second threshold value, the third threshold value, and the fourth threshold value that are different for each region ,or Preferably uses a threshold value for the number of defective chips. As a result, for example, on the outer peripheral side of the wafer, there are many problems in the quality of the chip as compared with the central side. The quality can be determined, and the reliability of the determination can be improved.
[0043]
As a wafer test result used in the chip quality determination method of the present invention, a final wafer test result, a plurality of wafer test results for each test item, or a plurality of wafer test results for each test item group including a plurality of test items are listed. be able to.
[0044]
In general, in the case of the same abnormality in the same manufacturing process, there is a tendency that it is determined to be defective with almost the same test items. Therefore, the determination accuracy may be improved by performing determination for each test item of the wafer test in the chip quality determination method of the present invention. However, the processing for each test item takes too much time, and when there are multiple test items, in order to shorten the time required for the wafer test, the test items after that are usually judged as defective at one test item. Will not be tested. Therefore, the test items may be grouped, and the wafer test result for each test item group may be used in the chip quality determination method of the present invention. There may be duplication of items for grouping test items. Rather, by duplicating items, it is possible to alleviate problems caused by not testing subsequent items when it is determined to be defective.
[0045]
The chip quality determination program of the present invention is for causing a computer to execute each step of the chip quality determination method of the present invention. As a result, the chip quality determination method of the present invention can be carried out using a computer, and it is possible to eliminate a large amount of man-hours that have conventionally been devoted to selecting problematic chips. Improve the judgment criteria that depended on experience.
[0046]
The marking mechanism of the present invention includes a marking unit for marking a target position on a wafer and a control unit for controlling the operation of the marking unit, and the control unit includes the chip quality determination program of the present invention. The marking unit is operated so as to mark the wafer position corresponding to the chip determined as a defective chip by the chip quality determination program of the present invention.
As a result, if judgment conditions such as a threshold value are input in advance, the quality of the chip is judged while guaranteeing the quality in a wafer having a defective chip in part, and the chip determined to be a defective chip is automatically Can be marked with.
[0047]
A first aspect of the wafer abnormality occurrence analysis method according to the present invention includes first index information, second index information, concentration failure distribution information, third index information obtained by the chip quality determination method according to the present invention, Or Fourth index information ,or Collects these combinations for a plurality of wafers, and identifies locations where defective chips are likely to occur on the wafers based on the collected information.
[0048]
Each piece of information obtained by the chip quality determination method of the present invention represents a defect distribution, and when combined with the coordinate information of the chip, the position information can be determined. Therefore, by using the information obtained by the chip quality determination method of the present invention, it is possible to specify a location where a defective chip is likely to occur on the wafer.
[0049]
The second aspect of the wafer abnormality analysis method of the present invention is the first index information, the second index information, the concentration failure distribution information, the third index information obtained by the chip quality determination method of the present invention, Or Fourth index information ,or Collects these combinations for a plurality of wafers, further collects processing history information and / or processing apparatus information in the manufacturing process for each wafer, and determines a defect generation process or a defect generation processing apparatus based on the collected information. Investigate.
[0050]
Each piece of information obtained by the chip quality determination method of the present invention represents a defect distribution, and when combined with the coordinate information of the chip, the position information can be determined. Therefore, the defect generation process can be determined by using the information obtained by the chip quality determination method of the present invention and the processing history information in the manufacturing process. Further, by using the information obtained by the chip quality determination method of the present invention and the processing device information, a defect occurrence processing device can be investigated.
[0051]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described together with illustrated examples. The present invention is a method for determining the quality of a chip while guaranteeing the quality in additional ink hitting performed to relieve a wafer having a defective chip in part, and systematizes the chip quality determination method using a computer. This guarantees the quality of the product without sacrificing the loss due to wafer destruction and the great man-hours. First, a chip quality determination method for an additional ink strike target chip, that is, a chip that may have a quality problem will be described. Since there are various methods for determining the chip quality, each will be described.
[0052]
FIG. 1A shows an example of the final wafer test result of the wafer test process, and FIG. 1B shows the first of each chip calculated in the first index calculation step of the first aspect of the chip quality determination method of the present invention. Index A is shown. FIG. 1 is a diagram for explaining an embodiment of the first aspect of the chip quality determination method of the present invention.
[0053]
For example, 120 chips are arranged vertically and horizontally on the wafer 1. The position of each chip on the wafer 1 is clarified by X coordinate information 2 and Y coordinate information 3. For example, the non-defective chip 4 is at the position of coordinates (14, 11). A chip determined to be a non-defective chip in the wafer test result is indicated by no mark like the non-defective chip 4, and a chip determined to be a defective chip is indicated by a cross mark such as the defective chip 5.
[0054]
When defective chips are distributed as shown in FIG. 1A, experience shows that good chips to be subjected to additional ink are defective chips adjacent to each other, such as good chips 6 and good chips 7. There are many chips. The non-defective chip 8 also has three defective chips adjacent to the non-defective chip 7 as in the case of the non-defective chip 7.
[0055]
In order to mechanically determine the additional ink strike target chip (chip quality determination) instead of empirically, the first index A of the determination target chip is obtained based on the coordinate information and the wafer test result. For example, the setting range in the vicinity of the determination target chip used for the calculation of the first index A is eight chips surrounding the determination target chip, and the number of defective chips included in the eight chips is obtained as the first index A (first index A). 1 index calculation step). Here, the first index A was calculated only for non-defective chips in order to shorten the processing time. However, the first index A may be calculated for all chips including defective chips.
[0056]
For example, the chips adjacent to the non-defective chip 6 in FIG. 1 are eight chips shown in FIG. Regarding the non-defective chip 6, since there are six defective chips in the adjacent eight chips, the first index A of the non-defective chip 6 is “6”.
[0057]
FIG. 1B shows the result of obtaining the first index A for all good chips on the wafer 1 individually. In addition, there are chips that do not surround the number of chips in the vicinity of the outer periphery of the wafer 1, for example, the non-defective chips 7 that surround three chips and the non-defective chips 8 that surround seven chips. In contrast, the number of defective chips is simply obtained and set as the first index A.
[0058]
In each chip, the first index A increases as the number of adjacent defective chips increases. Experience has shown that the quality deteriorates as the number of defective chips in adjacent chips increases. Therefore, the first threshold A is set for the first index A, and the first index A is the first threshold. When it is A or more, it can be determined that the quality of the non-defective chip is low (determination step).
[0059]
For example, if the threshold value is “4”, a non-defective chip having a first index A of “4” or more is determined as a defective chip and set as an additional ink strike target chip. The non-defective chip 6 that should be the target of additional ink experi- ence has a first index A of “6”, and thus becomes a chip for additional ink striking. Such processing of the first index calculation step and the determination step can be mechanically performed using a computer.
[0060]
However, since the first index A is “3” for the non-defective chip 7 that should be the target of additional ink experientially, it is determined as a non-defective chip and excluded from the additional ink striking target. If the first threshold value A is changed and a chip whose first index A is “3” or more is targeted, the non-defective chip 8 that is not originally targeted for additional ink strike becomes the target for additional ink strike. End up. This is a problem in layout when the first index A is obtained.
[0061]
This defect can be overcome by using, for example, the ratio (defective rate) of defective chips in the surrounding chips instead of the number of defective chips in the chips surrounded by the first index A. For example, if a chip with a first index A of 50% or more, which is a defect rate, is targeted for additional ink strike, the good chip 7 of FIG. 1 may be targeted for additional ink strike because the first index A is 100%. it can.
[0062]
There is also a method of performing compensation when there is a virtual chip area within a set range in the vicinity of the determination target chip. That is, the first index A is added not only when the chip within the set range is a defective chip but also when it is a virtual chip area.
For example, FIG. 3 shows a result of obtaining the first index A by adding 0.5 to the first index A of FIG. 1B by 0.5 for each virtual chip area.
[0063]
When the first threshold value A is set to “4” with respect to the first index A shown in FIG. 4, the non-defective chip 6 and the non-defective chip 7 can be subjected to additional ink strike, and the non-defective chip 8 is It can be excluded from additional ink strikes.
[0064]
Hereinafter, a chip quality determination method for determining the quality of each good chip based on the first index A obtained from the number of defective chips surrounding the good chip will be referred to as algorithm 1A.
The algorithm 1A will be described with reference to the flowchart of FIG.
[0065]
The coordinate information and wafer test result information of each chip is read (step S1), and the first index A is calculated based on the coordinate information and wafer test result information of each chip (step S2). The threshold value A is compared to make an additional ink strike determination to identify an additional ink strike target chip (step S3).
[0066]
The wafer test result is corrected, and a corrected wafer test result including marking data for the entire wafer including the specified additional ink application target chip or marking data for only the specified additional ink application target chip is created (step S4). The created marking data is sent to a tester or a marking prober equipped with a marking mechanism, and ink printing is performed.
[0067]
In the algorithm 1A, the numerical value of the first threshold value A and the degree of compensation in the virtual chip area when the number of defective chips is used as the first index A are changed according to the type of product and the process capability of the production line. May be. Further, as the first index A, in addition to the number of defective chips and the defective rate, the number of non-defective chips or the non-defective product rate within the set range may be used. When the number of non-defective chips is used as the first index A, if there is a virtual chip area within the set range, the first index A is calculated by subtracting a preset index value by the number of virtual chip areas.
[0068]
FIG. 5A shows an example of the final wafer test result of the wafer test process, and FIG. 5B shows the first of each chip calculated in the first index calculation step of the first aspect of the chip quality determination method of the present invention. Index B is shown. FIG. 5 is a diagram for explaining another embodiment of the first aspect of the chip quality determination method of the present invention.
[0069]
For example, 120 chips are arranged vertically and horizontally on the wafer 1. The position of each chip on the wafer 1 is clarified by X coordinate information 2 and Y coordinate information 3. For example, the non-defective chip 4 is at the position of coordinates (14, 11). A chip determined to be a non-defective chip in the wafer test result is indicated by no mark like the non-defective chip 4, and a chip determined to be a defective chip is indicated by a cross mark such as the defective chip 9.
[0070]
From experience, when defective chips are distributed as shown in FIG. 5A, the coordinates (X, Y) of the chips to be subjected to additional ink strike are (8, 6), (8, 8), (9,5), (9,9), (11,5), (11,9), (12,6), (12,8) and so on, eight chips surrounding a concentrated defect distribution, Or it becomes a chip which encloses further. When the operator determines the additional ink strike target chip, defective chips of (7, 12), (8, 11), (9, 12), (11, 12) are distributed alone. Therefore, it is not taken into consideration when examining the additional ink strike target chip.
[0071]
In order to mechanically determine the additional ink strike target chip instead of empirically, the first index B of the determination target chip is obtained based on the coordinate information and the wafer test result. For example, the setting range in the vicinity of the determination target chip used for calculating the first index B is 25 chips (5 × 5 chips) centering on the determination target chip, and the number of defective chips included in the 25 chips is the first index. Obtained as B (first index calculation step). Here, the first index B was calculated for all chips including defective chips. However, the first index B may be calculated only for non-defective chips.
[0072]
For example, the setting range for the non-defective chip 10 in FIG. 5 is 25 chips shown in FIG. Since there are six defective chips in the 25 chips, the first index B of the non-defective chip 10 is “6”. FIG. 5B shows the result of obtaining the first index B individually for all chips on the wafer 1 including defective chips. In addition, there is a chip in which the number of chips in the set range is not 25 near the outer periphery of the wafer 1, for example, a non-defective chip 4 having 9 chips in the set range. Of these, the number of defective chips is obtained and set as the first index B. In FIG. 5B, in order to make it easy to understand the position of the defective chip, the defective chip is marked with, for example, a defective chip 9.
[0073]
The first index B increases as the number of defective chips increases within the set range. Experience has shown that the closer the defective chips are to the denser range, the lower the quality is. Therefore, if the first index B is equal to or higher than the first threshold value B, it is determined that the quality of the good chip is low. can do.
[0074]
For example, if the first threshold value B is set to “8”, a non-defective chip having a first index B of “8” or more is determined as a defective chip and set as an additional ink strike target chip (determination step). The eight chips (8, 6), (8, 8), (9, 5), (9, 9), (11, 5), (8) to be subjected to additional ink strikes as described above based on experience. 11, 9), (12, 6), and (12, 8) are all chips for additional ink application since the first index B is “8” or more.
[0075]
Hereinafter, a chip quality determination method for determining the quality of each good chip based on the first index B obtained from the number of defective chips in the set range near the determination target chip is referred to as algorithm 1B.
The algorithm 1B will be described with reference to the flowchart of FIG.
[0076]
The coordinate information and wafer test result information of each chip is read (step S11), and the first index B is calculated based on the coordinate information and wafer test result information of the chip within the set range in each chip (step S12). The index B and the first threshold value B are compared to make an additional ink strike determination to identify an additional ink strike target chip (step S13).
[0077]
The wafer test result is corrected, and a corrected wafer test result including marking data for the entire wafer including the specified additional ink strike target chip or only the specified additional ink strike target chip is created (step S14). The created marking data is sent to a tester or a marking prober equipped with a marking mechanism, and ink printing is performed.
[0078]
The first index B used in the algorithm 1B may be a ratio (defective rate) of defective chips to chips within a set range. When the defect rate is used, similarly to the algorithm 1A, it is possible to improve a defect with respect to chips near the wafer outer periphery in which the virtual chip area is included in the set range.
[0079]
Further, the virtual chip area may be compensated as in algorithm 1A. However, the actual problem is that the algorithm 1B performs the virtual chip area compensation process in the algorithm 1A to obtain the first index A, and the algorithm 1B obtains the first index A and the algorithm 1B. When the second index B is used in combination, the data processing speed is faster and the detection accuracy (determination accuracy) of the additional ink strike target chip is higher.
[0080]
In Algorithm 1B, the value of the first threshold value B and the degree of compensation in the virtual chip area when the number of defective chips is used as the first index B are changed according to the type of product and the process capability of the production line. May be. Further, as the first index B, in addition to the number of defective chips and the defective rate, the number of non-defective chips or the non-defective rate of chips within a set range may be used.
[0081]
In the first index B of FIG. 5 (B), if the threshold value of the first index B is “8”, the chip located at the coordinates (9, 10) also has the first index B “8”. It becomes a chip targeted for ink hitting. This is due to the influence of defective chips of coordinates (7, 12), (8, 11), (9, 12), (11, 12) that should be ignored when applying the algorithm 1B.
[0082]
As a method for solving such a problem, an embodiment of the second aspect of the chip quality determination method of the present invention will be described.
In order to improve the determination accuracy of the additional ink application target chip, the maximum first index B within the set range for each chip is obtained as the second index based on the coordinate information and the first index B (second index calculation) Step). In this embodiment, a range of 25 chips (5 × 5 chips) centering on the determination target chip is used as the setting range.
[0083]
For example, the setting range for the non-defective chip 10 in FIG. 5 is 25 chips shown in FIG. FIG. 8 shows the first index B of each chip within the set range of the non-defective chip 10. As can be seen from FIG. 8, the maximum first index B within the set range for the non-defective chip 10 is “13”. Therefore, the second index of the non-defective chip 10 is “13”.
[0084]
FIG. 9 shows the results of obtaining the second index for all the chips on the wafer 1. In FIG. 9, in order to make it easy to understand the position of the defective chip, the defective chip is marked with, for example, a defective chip 9. When a chip near the outer periphery of the wafer 1 includes a virtual chip area within the set range, the maximum first index B of the chips within the set range excluding the virtual chip area is set as the second index.
[0085]
A threshold value (second threshold value) is provided in the second index, and a non-defective chip whose second index is equal to or greater than the second threshold value is determined as a defective chip and is set as an additional ink strike target chip (determination step).
[0086]
The second index shown in FIG. 9 represents the largest concentration failure distribution within the set range of each chip. That is, when the second index is high, there is a large concentration failure distribution within the set range of the chip.
Hereinafter, a technique for determining the quality of each good chip based on the second index obtained from the first index B within the set range for each chip is referred to as algorithm 2.
[0087]
Algorithm 2 can be used alone by providing a threshold value (second threshold value) in the second index, but the detection accuracy of the additional ink strike target chip is not so high. Therefore, it is preferable to use the first index B of the algorithm 1B and the AND condition. Here, the AND condition refers to determining that the condition is satisfied when all of the two or more conditions are satisfied.
[0088]
For example, in the case of the wafer test result shown in FIG. 5A, the first index B shown in FIG. 5B is “8” or more, and the second index shown in FIG. 9 is “13” or more. A non-defective chip is set as an additional ink hitting target chip. As a result, coordinates (8, 6), (8, 8), (9, 5), (9, 9), (11, 5), (11, 9), (12, 6) surrounding the concentrated defect distribution. ), (12, 8) can be determined by setting the 8 chips as targets for additional ink hitting, and the chip at coordinates (9, 10) as a target for additional ink hitting.
[0089]
A chip quality determination method using the algorithm 1B and the algorithm 2 under the AND condition will be described with reference to the flowchart of FIG.
The coordinate information and wafer test result information of each chip are read (step S21).
[0090]
The first index B is calculated based on the wafer test result information of the chips within the set range in each chip by the algorithm 1B (step S22).
By algorithm 2, the maximum first index B within the set range in each chip is obtained as the second index (step S23).
[0091]
For each chip, the first index B is compared with the first threshold value B, the second index is compared with the second threshold value, and the additional ink strike determination is performed under the AND condition to identify the additional ink strike target chip. (Step S24).
[0092]
The wafer test result is corrected, and a corrected wafer test result including marking data for the entire wafer including the specified additional ink strike target chip or only the specified additional ink strike target chip is created (step S25). The created marking data is sent to a tester or a marking prober equipped with a marking mechanism, and ink printing is performed.
[0093]
FIG. 11A shows an example of a final wafer test result of the wafer test process, and FIG. 11B shows a determination result according to an embodiment of the third aspect of the chip quality determination method of the present invention.
On the wafer 1, 120 chips are arranged vertically and horizontally. The position of each chip on the wafer is clarified by X coordinate information 2 and Y coordinate information 3. For example, the non-defective chip 4 is at the position of coordinates (14, 11). A chip determined as a non-defective chip based on the wafer test result is indicated by no mark like the non-defective chip 4, and a chip determined as a defective chip is indicated by a cross mark as the defective chip 11.
[0094]
The defective chips shown in FIG. 11 are distributed linearly. The cause of such a distribution (linear concentration failure distribution) is often caused by scratches in the manufacturing process, and peeled patterns are often scattered around the scratches. A chip including a peeled pattern may be determined as a defective chip in the wafer test, but may remain as a defect that is not determined as a defective chip in the wafer test. In other words, there is a possibility that it becomes a non-defective chip with suspected quality. Therefore, when a linear concentration failure distribution is found through experience, as shown by a circle in FIG. 11B, a chip adjacent to one of the defective chips in the linear concentration failure distribution, that is, a linear concentration failure distribution. The chip that surrounds is targeted for additional ink strikes.
[0095]
In order to determine the additional ink strike target chip mechanically instead of empirically, it is necessary to first group the chips into consecutive defective chips based on the coordinate information and the wafer test result. For each defective chip in the wafer, the presence of adjacent defective chips is confirmed to confirm the continuity and clarify which defective group each defective chip belongs to (defective chip classification step).
[0096]
Next, it is determined whether or not the distribution of defects is such that it is necessary to consider additional ink strikes. For example, the threshold value for the number of defective chips is set to five, and the concentrated defect distribution is determined based on whether or not the defective group includes five or more defective chips. Furthermore, the linearity of the concentration failure distribution is determined (concentration failure distribution determination step). For example, there are three methods for determining the linearity of the concentration failure distribution.
[0097]
In the first method, a rectangular range on coordinates is obtained based on coordinate information for the concentration failure distribution to be determined, and the number of chips on the longer side of the rectangular range is predetermined with respect to the number of chips in the rectangular range. If the ratio is larger than the specified ratio, it is determined as a linear concentration failure distribution.
[0098]
The second method obtains a rectangular range on the coordinates based on the coordinate information for the concentration failure distribution to be determined, and in advance the number of chips on the shorter side in the rectangular range in advance. When the ratio is smaller than the predetermined ratio, or when the number of chips on the longer side in the square range is larger than a predetermined ratio with respect to the number of chips on the shorter side, the distribution is determined to be linear concentration failure.
[0099]
The third method obtains a rectangular range on the coordinates based on the coordinate information for the concentration failure distribution to be determined, and when the ratio of defective chips in the rectangular range is smaller than a predetermined ratio, or in the rectangular range When the ratio of non-defective chips is larger than a predetermined ratio, it is determined as a linear concentration failure distribution.
[0100]
When it is determined that the concentration failure distribution is a linear concentration failure distribution, a non-defective chip adjacent to any failure chip in the linear concentration failure distribution is set as an additional ink target (determination step, ○ mark in FIG. 11B). reference). By implementing such processing using a computer, it is possible to mechanically identify linear non-conformity distributions and identify non-defective chips that may have been affected by quality degradation due to the cause of the linear concentration failure distribution. Can be done.
[0101]
Hereinafter, a method of determining the quality of each good chip based on the above-described defective chip classification step, concentrated defect distribution determination step, and determination step is referred to as algorithm 3.
Even in the concentration failure distribution that is not determined to be linear by the algorithm 3, a non-defective chip adjacent to the defective chip or a non-defective chip within the set range may be set as an additional ink strike target. However, in that case, it may be better to leave it to the determination of another algorithm.
[0102]
The algorithm 3 will be described with reference to the flowchart of FIG.
The coordinate information and wafer test result information of each chip is read (step S31).
In each chip, the defective chips are grouped based on the wafer test result information of the adjacent chips to clarify the defective group to which each defective chip belongs (step S32).
[0103]
The size determination of each defect group is performed to determine whether the distribution of defects is such that additional ink strike needs to be examined (step S33). Furthermore, it is determined whether the defect distribution is a shape distribution that needs to be examined for additional ink hitting by determining the shape of each defective group (deciding whether it is linear) (step S34).
[0104]
Based on the result of the determination of the size of each defective group (step S33) and the result of the determination of the shape of each defective group (step S34), additional ink strike determination is performed to determine a defective group that requires additional ink strike, and additional ink strike is performed. A target chip is specified (step S35).
[0105]
The wafer test result is corrected, and a corrected wafer test result including marking data for the entire wafer including the specified additional ink application target chip or marking data for only the specified additional ink application target chip is created (step S36). The created marking data is sent to a tester or a marking prober equipped with a marking mechanism, and ink printing is performed.
[0106]
In this embodiment, non-defective chips adjacent to any defective chip in the linear concentration defect distribution are targeted for additional ink strike, but the third aspect of the chip quality determination method of the present invention is not limited to this. Further, non-defective chips within a predetermined range set in advance from any defective chip in the linear concentrated defect distribution, for example, within a range of 5 × 5 chips centered on the defective chip, may be the target of additional ink strike.
[0107]
FIG. 13 shows an example of the final wafer test result of the wafer test process for explaining an embodiment of the fourth aspect of the chip quality determination method of the present invention.
On the wafer 1, 120 chips are arranged vertically and horizontally. The position of each chip on the wafer is clarified by X coordinate information 2 and Y coordinate information 3. For example, the non-defective chip 4 is at the position of coordinates (14, 11). A chip determined as a non-defective chip based on the wafer test result is indicated by no mark like the non-defective chip 4, and a chip determined as a defective chip is indicated by an X mark as the defective chip 12. A range surrounded by a thick frame in the wafer 1 is a one-shot range in the exposure process of the photoengraving process in the semiconductor device manufacturing process. Within the one-shot range, there are 2 chips in the X direction and 3 chips in the Y direction. Has been placed.
[0108]
In the wafer test result shown in FIG. 13, defective chips are concentrated in the shot range to which the defective chip 12 belongs. That is, the distribution is concentrated in a specific shot range. The cause of such a distributed defect is often an exposure defect in a specific shot range in the photoengraving process, and there is often a problem in quality even if there is a non-defective chip in the same shot range. Therefore, experience shows that additional ink is applied to all non-defective chips in the shot range where there was a poor exposure.
[0109]
In order to determine the additional ink strike target chip mechanically instead of empirically, first, based on the coordinate information, the wafer test result, and the shot layout information, for example, the yield (for example, non-defective product rate) for each shot range on the wafer 1 is determined. Obtained as the third index (third index calculation step).
[0110]
When the third index of the determination target shot range is lower than a predetermined yield (third threshold), it is determined as a defective shot range due to exposure failure, and all good chips in the defective shot range are determined as defective chips. Determination is made as a target for additional ink strike (determination step).
Here, the yield is used as the third index, but the defect rate, the number of defective chips, or the number of non-defective chips within the shot range may be used as the third index.
[0111]
Further, in the partial resolution failure in the wafer that occurs when foreign matters are attached to the back surface of the wafer, the failure distribution as shown in FIG. 13 is obtained. In this case, even in the shot range adjacent to the defective shot range, there is a possibility that the chip near the defective shot range is affected by the exposure failure.
[0112]
Therefore, for example, the number of defective chips of 14 chips adjacent to the defective shot range is obtained as the fourth index (fourth index calculating step).
If there are more defective chips than the preset fourth threshold value, the chips adjacent to the shot range determined to be defective in exposure are also subjected to additional ink strike (determination step).
Here, the number of defective chips is used as the fourth index, but a defective rate, a non-defective product rate, or a non-defective chip number may be used.
[0113]
Hereinafter, the chip quality determination method for determining the quality of the chip within the determination target shot range and the quality of the chip adjacent to the defective shot range by the third index calculation step and the determination step and the fourth index calculation step and the determination step. The chip quality judgment method for judging the above is called algorithm 4.
[0114]
The algorithm 4 will be described with reference to the flowchart of FIG.
The coordinate information and wafer test result information of each chip are read (step S41).
The shot layout information is read and it is clarified to which shot range each chip belongs (step S42).
[0115]
The yield is obtained for each shot range (step S43), the shot range of the problematic level yield is clarified by the additional ink strike determination, and a chip that needs additional ink strike is specified (step S44).
[0116]
The number of defective chips is calculated for the chips adjacent to the shot range determined to be the defective shot range in step S44 (step S45). (Step S46).
[0117]
The wafer test result is corrected, and a corrected wafer test result including marking data for the entire wafer including the specified additional ink strike target chip or only the specified additional ink strike target chip is created (step S47). The created marking data is sent to a tester or a marking prober equipped with a marking mechanism, and ink printing is performed.
[0118]
FIG. 15 shows the chip quality determination method of the present invention. First reference example of One case An example of the final wafer test result of the wafer test process for explaining the above is shown.
On the wafer 1, 120 chips are arranged vertically and horizontally. The position of each chip on the wafer is clarified by X coordinate information 2 and Y coordinate information 3. For example, the non-defective chip 4 is at the position of coordinates (14, 11). A chip determined as a non-defective chip based on the wafer test result is indicated by no mark like the non-defective chip 4, and a chip determined as a defective chip is indicated by an X mark as the defective chip 13. A range surrounded by a thick frame in the wafer 1 is a one-shot range in the exposure process of the photoengraving process in the semiconductor device manufacturing process. Within the one-shot range, there are 2 chips in the X direction and 3 chips in the Y direction. Has been placed.
[0119]
In the wafer test result shown in FIG. 18, the defects are concentrated at a specific shot range layout position of each shot range. The cause of such a distributed defect is often a defective exposure at a specific shot range layout position in the photoengraving process, and it is assumed that a non-defective chip exists at the same shot range layout position of another shot range. Often there are problems with quality. Therefore, from experience, when a defective chip is found at the same shot range layout position in a plurality of shot ranges, additional ink is applied to the non-defective chip for the layout positions within the shot range in all shot ranges.
[0120]
In order to determine the additional ink strike target chip mechanically instead of empirically, first, for each shot range in the wafer, for each shot range in the shot range, based on the coordinate information, the wafer test result, and the shot layout information. For example, the yield (for example, non-defective product rate) is obtained as the fifth index (fifth index calculation step).
[0121]
When the fifth index is lower than a predetermined yield (fifth threshold), it is determined that the exposure is defective at the layout position within the shot range, and the non-defective chips at the layout position within the shot range of all shot ranges are determined. It is set as a target for additional ink strike (determination step).
Here, the yield is used as the fifth index, but the defect rate, the number of defective chips, or the number of non-defective chips at the layout positions within each shot range may be used.
[0122]
Hereinafter, the chip quality determination method for determining the quality of the chip for each layout position within the shot range by the fifth index calculation step and the determination step will be referred to as algorithm 5.
[0123]
The algorithm 5 will be described with reference to the flowchart of FIG.
The coordinate information and wafer test result information of each chip are read (step S51).
The layout information is read, and it is clarified where in the shot range each chip belongs to the layout position in the shot range (step S52).
[0124]
A yield is determined for each layout position within the shot range (step S53), the layout position within the shot range at the problematic level of yield is clarified by additional ink strike determination, and a chip that requires additional ink strike is specified (step S54).
[0125]
The wafer test result is corrected, and a corrected wafer test result including marking data of the entire wafer including the specified additional ink strike target chip or only the specified additional ink strike target chip is created (step S55). The created marking data is sent to a tester or a marking prober equipped with a marking mechanism, and ink printing is performed.
[0126]
FIG. 17 shows the chip quality determination method of the present invention. Second reference example of One case An example of the final wafer test result of the wafer test process for explaining the above is shown.
On the wafer 1, 120 chips are arranged vertically and horizontally. The position of each chip on the wafer is clarified by X coordinate information 2 and Y coordinate information 3. For example, the non-defective chip 4 is at the position of coordinates (14, 11). A chip determined as a non-defective chip based on the wafer test result is indicated by no mark like the non-defective chip 4, and a chip determined as a defective chip is indicated by an X mark as the defective chip 14.
[0127]
Although most of the non-defective chips to be subjected to additional ink strike can be detected by the algorithms 1A, 1B, 2, 3, 4 and 5 described so far, as shown in FIG. In reality, for example, many of the Y coordinate 3 chips in each wafer are defective chips. Regardless of the cause, this is a tendency of defects inherent in varieties. In the case of the wafer test result shown in FIG. 17, the experience additional chip to be applied with ink is a good chip with coordinates (7, 3).
[0128]
However, if the algorithms 1A, 1B, 2, 3, 4 and 5 described so far are applied, the coordinates (8, 3) and (9, 3) are determined by the algorithm 3, for example, depending on the setting of the threshold value. , (10, 3), (11, 3) and (12, 3) are determined to be a linear concentration failure distribution, and coordinates (7, 3), (7, 4), (8, 4) , (9, 4), (10, 4), (11, 4), and (12, 4) non-defective chips become additional ink strike target chips.
[0129]
In this way, when defective chips are concentrated in a specific range (defective chip frequent occurrence range) specific to the product, the defective chip frequent occurrence range is stored as information in advance, and for example, the yield of the defective chip frequent occurrence range is calculated as the sixth index. However, if the yield is lower than a predetermined yield (sixth threshold value), all non-defective chips within the defective chip frequent occurrence range are set as additional ink strike target chips (determination step).
Here, the yield is used as the sixth index, but the defect rate, the number of defective chips, or the number of non-defective chips at the layout positions within each shot range may be used.
[0130]
The information on the defective chip frequent occurrence range held here may be coordinate information representing the range, or may be coordinate information on chips belonging to the defective chip frequent occurrence range. In the case where the coordinate information of chips belonging to the defective chip frequent occurrence range is held, a range or the like for chips that are obliquely continuous in coordinates can be set, so that a flexible range can be specified.
[0131]
Hereinafter, the chip quality determination method for determining the quality of non-defective chips within the defective chip frequent occurrence range based on the preset yield within the defective chip frequent occurrence range by the sixth index calculation step and determination step will be referred to as algorithm 6.
[0132]
The algorithm 6 will be described with reference to the flowchart of FIG.
The coordinate information and wafer test result information of each chip is read (step S61).
The defective chip frequent occurrence range information is read, and the chips belonging to the defective chip frequent occurrence range are clarified (step S62).
[0133]
The yield in the defective chip frequent occurrence range is obtained (step S63).
It is determined whether or not the yield of the defective chip frequent occurrence range is equal to or greater than a threshold value, and additional ink strike determination is performed to identify a chip that requires additional ink strike (step S64).
[0134]
The wafer test result is corrected, and a corrected wafer test result including the marking data of the entire wafer including the specified additional ink hitting target chip or the marking data of only the specified additional ink hitting target chip is created (step S65). The created marking data is sent to a tester or a marking prober equipped with a marking mechanism, and ink printing is performed.
[0135]
When executing the algorithms 1A, 1B, 2, 3, 4, and 5, it is preferable to process chips in the defective chip frequent occurrence range as non-defective chips or virtual chip areas. As a result, for example, a defect in the algorithm 3 caused by a defective chip in the defective chip frequent occurrence range as described above, such as a defect in the algorithm 1A, 1B, 2, 3, 4, 5 due to a defective chip in the defective chip frequent occurrence range. Trouble can be eliminated.
[0136]
The chips to be processed as good chips or virtual chip areas when executing the algorithms 1A, 1B, 2, 3, 4, and 5 may be all chips within the defective chip frequent occurrence range, or within the defective chip frequent occurrence range. Only defective chips may be used, or only chips within the defective chip frequent occurrence range determined as defective chips in a specific wafer test item may be used.
[0137]
Further, when a defective distribution that clearly shows a tendency is found by the algorithm 4 and the algorithm 5, it is preferable to perform additional algorithms by excluding non-defective chips in the defective distribution or defective chips that have become judgment materials. This tends to lead to an improvement in the determination accuracy of the target chip.
[0138]
Further, in the algorithm 1A, the first index A of each good chip is obtained, and then it is determined whether or not there is a defective chip adjacent to each defective chip, and there is no other defective chip adjacent when the algorithm 1B is executed. By calculating the first index B by excluding the defective chip, there is a tendency that the accuracy of specifying the additional ink strike target chip is improved. Furthermore, if a defective chip without other adjacent defective chips is clarified, it can be excluded from the processing target in the algorithm 3 as well, leading to a reduction in processing time.
[0139]
In the foregoing, seven types of algorithms have been described as methods for identifying chips that may have quality problems. Each of the seven types of algorithms has its characteristics. It has been stated earlier that algorithm 1B and algorithm 2 are preferably used under AND conditions. However, the combination of algorithms is not limited to this, and all of the seven types of algorithms or some of them may be used in the AND condition, or all of the seven types of algorithms or of them may be used. Some combinations of these may be used in the OR condition. Thereby, the detection accuracy of the additional ink striking target chip can be increased. Here, the OR condition refers to determining that the condition is satisfied when any one of the two or more conditions is satisfied.
[0140]
For example, when the determination result when the algorithm 1B and the algorithm 2 are used under the AND condition and the determination result of the algorithm 1A are used under the OR condition, if the compensation processing of the virtual chip area is performed with the algorithm 1A, the virtual chip with the algorithm 1B Since detection accuracy can be increased without performing region compensation processing, processing time can be shortened.
Thus, by using a plurality of algorithms together, it is possible to expect an improvement in detection accuracy and an improvement in data processing speed.
[0141]
Further, on the outer peripheral side in the wafer surface, there are many problems in terms of chip quality compared to the central side. Therefore, in order to make the determination of the additional ink strike target chip by the algorithm closer to the result based on experience, it is preferable to change the index calculation method and the threshold value between the outer peripheral side and the central side of the wafer. Hereinafter, the position in the wafer surface where the chip belongs is referred to as an in-wafer positional attribute.
[0142]
As a method of mechanically determining whether each chip belongs to the outer peripheral side or the central side of the wafer using a computer, for example, the relative coordinates from the wafer center of each chip are obtained based on the chip size and the chip layout. The distance from the center of the wafer is obtained using the three-square theorem, and if the distance exceeds a predetermined distance, it can be determined that the chip is near the wafer outer periphery.
[0143]
Actually, since it takes time to calculate the distance from the wafer center in each lot, each wafer, and each chip and determine whether it is near the outer periphery, the positional attribute information in the wafer of each chip is previously stored. It may be stored in a file or database, and the positional attribute in the wafer of the determination target chip may be identified using coordinate information or individual chip information.
[0144]
When holding in-wafer positional attribute information, the in-wafer positional attribute information of each chip may be the result obtained by the above-mentioned three-square theorem, or the result may be partially changed depending on the type of product. However, the three-square theorem may not be applied, and the positional attributes in the wafer may not be two types on the outer peripheral side and the central side.
[0145]
In this way, the in-wafer positional attribute of each chip is identified, and not only whether each algorithm is applied for each in-wafer positional attribute, but also how to determine the index of each algorithm and the threshold value of the discrimination criterion can be changed. it can.
[0146]
Note that algorithm 4 is processed using shot layout information, and algorithm 5 is processed using shot position layout position information. These information can also be calculated using coordinate data, but considering the time required for processing, such information is stored in a file or database and is used using coordinate information or individual chip information. It is most efficient to identify in-wafer positional attributes. The in-wafer positional attribute information, shot layout information, in-shot range layout position information, etc. may be separately stored in a file or database, but may be combined.
[0147]
Further, information unique to a product other than the in-wafer positional attribute information, the shot layout information, and the in-shot layout position information may be set, and each algorithm may be applied.
[0148]
The target of the additional ink strike described above is basically a non-defective chip that is likely to have a quality problem due to the same abnormality in the same manufacturing process. The chip quality determination method of the present invention is to determine a non-defective chip that is likely to have a quality problem using an algorithm based on a wafer test result. In the case of a simple semiconductor device, the test contents are simple and there are few test items. However, in the case of an integrated circuit, the test contents become complicated and the test items increase. In general, in the case of the same abnormality in the same manufacturing process, there is a tendency that it is determined to be defective with almost the same test items.
[0149]
Therefore, when executing the algorithms 1A, 1B, 2, 3, 4, 5, and 6 described above, it is preferable to perform processing using the wafer test results for each test item, not the final wafer test results. In some cases, the detection accuracy can be improved.
[0150]
However, when there are a large number of test items, the processing for each test item takes too much time, which is not realistic. Further, when there are a plurality of test items, in order to shorten the time required for the wafer test, the subsequent test items for the chip are usually not performed when it is determined as a defective chip.
[0151]
Therefore, it is preferable to group test items and specify the target of additional ink strike by executing the above algorithm using the wafer test result for each test item group. Regarding grouping of test items, there may be duplication of test items. Rather, by duplicating the test items, it is possible to alleviate problems caused by the subsequent test items not being performed for the chip when it is determined as a defective chip.
In the above, the embodiment of the chip quality determination method for a chip that may have a quality problem has been described.
[0152]
Next, systematization using a computer will be described.
FIG. 19 is a schematic configuration diagram illustrating an example of a conventional quality determination system. This quality determination system performs ink printing using a marking prober without using the inker function provided in the prober during testing.
[0153]
A wafer is placed on the prober 16, and a wafer test is performed by supplying power and a test signal from the tester 15 with the probe needle in contact with the electrode of the inspection target chip on the wafer. The wafer test result is sent from the prober 16 to the information management workstation 17. The wafer test result may be sent directly to the marking prober 19. However, since a plurality of testers 15, probers 16 and marking probers 19 are usually provided, the wafer test results are temporarily sent to the information management workstation 17. It is more reasonable to collect.
[0154]
The operator confirms the wafer test result at the information management workstation 17 and manually performs additional ink strike determination and creation of marking data. This operation may be performed using the X terminal 18. After confirming the marking object, a lot is placed on the marking prober 19. The marking prober 19 reads the marking data from the information management workstation 17 and performs ink printing on the defective chip based on the wafer test result and the defective chip set by the additional ink hitting determination.
[0155]
FIG. 20 is a schematic configuration diagram illustrating an example of a quality determination system including the marking mechanism of the present invention.
A personal computer 20 is connected to the information management workstation 17. The personal computer 20 is installed with application software incorporating a quality determination program for causing the computer to execute the chip quality determination method of the present invention. Other configurations are the same as those of the quality determination system shown in FIG. Similarly to the quality determination system shown in FIG. 19, the wafer test result is sent from the prober 16 to the information management workstation 17.
[0156]
The wafer test result includes coordinate information of each chip, pass / fail information, defect category information, and the like. The information management workstation 17 associates the wafer test result with shot layout information, shot range layout position information, occurrence of defective chips. Range information and the like are held. The marking prober 19 constitutes the marking part of the marking mechanism of the present invention, and the information management workstation 17, the control part for controlling the operation of the marking prober 19, and the personal computer 20 constitute the control part of the marking mechanism of the present invention. .
[0157]
FIG. 21 shows a flowchart of an example of application software incorporating the quality judgment program of the present invention. This application software displays on the screen of the personal computer 20 an automatic determination result related to the additional ink hitting chip determination by the algorithm described above, and further allows the operator to change the additional ink hitting target chip.
[0158]
First, in wafer test result transfer (step S71), the wafer test result and associated information are transferred from the information management workstation 17 to the personal computer 20 using FTP (File Transfer Protocol) or the like.
[0159]
By reading the wafer test result (step S72), information such as coordinate information of each chip, wafer test result information, and defect category information is read from the wafer test result transferred from the information management workstation 17.
[0160]
By reading the layout information (step S73), the shot layout information, the in-shot range layout position information, the defective chip frequent occurrence range information, etc. are read to clarify the positional attributes of each chip.
[0161]
The first index A, the first index B, and the second index are obtained by the algorithm 1A, the algorithm 1B, and the algorithm 2 (step S74), and defective chips are grouped by the algorithm 3 to obtain defective group information (step S75).
[0162]
Using the coordinate information of each chip as a key, wafer test result information, defect category information, first index A, first index B, second index, defect group information, shot layout information, shot position layout position information, defective chip The frequent occurrence range information and the like are made into a database (step S76).
[0163]
The additional ink strike determination is sequentially performed by the algorithms 1A, 1B, 2, 3, 4, 5, and 6 described above. For example, the first index A is compared with the first threshold value A, the first index B is compared with the first threshold value B, the second index is compared with the second threshold value, and the additional ink strike target chip is specified (step S77). ).
[0164]
Since the information necessary for the additional ink strike determination (step S77) is made into a database by information database conversion (step S76), the scale determination of each defective group in algorithm 3 (see step S33 in FIG. 12). Further, the shape determination of each defective group (see step S34 in FIG. 12), the calculation of the yield for each shot range of algorithm 4 (see step S43 of FIG. 14), and the calculation of the yield for each layout position in the shot range of algorithm 5 (see FIG. 16). The calculation of the yield for each defective chip frequent occurrence range of algorithm 6 (see step S53) (see step S63 in FIG. 18) can be easily obtained using an SQL (Structured Query Language) statement. In the flowchart of FIG. 21, these processes are also included in the additional ink strike determination (step S77).
[0165]
The additional ink strike target chip specified in the additional ink strike determination (step S77) is displayed on the display screen on the screen of the personal computer 20 (step S78). The operator confirms on the screen of the personal computer 20 how the additional ink strike target chip has been specified (step S79).
[0166]
When the operator confirms the determination result (step S79) and the operator determines that there is an excess or deficiency in the specification of the additional ink strike target chip, the algorithm threshold value is input by the operator's manual operation input. Is changed (step S80), the process returns to the additional ink strike determination (step S77), or the additional ink strike target chip is set by the operator's manual operation input (step S81), and then the additional ink strike target The chip is displayed on the display screen on the screen of the personal computer 20 (step S78).
[0167]
The change of the threshold value (step S80) is used when the appropriate additional ink strike target chip identification result cannot be obtained due to inappropriate setting of each threshold value of the algorithm.
The setting of the additional ink strike target chip by manual operation input (step S81) is used to specify the additional ink strike target chip that cannot be handled by the determination using the algorithm.
[0168]
When the operator confirms the determination result (step S79) and the operator determines that the additional ink strike target chip is appropriate, the process proceeds to correction of the wafer test result (step S82). In the correction of the wafer test result (step S82), a corrected wafer test result including marking data including the specified additional ink strike target chip or marking data of only the specified additional ink strike target chip is created. The created corrected wafer test result is transferred to the information management workstation 17 using, for example, FTP (step S83).
[0169]
The corrected wafer test result is sent from the information management workstation 17 to the marking prober 19. Since the marking prober 19 performs ink printing using the marking data (corrected wafer test result) including information on the additional ink application target chip, the additional ink printing information is reflected in the actual ink printing.
[0170]
The above-described configuration of the quality determination system is an example, and various modifications such as operating the quality determination program of the present invention on the information management workstation 17 or the marking prober 19 are possible.
[0171]
As described above, according to the chip quality determination method of the present invention, the quality of a chip can be determined while guaranteeing the quality in a wafer having a defective chip in part. Furthermore, according to the chip quality determination program of the present invention, since each step of the chip quality determination method of the present invention can be executed by a computer, a large number of people who have conventionally been assigned to select problematic chips. It is possible to eliminate the man-hours, and to improve the judgment standard that relies on the experience of the worker. Furthermore, even in a factory that has not performed additional ink strike due to man-hours, the loss due to wafer discard can be reduced by using the additional ink strike system using the marking mechanism of the present invention.
[0172]
Each index information and concentration failure distribution information calculated by the algorithm of the present invention described above is useful information for stabilizing the semiconductor device manufacturing process, and can be collected in a database and used for investigating an abnormality occurrence process.
Conventionally, the data of the wafer test process is the yield and the defect category, and neither of them is information showing the distribution of defects.
Each index information and concentration failure distribution information obtained by the algorithm of the present invention represents a failure distribution, and when combined with the coordinate information of the chip, the position information can be determined.
[0173]
In the wafer abnormality occurrence analysis method of the present invention, each index information and concentrated defect distribution information obtained by the algorithm of the present invention is used to identify a location where a defective chip is likely to occur on the wafer, a defect occurrence process and a defect occurrence. Investigate the processing equipment.
[0174]
For example, the maximum value of the first index B of the algorithm 1B and the chip coordinates of the maximum value in the wafer are stored in the database for all wafers of all lots subjected to the wafer test, regardless of whether or not additional ink is applied. Collecting and accumulating can be used for analysis of locations where the concentration failure distribution is likely to occur.
In addition, if the lot where the concentration failure distribution occurs and the lot where it does not occur are stratified and tied to the processing history and processing equipment in the manufacturing process, the processing device causing the concentration failure distribution and the processing device causing it It can also be used to investigate.
[0175]
The embodiments of the chip quality determination method, the chip quality determination program, the marking mechanism using the chip quality determination method, and the wafer abnormality occurrence analysis method have been described above, but the present invention is not limited thereto, and Various modifications are possible within the scope of the present invention described in.
[0176]
【The invention's effect】
According to the chip quality determination method of the first and second aspects, the first index is used to calculate the number of defective chips as a first index for a plurality of chips within a set range near the determination target chip based on the wafer test result. Since the index calculation step and the determination step of comparing the first threshold value set in advance with the first index to determine the quality of the determination target chip are included, the quality of the determination target chip is ensured while ensuring the quality. Can be determined.
[0177]
In the chip quality determination method according to the third aspect, since the determination target chips are only non-defective chips, the number of determination target chips can be reduced, and the processing time can be shortened.
[0178]
5. The chip quality determination method according to claim 4, wherein the first index calculation calculates the number of defective chips as a first index for a plurality of chips within a set range near the determination target chip based on the wafer test result. A second index calculating step of calculating, as a second index, the first index that is maximum or minimum within the setting range or a setting range different from the setting range, and a preset second threshold value and the above Since the determination step of comparing the second index to determine the quality of the determination target chip is included, the quality of the determination target chip can be determined while guaranteeing the quality.
[0179]
In the chip quality determination method according to claim 5, in the chip quality determination method according to claim 4, the determination step compares a first threshold value set in advance with the first index, and Since the quality of the determination target chip is determined based on the comparison result between the first threshold and the first index and the comparison result between the second threshold and the second index, the determination accuracy is improved. be able to.
[0180]
6. The chip quality determination method according to claim 6, wherein in the chip quality determination method according to any one of claims 1 to 5, in the first index calculation step, the number of defective chips or non-defective chips is used as the first index. When there is a virtual chip area within the set range, the first index is calculated by adding or subtracting a preset index value by the number of virtual chip areas. Accuracy can be improved.
[0181]
8. The chip quality determination method according to claim 7, wherein in the chip quality determination method according to any one of claims 1 to 6, a defective chip in which defective chips frequently occur in a plurality of wafers in the first index calculation step. Since the first index is calculated using a chip in the frequent occurrence range as a non-defective chip or a virtual chip area, the determination accuracy can be improved.
[0182]
In the chip quality determination method according to claim 8, in the chip quality determination method according to any one of claims 1 to 7, before the first index calculation step, a defective chip adjacent to the target defective chip is detected. An adjacent defective chip detecting step for determining whether or not there is, and in the first index calculating step, the defective chip determined as having no adjacent defective chip in the adjacent defective chip detecting step is defined as a non-defective chip or a virtual chip region Since the first index is calculated, the determination accuracy can be improved.
[0183]
10. The chip quality determination method according to claim 9, wherein a defective chip classification step of classifying defective chips into defective groups based on continuity on coordinates based on a wafer test result, and the defective group with respect to the defective group. When the number of defective chips is equal to or larger than the threshold value of the defective chip number or larger than the threshold value of the defective chip number It includes a concentration failure distribution determination step for determining a failure group as a concentration failure distribution, and a determination step for determining a chip within a predetermined range from a failure chip belonging to the concentration failure distribution as a failure chip. However, the quality of the determination target chip can be determined.
[0184]
The chip quality determination method according to claim 10, wherein in the chip quality determination method according to claim 9, the concentration failure distribution determination step is configured to determine a rectangular range on coordinates where the defective chips are distributed for the failure group. If the number of chips on the longer side of the rectangular range is greater than a predetermined ratio with respect to the number of chips in the rectangular range, the side having the longer number of chips on the shorter side in the rectangular range is obtained. If the number of chips on the longer side in the square range is smaller than a predetermined ratio with respect to the number of chips of If the percentage of defective chips in the case is smaller than a predetermined percentage, or if the percentage of non-defective chips in the square range is larger than a predetermined percentage, the defective group is classified as a concentrated defect Therefore, it is possible to detect a linear concentration failure distribution, and to determine a chip that may be affected by quality degradation due to a pattern peeled off by a scratch as a defective chip. it can.
[0185]
The chip quality determination method according to claim 11 is the chip quality determination method according to claim 9 or 10, wherein the defective chip classification step includes a defective chip frequent occurrence range in which defective chips frequently occur in a plurality of wafers. Since a certain chip is regarded as a non-defective chip and defective groups are classified as defective chips, it is possible to prevent erroneous detection of a defective chip frequent occurrence range as a concentrated defect distribution, and to improve determination accuracy.
[0186]
In the chip quality determination method according to claim 12, in the chip quality determination method according to any one of claims 9, 10 and 11, before the defective chip classification step, based on a wafer test result, The defective chip includes an adjacent defective chip detection step for determining whether there is a defective chip adjacent to the target defective chip, and the defective chip classification step determines that there is no adjacent defective chip in the adjacent defective chip detection step. Since the defective chips are classified as good chips, the defective groups are classified into defective groups, so that the number of defective chips whose continuity should be judged in the defective chip classification step can be reduced, and the processing time can be shortened. .
[0187]
In the chip quality determination method according to claim 13, based on the wafer test result and the shot layout information in the photoengraving process, the number of defective chips and the like for the plurality of chips in the shot range for each shot range is set as the third index. Since a third index calculating step for calculating and a determination step for comparing the third index set in advance with the third index to determine the quality of the chip for each of the shot ranges, exposure failure or the like is included. A non-defective chip that is likely to have a problem in quality due to the above can be determined as a defective chip, and the quality of the determination target chip can be determined while ensuring the quality.
[0188]
In the chip quality determination method according to claim 14, in the chip quality determination method according to claim 13, the number of defective chips and the like for a plurality of chips adjacent to the shot range determined as the defective shot range in the determination step. A fourth index calculating step for calculating the fourth index as a fourth index, and a determination step for comparing the fourth index set in advance with the fourth index to determine the quality of the chip adjacent to the shot range. Therefore, a non-defective chip that is highly likely to be affected by the cause of the defective shot can be determined as defective, and the quality of the chip can be guaranteed.
[0191]
Claim 15 In the chip quality determination method described in claim 1, in the chip quality determination method described in any one of claims 1 to 8, the first index calculation step includes: Or 14 Since the first index is calculated as a non-defective chip or a non-defective chip used as a determination material as a non-defective chip determined as a defective chip by the chip quality determination method described in the above, the determination accuracy is improved. be able to.
[0192]
Claim 16 In the chip quality determination method described in any one of claims 9 to 11, in the chip quality determination method described in any one of claims 9 to 11, in the defective chip classification step, Or 14 The defective chip is classified as a non-defective chip determined as a defective chip and a defective chip determined as a determination material by the chip quality determination method described in the above. In the chip quality determination method described in 1), the determination accuracy can be improved and the processing time can be further reduced.
[0193]
Claim 17 In the chip quality determination method described in claim 13, in the chip quality determination method described in claim 8 or 12, in the adjacent defective chip detection step, Or 14 As a non-defective chip determined as a defective chip by the chip quality determination method described in the above and a defective chip used as a determination material, it is determined whether there is a defective chip adjacent to the target defective chip. In the adjacent defective chip detection step of the chip quality determination method according to claim 8 or 12, the determination accuracy can be improved, and the processing time can be further shortened.
[0194]
Claim 18 In the chip quality determination method described in 1), in the chip quality determination method of the present invention, regions on the wafer are divided into regions, and a first threshold value, a second threshold value, a third threshold value, which are different for each region, 4th threshold ,or Since the threshold value of the number of defective chips is used, the reliability of determination can be improved.
[0195]
Claim 19 In the chip quality determination method described in 1), a test item including a final wafer test result, a plurality of wafer test results for each test item, or a plurality of test items as a wafer test result used in the chip quality determination method of the present invention. Since a plurality of wafer test results for each group are used, the determination accuracy can be improved in some cases.
[0196]
Claim 20 In the chip quality determination program described in the above, since each step of the chip quality determination method of the present invention is executed by a computer, the chip quality determination method of the present invention can be implemented using a computer. It is possible to eliminate a great amount of man-hours that have been spent on selecting problematic chips, and to improve the judgment criteria that depend on the experience of the operator.
[0197]
Claim 21 The marking mechanism described in (1) includes a marking unit for marking a target position on the wafer and a control unit for controlling the operation of the marking unit. The control unit executes the chip quality determination program of the present invention. Since the marking unit is operated so as to mark the wafer position corresponding to the chip determined to be a defective chip by the chip quality determination program of the present invention, determination conditions such as a threshold value are input in advance. If this is done, it is possible to determine the quality of a chip while guaranteeing the quality of a wafer with a defective chip in part, and to automatically mark a chip determined to be a defective chip. Can be achieved.
[0198]
Claim 22 In the wafer abnormality occurrence analysis method described in 1), first index information, second index information, concentration failure distribution information, third index information obtained by the chip quality determination method of the present invention, Or Fourth index information ,or Collects these combinations for a plurality of wafers, and based on the collected information, identifies the location where a defective chip is likely to occur on the wafer. Therefore, identifies the location where a defective chip is likely to occur on the wafer. be able to.
[0199]
Claim 23 In the wafer abnormality occurrence analysis method described in 1), first index information, second index information, concentration failure distribution information, third index information obtained by the chip quality determination method of the present invention, Or Fourth index information ,or Collects these combinations for a plurality of wafers, further collects processing history information and / or processing apparatus information in the manufacturing process for each wafer, and determines a defect generation process or a defect generation processing apparatus based on the collected information. Since it was made to investigate, a defect generation process and a defect generation processing apparatus can be investigated.
[Brief description of the drawings]
FIG. 1A is a diagram showing an example of a final wafer test result of a wafer test process, and FIG. 1B is a diagram showing a first index A of each chip calculated by an algorithm 1A.
FIG. 2 is a diagram for explaining an example of a setting range for calculating a first index A.
3 is a diagram showing a result of obtaining the first index A by adding the first index A by 0.5 for each virtual chip area to the first index A of FIG. 1B.
FIG. 4 is a flowchart of algorithm 1A.
5A is a diagram showing an example of a final wafer test result of the wafer test process, and FIG. 5B is a diagram showing a first index B of each chip calculated by an algorithm 1B.
6 is a diagram for explaining an example of a setting range for calculating a first index B. FIG.
FIG. 7 is a flowchart of algorithm 1B.
FIG. 8 is a diagram for explaining an example of a setting range for calculating a second index.
FIG. 9 is a diagram showing a result obtained by obtaining a second index calculated by the algorithm 2;
10 is a flowchart of Algorithm 3. FIG.
11A is a diagram illustrating an example of a final wafer test result of the wafer test process, and FIG. 11B is a diagram illustrating a third index of each chip calculated by the algorithm 3;
12 is a flowchart of Algorithm 3. FIG.
FIG. 13 is a diagram illustrating an example of a final wafer test result of a wafer test process for explaining an algorithm 4;
14 is a flowchart of Algorithm 4. FIG.
15 is a diagram illustrating an example of a final wafer test result of a wafer test process for explaining algorithm 5. FIG.
16 is a flowchart of Algorithm 5. FIG.
FIG. 17 is a diagram illustrating an example of a final wafer test result of a wafer test process for explaining an algorithm 6;
18 is a flowchart of algorithm 6. FIG.
FIG. 19 is a schematic configuration diagram illustrating an example of a conventional quality determination system.
FIG. 20 is a schematic configuration diagram showing an example of a quality determination system including a marking mechanism according to the present invention.
FIG. 21 is a flowchart of an example of application software incorporating the quality determination program of the present invention.
[Explanation of symbols]
1 Wafer
2 X coordinate information
3 Y coordinate information
4,6,7,8 Good quality chip
5 Bad chip

Claims (23)

A wafer test step for determining good and defective products of all chips in the wafer;
Said chips determined as good chips as determination target chip in wafer test based on the wafer test results, defective chips number of a plurality of chips within the setting range in the vicinity of each of the judgment target chip, good chips number, failure rate or the first index calculating step of calculating a yield rate as the first index of each determination target chip, and determining determines the quality of each determination target chip compared with a preset first threshold value the first exponent A chip quality determination method including steps.   The chip quality determination method according to claim 1, wherein the setting range is eight chips surrounding a determination target chip.   The chip quality determination method according to claim 1, wherein the determination target chip is only a non-defective chip. A wafer test step for determining good and defective products of all chips in the wafer;
A first index calculation step of calculating, as a first index, the number of defective chips, the number of non-defective chips, the defect rate, or the non-defective ratio for a plurality of chips within a set range near the determination target chip based on the wafer test result;
When the number of defective chips or the defective rate is used as the first index within the setting range or a setting range different from the set range, the maximum first index and the number of non-defective chips or the non-defective product rate as the first index are used. A second index calculating step for calculating the minimum first index as the second index when used, and a determination for determining the quality of the determination target chip by comparing the second index with a preset second threshold A chip quality determination method including steps.   The determination step compares a first threshold value set in advance with the first index, a comparison result between the first threshold value and the first index, and the second threshold value and the second index. The chip quality determination method according to claim 4, wherein the quality of the determination target chip is determined based on the comparison result.   In the first index calculation step, the number of defective chips is used as the first index, and when there is a virtual chip area within the set range, a preset index value is added by the number of virtual chip areas, or The number of non-defective chips is used as the first index, and when there is a virtual chip area within the set range, the first index is calculated by subtracting a preset index value by the number of virtual chip areas. 6. The chip quality determination method according to any one of 1 to 5.   7. The first index calculation step calculates the first index by using, as a good chip or a virtual chip area, a chip within a defective chip frequent occurrence range where defective chips occur frequently on a plurality of wafers. 8. Chip quality judgment method. Before the first index calculation step, an adjacent defective chip detection step for determining whether there is a defective chip adjacent to the target defective chip for each defective chip based on a wafer test result,
8. The first index calculation step calculates the first index with the defective chip determined to have no adjacent defective chip in the adjacent defective chip detection step as a non-defective chip or a virtual chip region. 9. The chip quality determination method according to 1. A wafer test step for determining good and defective products of all chips in the wafer;
On the basis of the wafer test results, carried out to confirm the presence of the defective chip adjacent each defective chip, adjacent defective chips defective chip sorting step of sorting the defective chip to belong to the same group to the defective group,
For the defective group, the number of defective chips belonging to the defective group is compared with a predetermined defective chip number threshold, and when the number of defective chips is equal to or larger than the defective chip number threshold or the number of defective chips A chip including a concentration failure distribution determination step for determining that the failure group is a concentration failure distribution when the value is greater than a value; and a determination step for determining a chip within a predetermined range from the failure chips belonging to the concentration failure distribution as a failure chip Quality judgment method.   The concentration defect distribution determining step obtains a rectangular range on the coordinates where defective chips are distributed for the defect group, and the number of chips on the longer side of the rectangular range is previously set to the number of chips in the rectangular range. If the ratio is greater than a predetermined ratio, the number of chips on the shorter side in the square range is smaller than the ratio determined in advance with respect to the number of chips on the longer side, and the chip on the longer side in the square range. When the number is larger than a predetermined ratio with respect to the number of chips on the shorter side, the ratio of defective chips within the rectangular range is smaller than a predetermined ratio, or the ratio of non-defective chips within the rectangular range 10. The chip quality determination method according to claim 9, wherein if the value is larger than a predetermined ratio, the defect group is determined to be a concentrated defect distribution.   11. The chip quality determination method according to claim 9, wherein the defective chip classification step performs defective group classification of defective chips by using, as non-defective chips, chips within a defective chip frequent occurrence range where defective chips occur frequently on a plurality of wafers. Before the defective chip classification step, an adjacent defective chip detection step for determining whether there is a defective chip adjacent to the target defective chip for each defective chip based on a wafer test result,
12. The defective chip classification step according to claim 9, wherein the defective chip classification step performs defective group classification of defective chips with the defective chip determined as having no defective chip adjacent in the adjacent defective chip detection step as a non-defective chip. Chip quality judgment method. A wafer test step for determining good and defective products of all chips in the wafer;
Based on the wafer test result and the shot layout information in the photoengraving process, the number of defective chips, the number of non-defective chips, the defective rate or the non-defective rate is calculated as a third index for a plurality of chips within the shot range for each shot range. A chip quality determination method comprising: a 3-index calculation step; and a determination step of comparing a third threshold value set in advance with the third index to determine chip quality for each shot range. A fourth index calculating step for calculating, as a fourth index, the number of defective chips, the number of non-defective chips, the defect rate or the non-defective product rate for a plurality of chips adjacent to the shot range determined as the defective shot range in the determination step; 14. The chip quality determination method according to claim 13, further comprising a determination step of comparing the fourth threshold value and the fourth index to determine the quality of a chip adjacent to the shot range. 15. The first index calculation step uses the first index as a non-defective chip or a virtual chip area, with a non-defective chip determined as a defective chip by the chip quality determination method according to claim 13 or 14 and a defective chip used as a determination material. The chip quality determination method according to claim 1, wherein the chip quality determination method is calculated. 15. The defective chip classification step performs defective group classification of defective chips using a defective chip determined as a defective chip by the chip quality determination method according to claim 13 or 14 and a defective chip used as a determination material as a non-defective chip. The chip quality determination method according to any one of 9 to 12. 15. The adjacent defective chip detection step uses a defective chip determined as a defective chip by the chip quality determination method according to claim 13 or 14 and a defective chip used as a determination material as a non-defective chip, and is adjacent to the target defective chip. The chip quality determination method according to claim 8 or 12, wherein it is determined whether or not there is a chip. The area on the wafer is divided into regions, a first threshold value that is different for each region, a second threshold, third threshold, claim fourth threshold, or using a bad chip number threshold 1 18. The chip quality determination method according to any one of items 1 to 17 . As the wafer test results, the final wafer test results, either a plurality of wafer test results for each test item, or a plurality of wafer test results for each test item group including a plurality of test items claims 1 using 18 The chip quality determination method according to 1. Chip quality determination program for executing the steps according to the computer in any one of claims 1 19. A marking unit for marking a target position on a wafer and a control unit for controlling the operation of the marking unit, the control unit comprising the chip quality determination program according to claim 20 , A marking mechanism that operates the marking unit so as to mark a wafer position corresponding to a chip determined as a defective chip by a chip quality determination program. The first index information calculated in the first index calculation step according to any one of claims 1 to 8, 15, 17 , 18 or 19 , and any one of claims 4 to 8, 15, 17 , 18 or 19. The second index information calculated in the second index calculation step, the concentration failure distribution information obtained in the concentration failure distribution determination step according to any one of claims 9 to 12, or 16 to 19 , claim 13, 18 or third exponent calculated by the third index calculating step described in 19, the fourth index information calculated in the fourth index calculation step of claim 14, 18 or 19, or a plurality of wafers of these combinations A wafer abnormality occurrence analysis method that collects and identifies locations where defective chips are likely to occur on a wafer based on the collected information. The first index information calculated in the first index calculation step according to any one of claims 1 to 8, 15, 17 , 18 or 19 , and any one of claims 4 to 8, 15, 17 , 18 or 19. The second index information calculated in the second index calculation step, the concentration failure distribution information obtained in the concentration failure distribution determination step according to any one of claims 9 to 12, or 16 to 19 , claim 13, 18 or third exponent calculated by the third index calculating step described in 19, the fourth index information calculated in the fourth index calculation step of claim 14, 18 or 19, or a plurality of wafers of these combinations Further, processing history information and / or processing apparatus information in the manufacturing process is collected for each wafer, and based on the collected information, a defect occurrence process or A method for analyzing the occurrence of an abnormality in a wafer to investigate a defect occurrence processing apparatus.

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