JP2006128251A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device by which the quality of a semiconductor device can be improved. <P>SOLUTION: After the qualities of chips mounted on semiconductor wafers are discriminated in a P-inspection 1 step, the presence of defective chips is discriminated on the all semiconductor wafers on which the qualities of the chips are discriminated in the next AUF 1 step. In the AUF 1 step, the presence of the defective chips is discriminated by providing a plurality of discriminating modes (for example, longitudinally and laterally dividing discriminating mode, concentric circular dividing discriminating mode, outer periphery discriminating mode, radially dividing discriminating mode, block detecting discriminating mode, straight line detecting discriminating mode, and straight line summing-up discriminating mode) and, on the semiconductor wafer on which the existence of a defective chip is discriminated, the chips around the defective chip are treated as defective chips in which defective potential exists. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and is particularly effective when applied to an inspection process for determining whether each chip is good or defective in a wafer state after an integrated circuit is formed on a main surface of a semiconductor wafer in units of chips. It is about technology.

  For example, in Japanese Patent Application Laid-Open No. 2003-28930 (Patent Document 1), even when a plurality of causes of defects are mixed, an optimum inspection condition for identifying the cause of defects can be automatically obtained. Furthermore, in addition to the correlation between the inspection conditions and the defect density, there are described inspection analysis apparatuses and inspection analysis methods for semiconductor applied devices equipped with a new quantitative defect cause identification means that is not easily affected by the skill level of analysts. .

  Further, for example, in Japanese Patent Laid-Open No. 10-214866 (Patent Document 2), defect position data related to a semiconductor wafer is acquired from inspection result data of the semiconductor wafer, and a defect is detected from a defect position distribution which is defect position data. A failure analysis method is disclosed in which a concentrated region is regarded as a cluster, and an observation position is determined from the area occupation ratio of the cluster over the entire surface of the semiconductor wafer and the cluster shape.

  Further, for example, in Japanese Unexamined Patent Publication No. 2000-200144 (Patent Document 3), the divisor f is obtained for all the position coordinate intervals Δx of any two defective elements, and the expected value function T is calculated for each f. When the value of (f) is calculated and the values of the expected value function T (f) are all 1 or less, the distribution of defective elements is an irregular distribution; otherwise, the distribution of regular elements is included. A failure distribution analysis system that determines that is disclosed.

Further, for example, in Japanese Patent Laid-Open No. 11-186354 (Patent Document 4), in an integrated circuit in which circuit element groups are arranged in an orderly manner, defects caused by design and defects that do not exist are indicated for each defective element. A semiconductor integrated circuit inspection and analysis apparatus and method are disclosed in which the cause of failure can be distinguished qualitatively and quantitatively by analyzing the types of divisors of intervals and their frequency.
JP 2003-28930 A Japanese Patent Application Laid-Open No. 10-214866 JP 2000-200144 A JP-A-11-186354

  After an integrated circuit is formed on a main surface of a semiconductor wafer in units of chips, various tests are performed on the integrated circuit formed on each chip to determine whether the integrated circuit meets the standard. A test is performed. In this wafer test process, first, a semiconductor wafer is placed on a measurement stage of an inspection apparatus, and a probe (probe) is brought into contact with an electrode pad of an integrated circuit. Subsequently, a signal waveform is input from the input terminal, the tester reads the signal waveform output from the output terminal, and the quality of the chip is determined from the measurement result. A defective chip is marked on a chip determined to be defective (hereinafter referred to as a defective chip).

  Further, in this wafer test process, in addition to determining whether a chip is good or defective, the probability of a good chip in one semiconductor wafer (a chip determined to be good obtained from one semiconductor wafer (hereinafter referred to as a good chip). ) Divided by the number of active chips is displayed as a decimal point or percentage, which is referred to herein as GW yield) and the ratio of defective chips in a specific test item. Further, it is determined whether or not there is a distribution of defective chips in the semiconductor wafer (AUF: Area Usage of Factor).

  The determination of the presence or absence of AUF is an inspection means introduced in recent years to ensure the quality of semiconductor devices. That is, in a semiconductor wafer having an AUF, a defective potential may be latent in a good chip adjacent to the AUF. Therefore, for a semiconductor wafer determined to have an AUF, a chip adjacent to the AUF is regarded as a defective chip even if it is determined to be good in the wafer test process, and the product is not shipped. Discarded. As a result, it is possible to prevent the outflow of a chip having a potential defect and to ensure the quality of the semiconductor device after being shipped.

  However, regarding the determination of the presence or absence of the AUF, there are various technical problems described below.

  For example, about one or two semiconductor wafers are extracted from all the semiconductor wafers on which the integrated circuits are formed, and the presence or absence of AUF is determined by the operator with respect to the extracted semiconductor wafers. However, since there is no criterion for determining the presence or absence of AUF, the determination of the presence or absence of AUF often depends on the operator's sense, and the determination result may depend on the operator. Further, since the presence / absence of AUF is determined only for the extracted semiconductor wafer, there is a possibility that a chip having a defective potential may flow out. The chip that has flowed out may exhibit abnormal operating characteristics after shipment, leading to a deterioration in the quality of the semiconductor device. In addition, some workers require a great deal of time to determine the presence or absence of AUF. Since the flow of the semiconductor wafer is stopped until the determination result is obtained, the work efficiency in the wafer test process is reduced.

  One object of the invention disclosed in the present application is to provide a technique capable of improving the quality of a semiconductor device.

  Another object of the invention disclosed in the present application is to provide a technique capable of improving work efficiency in a wafer test process of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to the semiconductor device manufacturing method of the present invention, a specific test is performed on all the chips formed on a semiconductor wafer, and the result of the specific test indicates whether each chip is a good chip or a defective chip. The process of performing the determination and the results of the determination are compared with a plurality of determination modes, and the presence or absence of AUF is automatically determined for all the semiconductor wafers for which the specific test has been performed.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Quantitatively defining AUF using a plurality of determination modes, and determining the presence or absence of AUF for all semiconductor wafers that have undergone a specific test, thereby improving the detection rate of chips with potential defective potential be able to. As a result, the outflow of the chip with potential defect potential can be prevented, and the quality of the semiconductor device can be improved. Furthermore, since the presence / absence of the AUF is automatically determined, the time required for determining the presence / absence of the AUF is shorter than that performed by the operator, and the work efficiency in the wafer test process can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related. Also, in this embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified, or in principle limited to a specific number in principle. The number is not limited to the specific number, and may be a specific number or more. Further, in the present embodiment, it is needless to say that the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. Further, in the drawings used in this embodiment mode, hatching may be added to make the drawings easy to see even if they are plan views or process drawings. In this embodiment, the term “semiconductor wafer” is mainly a silicon (Si) single crystal wafer. However, not only that, but also an SOI (Silicon on Insulator) wafer and an integrated circuit are formed thereon. Insulating film substrate or the like. The shape includes not only a circle or a substantially circle but also a square, a rectangle and the like. In addition, when referring to a gas, solid or liquid component, the component specified therein is one of the major components, but unless otherwise specified or otherwise apparent in principle, It does not exclude ingredients.

  A method for determining the presence or absence of AUF according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a process diagram of a wafer test according to the present embodiment, FIG. 2 is an inspection process diagram illustrating an example of an inspection flow in a P inspection process according to the present embodiment, and FIG. FIG. 4 to FIG. 10 are explanatory diagrams of an AUF detection method according to the present embodiment, and FIG. 11 is a process diagram illustrating an example of an AUF determination flow according to the present embodiment. 12 is a process diagram for explaining another example of the flow of AUF determination according to the present embodiment, FIG. 13 is a schematic chip distribution diagram showing an example of a method for selecting a latent defective chip according to the present embodiment, and FIG. It is a chip distribution map of a good chip and a defective chip showing an example of AUF by form.

  First, in the pre-process, an integrated circuit is formed on the main surface of the semiconductor wafer in units of chips (pre-process in FIG. 1). The semiconductor wafer is made of, for example, silicon single crystal, and has a diameter of, for example, about 300 mm and a thickness of, for example, about 700 μm. The pre-process is a manufacturing process for forming elements such as transistors and wirings on the main surface of the semiconductor wafer. The pre-process includes a film forming process for forming various thin films, a lithography process and an etching process for processing the thin film into a certain shape, an impurity adding process for introducing conductive impurities, and the like.

  Next, the semiconductor wafer is flowed to the wafer test process WT (receiving process in FIG. 1). When a semiconductor wafer is received in the wafer test process WT, first, information related to the start history of the semiconductor wafer in the previous process, such as work date and time, manufacturing apparatus, manufacturing conditions, and inspection data in each manufacturing process, is confirmed. The manufacturing history information of the semiconductor wafer is stored in a database via a network or via a storage medium such as a floppy (registered trademark) disk, and the data stored in the database passes via the network or the storage medium. Then, it can be taken out by a terminal or an inspection apparatus installed in the wafer test process WT. Therefore, the manufacturing history information of the semiconductor wafer can be taken out and confirmed by inputting the lot name and wafer number of the semiconductor wafer to a terminal or an inspection apparatus installed in the wafer test process WT.

  Next, in the W inspection process, basic electrical characteristics and the like of all semiconductor wafers received in the wafer test process WT are evaluated (W inspection process in FIG. 1). In this W inspection process, for example, a TEG (Test Element Group, Test Experimental Group) formed on a semiconductor wafer scribe is used. Of the TEGs formed in one semiconductor wafer, five or nine TEGs are designated, and electrical characteristics and the like are measured at these selected TEGs. The TEG is a group of test elements and is used, for example, to collect basic data relating to basic electrical characteristics and circuit operations at the element level. Further, TEG data is recorded in an inspection apparatus or a database.

  The semiconductor wafer that does not satisfy the standard in the W inspection process is determined as “Fail” and discarded (one scrap process in FIG. 1). The semiconductor wafer that satisfies the standard in the W inspection process is determined to be “Pass” and proceeds to the next P inspection 1 process (P inspection 1 process in FIG. 1). In this P test 1 process, a specific test is performed on all the chips for all semiconductor wafers that are accepted in the wafer test process WT and determined as “Pass” in the W test process.

  First, a semiconductor wafer is placed on a measurement stage of an inspection apparatus, and a probe is brought into contact with an electrode pad of an integrated circuit formed on a chip. Subsequently, when a signal waveform is input from the input terminal, the signal waveform is output from the output terminal, and various data of the chip can be acquired by reading this from the tester. Here, a probe card in which probes are arranged in accordance with all electrode pads of the integrated circuit is used, and signal lines corresponding to the probes are projected from the probe card and connected to a tester. Furthermore, chip data can be recorded in an inspection apparatus or database, and can be displayed on a terminal or an inspection apparatus as a chip distribution map on a semiconductor wafer.

  Specific test items vary by product. For example, in a microcomputer equipped with flash memory (non-volatile memory that can erase and rewrite stored information electrically), as shown in FIG. 2, for example, open test, DC test, FC (function) test and standby current (hereinafter referred to as Isb) The test of the memory unit such as a test is sequentially performed in the P detection 1 step. The open test is a test for confirming that the probe is securely in contact with the electrode pad of the integrated circuit, and is usually performed at the beginning of the test. The DC test is a test of the operating characteristics of the integrated circuit under a direct current condition, and a threshold voltage, a leak current, a bias current, etc. under a standard use condition are measured in accordance with the function of the product. The FC test is a test to check whether the integrated circuit operates according to a predetermined function. The signal waveform that appears at the output terminal when a constant signal waveform is input to the input terminal of the integrated circuit is compared with the normal waveform. Compared. The Isb test is a test for examining the leakage current of the memory cell in the standby state.

  Next, a chip that satisfies a specified value in a specific test is determined as a good chip, and a chip that does not satisfy the specified value is determined as a defective chip. For example, in the Isb test, if the Isb is defined as a good chip if it is less than 1 μA and a defective chip if 1 μA or more is defined as a defective chip, a chip that has passed an Isb of 10 μA or more is determined as a defective chip.

  The determination result is recorded in an inspection apparatus or a database, and can be displayed on a terminal or an inspection apparatus as a chip distribution map on a semiconductor wafer. Further, a defective marking is applied to a chip determined to be defective.

  FIG. 3 is a chip distribution diagram on a semiconductor wafer showing an example of an Isb test result in the P test 1 process of the microcomputer equipped with a flash memory. In FIG. 3, a square in the semiconductor wafer SW is defined as one chip, “/” described on the chip is a good chip determined to be good by the Isb test, and “J” is a defective chip determined to be bad by the Isb test. , “C”, “O”, and “H” are defective chips determined to be defective in other tests. The result of each specific test can be displayed as such a chip distribution map on the semiconductor wafer.

  Next, the presence or absence of AUF is determined (step AUF1 in FIG. 1). In this AUF1 process, all semiconductor wafers accepted in the P test 1 process are targeted, and it is automatically determined whether or not there is an AUF in the results of all the specific tests obtained in the P test 1 process. . Since it is automatically performed using the inspection apparatus, the presence or absence of AUF can be determined in a shorter time than the case where the operator makes a determination, and the time during which the flow of the semiconductor wafer stops can be shortened. Thereby, the fall of working efficiency can be suppressed.

  For the determination of the presence / absence of the AUF, a plurality of determination criteria, for example, seven determination modes of vertical / horizontal division determination, concentric circle division determination, outer periphery determination, radial division determination, lump detection determination, straight line detection determination, and straight line total determination are used.

  Next, an AUF detection method using these determination modes will be described.

1. Vertical / Horizontal Division Determination FIG. 4A is a schematic diagram of a semiconductor wafer for explaining vertical / horizontal division of the semiconductor wafer, and FIG. 4B is a process diagram of vertical / horizontal division determination. In the vertical / horizontal division determination, the semiconductor wafer is divided into lattice areas to determine the yield bias.

  First, the vertical chip number Y and the horizontal chip number X on the semiconductor wafer SW are obtained. The number of chips X and Y is divided by the set division number n, and the number of chips in each divided area is divided almost evenly. Subsequently, after obtaining the yield of each area, the difference between the maximum yield value and the minimum yield value between the areas is obtained. The semiconductor wafer SW in which the difference between the maximum yield value between the areas and the minimum yield value is greater than or equal to the reference yield is determined to be AUF, and the semiconductor wafer SW that is less than the reference yield is determined to be no AUF.

2. FIG. 5A is a schematic diagram of a semiconductor wafer for explaining concentric circle division of a semiconductor wafer, and FIG. 5B is a process diagram of concentric circle division determination. In the concentric circle division determination, the semiconductor wafer is divided into concentric areas to determine the yield bias.

  First, the leftmost top chip in the chip map is set as the origin. The position coordinates of the center chip are obtained, and further the center position coordinates of each chip are obtained. Subsequently, after obtaining the radius of the outermost circle, the radius of the circle is divided by the division number n (3 in FIG. 5A) to obtain the radius of the innermost circle. Subsequently, the radius of each circular area is obtained, and each chip is assigned to each circular area. Subsequently, after obtaining the yield of each circle area, the difference between the maximum yield value and the minimum yield value between the circle areas is obtained. A semiconductor wafer SW in which the difference between the maximum yield value and the minimum yield value between the circular areas is greater than or equal to the reference yield is determined to be AUF, and a semiconductor wafer SW that is less than the reference yield is determined to be no AUF.

3. FIG. 6A is a schematic diagram of a semiconductor wafer for explaining the outer periphery of the semiconductor wafer, and FIG. In the outer periphery determination, the semiconductor wafer is divided into an inner periphery area and an outer periphery area, and a yield bias is determined.

  First, after obtaining the yield of the inner peripheral area and the yield of the outer peripheral area, the difference between the yield of the inner peripheral area and the yield of the outer peripheral area is obtained. The semiconductor wafer SW in which the difference between the yield in the inner peripheral area and the yield in the outer peripheral area is equal to or greater than the reference yield is determined to be AUF, and the semiconductor wafer SW that is less than the reference yield is determined to be absent.

4). Radial division determination FIG. 7A is a schematic diagram of a semiconductor wafer for explaining the radial division of the semiconductor wafer, and FIG. 7B is a process diagram of the radial division determination. In the radial division determination, a yield bias depending on an area obtained by dividing the radial area by 2n is determined.

  First, a table for radially dividing is prepared. The center of the chip map and the center of the table are matched and overlapped. Subsequently, after obtaining the yield of each area, the difference between the maximum yield value and the minimum yield value between the areas is obtained. The semiconductor wafer SW in which the difference between the maximum yield value between the areas and the minimum yield value is greater than or equal to the reference yield is determined to be AUF, and the semiconductor wafer SW that is less than the reference yield is determined to be no AUF.

5. Block Detection Determination FIG. 8A is a schematic diagram of a semiconductor wafer for explaining semiconductor wafer block detection, and FIG. 8B is a block diagram of block detection determination. In the block detection determination, it is determined that there is an abnormality when there is a block of defective categories with the number of chips = M × N in the chip map.

  First, the reference chip number for the defective chip is set. FIG. 8A illustrates a case where the reference chip number is set to 4 (= 2 × 2). Subsequently, the defect category of the chip within the set number of reference chips is investigated, and the semiconductor wafer SW in which the defect category is the same as the designated defect category is determined as having AUF, and a different semiconductor wafer SW is not having AUF. Is determined.

6). Straight Line Detection Judgment FIG. 9A is a schematic diagram of a semiconductor wafer for explaining the straight line detection of the semiconductor wafer, and FIG. 9B is a process chart of the straight line detection judgment. In the straight line detection determination, a case where there are N defect categories that are continuous in a straight line is determined to be abnormal.

  First, the number of linear chips for a defective chip is set. FIG. 9A illustrates a case where the number of linear chips is set to four. Subsequently, the defect category of the chip within the set range of the number of linear chips is investigated, and the semiconductor wafer SW in which the defect category is the same as the designated defect category is determined as having AUF, and a different semiconductor wafer SW is identified as AUF. Judge that there is no.

7). Straight Line Aggregation Determination FIG. 10A is a schematic diagram of a semiconductor wafer for explaining the linear aggregation of the semiconductor wafer, and FIG. 10B is a process chart of the straight line aggregation determination. In the straight line totaling determination, the yield in the row direction and the yield in the column direction of the semiconductor wafer are obtained, and the yield bias depending on the row direction or the column direction is determined.

  First, the number of chips X in the row direction and the number of chips Y in the column direction are obtained, and then the GW yield Z in the entire semiconductor wafer SW is obtained. Subsequently, each row is processed. Here, in order to match the parameters, the number of spaces in which chips in each row are not formed is obtained, and the yield of each row is calculated using the following equation (1).

(Number of spaces × Z / 100 + number of good chips in a row) / X Formula (1)
Subsequently, each column is processed. Here, in order to match the parameters, the number of spaces in which chips in each column are not formed is obtained, and the yield of each column is calculated using the following equation (2).

(Number of spaces × Z / 100 + number of good chips in a row) / Y Formula (2)
Subsequently, the semiconductor wafer SW in which the difference between the GW yield Z of the entire semiconductor wafer SW and the minimum yield value of each row or the minimum yield value of each column is equal to or greater than the reference yield is determined to be AUF, and less than the reference yield. The determined semiconductor wafer SW is determined to have no AUF.

  The determination result of the presence or absence of AUF obtained by the above determination is recorded in an inspection apparatus or database, and all determination results for all specific test items are displayed on a terminal or inspection apparatus for each semiconductor wafer as a list, for example. can do.

  Further, in this AUF1 process, in addition to the determination of the presence or absence of AUF, the semiconductor wafer is advanced to the next process based on the result of the specific test obtained in the P test 1 process or the determination result of the good / bad of the chip. Whether or not it is automatically determined. That is, there are many chips that do not satisfy the value specified in a specific test and the number of good chips is extremely small, and a semiconductor wafer or the like is judged as “Fail” and discarded (step 2 of scrap in FIG. 1). For example, as a criterion, if the defective chip of Isb occupies 20% or more of the effective chip on the semiconductor wafer, it is defined as discarding. If the defective chip of Isb occupies 50% of the effective chip on the semiconductor wafer In this case, the semiconductor wafer is judged as “Fail” and discarded regardless of the presence or absence of AUF.

  Next, the flow of the AUF1 process will be summarized using the process diagram shown in FIG.

  First, in each of the determination modes 1 to 7, the presence / absence of AUF is automatically determined by computer processing or the like. The determination result obtained by each determination is recorded in an inspection device or a database. However, it is not necessary to perform the determination of the presence or absence of AUF for all these seven determination modes, and a determination mode that is not performed depending on the semiconductor device may be provided.

  Subsequently, after determining whether or not there is an AUF, using the result of a specific test for the semiconductor wafer, it is automatically determined whether or not to proceed to the next process for each semiconductor wafer, and the determination result is recorded. Similarly, a determination result of whether or not to proceed to the next process is automatically performed for each semiconductor wafer by using the determination result of good / bad chips, for example, GW yield, and the determination result is recorded.

  Subsequently, whether the flow is made for each lot using the result of a specific test for a lot (a unit of a specific number of semiconductor wafers managed along the flow of the manufacturing process, and generally made in the same manufacturing process). The determination of whether or not is performed automatically and the determination result is recorded. Similarly, it is automatically determined whether or not to proceed to the next process for each lot using the determination result of chip quality, for example, GW yield, and the determination result is recorded. Finally, based on all the determination results, whether or not the semiconductor wafer or lot is advanced to the next process is confirmed in the final process. As described above, in the AUF1 process, a series of processes from determination of presence / absence of AUF, determination of whether to advance the semiconductor wafer or lot to the next process, and final confirmation of the determination result are automatically performed.

  Next, a semiconductor wafer that has been determined as “no AUF” and has satisfied the standard by a specific test or a determination of good / bad of a chip proceeds to the next P inspection step (P inspection (n) step in FIG. 1). . Here, (n) is an integer equal to or greater than 2, and is the number of times the test is repeated. In this P test (n) process, a specific test of an item different from the specific test items of the P test 1 process is performed, and all semiconductor wafers input to the P test (n) process are targeted, Whether the chip is good or bad is determined. In the flash memory-equipped microcomputer, for example, a test of the logic part is performed in the P detection 2 process. The determination result is recorded in an inspection apparatus or a database, and can be displayed on a terminal or an inspection apparatus as a chip distribution map on a semiconductor wafer. Further, a defective marking is applied to a chip determined to be defective.

  When the P inspection (n) process is completed, the semiconductor is based on the determination of the presence or absence of AUF, the result of the specific test obtained in the P inspection (n) process, or the determination result of good / bad of the chip, as in the above AUF1 process. Whether or not to advance the wafer to the next process is automatically performed in the AUF (n) process (AUF (n) process in FIG. 1). Here too, there are many chips that do not satisfy the values specified in the specific test, and semiconductor wafers with a very small number of good chips are discarded (scrap three steps in FIG. 1).

  The P detection (n) process and the AUF (n) process are repeated n times, but the number of times varies depending on the semiconductor device. In the case of a semiconductor device that repeats the P detection process and the AUF process n times or more, for example, many of the chips that are determined to be “Fail” in the k (1 ≦ k <n) AUF (k) process performed earlier. Is determined to be “Fail” in the next (k + 1) -th AUF (k + 1) process, and therefore the same AUF is determined in all the AUF (n) processes n times. In order to avoid this, for example, the difference between the GW yield of the previously performed P test k process and the GW yield of the next P test (k + 1) process is taken, and the difference in the GW yield is determined from the set reference value. If smaller, a function that does not determine whether or not there is an AUF in the AUF (k + 1) step may be added.

  Further, when determining whether or not to advance the semiconductor wafer to the next process based on the result of the specific test or the result of determining whether the chip is good or defective, for example, the P test ( k) When the GW yield of the P test (k + 1) process performed next is lower than the GW yield of the process, for example, the difference between the GW yield of the P test (k) process and the GW yield of the P test (k + 1) process is calculated. In addition, if the difference in GW yield is smaller than the set reference value, a function that does not determine whether the chip is good or bad in the AUF (k + 1) process may be added.

  Similarly, when determining whether or not to advance the semiconductor wafer to the next process based on the result of a specific test or the result of determining whether a chip is good or defective, for example, a P test ( k) When the GW yield of the P test (k + 1) process performed next is lower than the GW yield of the process, for example, the difference between the GW yield of the P test (k) process and the GW yield of the P test (k + 1) process is calculated. In addition, if the difference in GW yield is smaller than the set reference value, a function that does not determine whether the chip is good or bad in the AUF (k + 1) process may be added.

  FIG. 12 illustrates an example of the flow of the AUF (n) process when a function for instructing whether or not to perform the determination of the presence / absence of the AUF and whether the chip is good / bad in the AUF (k + 1) process is added. Process drawing is shown.

  A function for instructing whether or not to perform the determination of the presence or absence of AUF is added after the determination of the presence or absence of AUF is performed in 1 to 7 AUF determination modes. Further, a function for instructing whether or not to determine whether a chip is good or defective for each semiconductor wafer is added after the determination of whether a chip is good or defective in the semiconductor wafer. Further, a function for instructing whether or not to determine whether a chip is good or defective for each lot is added after determining whether a chip is good or bad in a lot. By instructing whether or not to perform the determination of the presence / absence of an AUF and the determination of whether the chip is good or bad, the final confirmation of a semiconductor wafer or a lot with a clearly low yield can be omitted, so the time required for the final confirmation Can be shortened.

  Next, in the AUF (n) process, it is determined that “no AUF” and the semiconductor wafer that satisfies the standard by the specific test or the determination of good / bad of the chip is a process of creating the next shipment data (FIG. 1). Proceed to the shipping data creation process. In this shipment data creation step, product specifications and characteristic data attached to the semiconductor device at the time of shipment are automatically created.

  On the other hand, the semiconductor wafer determined as “AUF present” in the AUF1 step and the AUF (n) step proceeds to the automatic processing step (automatic processing step in FIG. 1). In this automatic processing process, peripheral chips of the AUF or adjacent chips, for example, one or two good chips in the peripheral area of the AUF are defective chips (potential) The defective chip processing is automatically executed by computer processing or the like. The number of good chips around the AUF to be defective is determined in consideration of the number of good chip losses due to the defect and the quality of the good chips.

  FIG. 13A is a schematic chip distribution diagram for explaining an example of a method for selecting a latent defective chip, and FIG. 13B is a schematic diagram showing Isb values of chips arranged on the line AA ′ in FIG. FIG. For example, in the P test 1 step, a chip having an Isb larger than a specification (specified value) is determined as a defective chip (Fail) NC, and a chip having a small Isb is determined as a good chip (Pass) PC. However, even if the chip is determined to be a good chip, a good chip close to the specification has a great potential to become a defective chip. Therefore, in a semiconductor wafer having such an AUF, it is considered important to detect a good chip PC around the AUF as a latent defective chip UPC.

  FIG. 14 is a chip distribution diagram on the semiconductor wafer in which the good chips in one row around the AUF are defective in the test result of the Isb test shown in FIG. “Z” is a good chip with a defect. From the results of the Isb test, 392 good chips were obtained with respect to the number of 603 effective chips, but the number of good chips became 279 due to the failure of the good chips. Decrease. However, since all of the semiconductor wafers with AUF can be excluded from chips that have potential defects, the outflow of chips with potential defects can be stopped. It is possible to prevent the quality of the semiconductor device from being deteriorated after product shipment.

  The determination result is stored in an inspection apparatus or a database, and can be displayed on a terminal or an inspection apparatus as a chip distribution map on a semiconductor wafer. Further, a defective marking is applied to a chip determined to be a latent defect. In addition, although the defect marking was put on the chip determined to be defective in the P inspection 1 step or the P inspection (n) step, the defective chip and the latent defective chip may be collectively marked in this step.

  In the automatic processing step for deteriorating good chips, a standard is set as to whether or not to flow the “AUF present” semiconductor wafer. As one of the setting criteria, for example, a good chip yield considering latent defective chips can be cited. The good chip yield mentioned here is the number of good chips obtained from one semiconductor wafer (the number of effective chips minus the total number of defective chips and latent defective chips) divided by the number of effective chips. The value is displayed as a decimal point or a percentage, and is different from the GW yield that does not consider a potential defective chip.

  Next, the semiconductor wafer that satisfies the target setting criteria in the automatic processing process proceeds to a process of generating shipping data (shipping data generating process in FIG. 1).

  On the other hand, the semiconductor wafer that does not satisfy the target setting criteria in the automatic processing process is analyzed by the operator (analysis process in FIG. 1). Here, the cause of the defect is examined, and the analysis result is sent to each manufacturing process of the semiconductor wafer via the network, for example.

  Subsequently, the operator determines whether or not to ship the semiconductor wafer (flow determination step in FIG. 1). Even if it is a semiconductor wafer that does not meet the setting criteria in the automatic processing step, for example, when it is desired to acquire even a few good chips, it is possible to proceed to a shipping data creation step. On the other hand, a semiconductor wafer or the like for which good chips cannot be obtained at all due to defective good chips is discarded (scrap four steps in FIG. 1).

  Next, the semiconductor wafer on which the shipping data is created is packed (packing process in FIG. 1) and shipped to the customer (shipping process in FIG. 1). Thereafter, the semiconductor wafer is cut in a post-process (the post-process in FIG. 1), and only good chips that are not marked are assembled into a product. For example, first, a chip is placed on a lead frame, and an electrode on the chip and an electrode on the lead frame are connected by a gold wire. Further, the chip is encapsulated with mold resin, the product name and the like are printed, the lead is plated, and each chip is cut from the lead frame. After processing the leads into various shapes, the finished chips are sorted according to product specifications, checked for reliability, and the chips that have passed the final inspection are completed as products.

  As described above, according to the present embodiment, since the AUF is quantitatively defined using a plurality of determination modes, the presence / absence of AUF can be determined for all semiconductor wafers. It is possible to improve the chip detection rate. As a result, it is possible to prevent the outflow of a chip having a defective potential, and to avoid deterioration of the quality of the semiconductor device after product shipment. Further, by automatically determining the presence or absence of AUF, the time required for determining the presence or absence of AUF is shorter than the time required for processing by the operator, so that the work efficiency in the wafer test process can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above embodiment, seven AUF modes are exemplified as a method for detecting AUF, but the present invention is not limited to this.

  The method for manufacturing a semiconductor device of the present invention can be applied to a semiconductor device inspection process.

It is process drawing of the wafer test by embodiment of this invention. It is a test process figure which shows an example of the flow of a test | inspection in P test process by embodiment of this invention. It is a chip distribution diagram which shows an example of the P test result in the microcomputer with built-in flash memory according to the embodiment of the present invention. (A) is the schematic of the semiconductor wafer explaining the vertical / horizontal division | segmentation of a semiconductor wafer, (b) is process drawing of vertical / horizontal division | segmentation determination. (A) is the schematic of the semiconductor wafer explaining the concentric division of a semiconductor wafer, (b) is a process figure of concentric division determination. (A) is the schematic of the semiconductor wafer explaining the outer periphery of a semiconductor wafer, (b) is a flowchart of an outer periphery determination. (A) is the schematic of the semiconductor wafer explaining the radial division of a semiconductor wafer, (b) is process drawing of radial division determination. (A) is a schematic diagram of a semiconductor wafer for explaining detection of a lump of a semiconductor wafer, and (b) is a process diagram of lump detection determination. (A) is a schematic diagram of a semiconductor wafer for explaining the straight line detection of the semiconductor wafer, and (b) is a process chart of straight line detection determination. (A) is the schematic of the semiconductor wafer explaining the straight line totalization of a semiconductor wafer, (b) is a process figure of a straight line total determination. It is process drawing explaining an example of the flow of AUF determination by embodiment of this invention. It is process drawing explaining the other example of the flow of AUF determination by embodiment of this invention. (A) is a schematic chip distribution diagram showing an example of a method for selecting a latent defective chip according to an embodiment of the present invention, and (b) is a value of Isb of a chip arranged on the AA ′ line in FIG. FIG. It is a chip distribution map of a good chip and a defective chip showing an example of an AUF according to an embodiment of the present invention.

Explanation of symbols

SW semiconductor wafer WT wafer test process NC good chip PC bad chip UPC latent bad chip

Claims (9)

A semiconductor device manufacturing method including the following steps:
(A) performing a specific test on all the chips formed on the semiconductor wafer;
(B) determining whether each chip is a good chip or a defective chip from the result of the specific test;
(C) A step of determining whether or not there is a distribution of defective chips in the semiconductor wafer from the result of the determination in the step (b).
Here, the step (c) targets all semiconductor wafers that have undergone the specific test.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (c) is automatically performed by a computer process based on a database including a result of the determination in the step (b). The method for manufacturing a semiconductor device according to claim 1 further includes the following steps:
(D) A step of setting a good chip around the defective chip distribution as a latent defective chip for the semiconductor wafer determined to have a distribution of defective chips in the semiconductor wafer in the step (c).   4. The method of manufacturing a semiconductor device according to claim 3, wherein the step (d) is automatically performed by computer processing based on a database including a result of determination in the step (c).   2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (c) is performed in light of a plurality of determination modes. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the plurality of determination modes include some or all of the following:
(I) Yield bias divided into grid-like areas,
(Ii) yield bias divided into concentric areas,
(Iii) Yield bias divided into inner and outer peripheral areas,
(Iv) Yield bias depending on the area divided by 2n into a radial area,
(V) a defect category that exists in a lump with a specific number of chips,
(Vi) N defect categories that exist continuously in a straight line,
(Vii) Yield bias depending on the row direction or column direction of the semiconductor wafer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (c) further includes the following steps:
(C1) A step of calculating a ratio of the number of good chips to the number of effective chips and discarding a semiconductor wafer in which the ratio does not satisfy a prescribed value. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step (c) further includes the following steps:
(C2) A step of discarding a semiconductor wafer whose result of the specific test does not satisfy a specified value. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the step (d) further includes the following steps:
(D1) A step of calculating a ratio of the number of good chips to the number of effective chips minus latent defective chips, and discarding the semiconductor wafer in which the ratio does not satisfy a specified value.