JP2007335785A - Apparatus, method and program for testing semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus, a method and a program for testing a semiconductor wafer in which a defective article is not handled as a good article, and an yield can be improved. <P>SOLUTION: Based on the yield for each position of a chip in a tested semiconductor wafer, information indicative of a region where a probability to be defective is high is created as a latent defective region map. An AND region is calculated overlapping the position of a chip that becomes defective in a measurement test for a semiconductor wafer to be tested, and the latent defective region map. Based on the AND region, a file for forcible exclusion chip is created. A chip included within a region totaling regions indicated by the defective chip map and the file for forcible exclusion chip is defined as an exclusion chip. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer inspection apparatus, an inspection method, and an inspection program for inspecting a semiconductor wafer and sorting in units of chips.

  A semiconductor wafer having a plurality of chips is known. A plurality of chips formed on one semiconductor wafer are individually commercialized. Therefore, a test for a good product or a defective product is performed not for each wafer but for each chip. This test is performed, for example, by measuring the electrical characteristics of each chip using a tester. Chips determined to be defective as a result of the test are subjected to processing such as marking, and are cut into chips, and then removed as defective products. As described above, as a method of testing a chip to determine whether it is good or bad, for example, Patent Document 1 compares and tabulates the measured data of each wafer and the standard so that the standard at the same coordinate between the wafers is shifted. Is output in one map format.

  By the way, depending on the accuracy of the test, some chips determined to be non-defective products may have a cause of failure.

  The good / defective result of each chip largely depends on the position on the semiconductor wafer. In order to prevent a defective product from being handled as a non-defective product, an inspection technique using this position dependency is known. For example, Patent Document 2 describes that when a continuous defect distribution occurs, a defect mark is automatically formed around a defective chip. That is, when a defective chip is solidified as a result of actual measurement of a semiconductor wafer, even if the test result is a non-defective product at the periphery, it is forcibly excluded.

However, as described in Patent Document 2, when chips around defective chips are automatically handled as defective, the ratio of chips that are not defective but are excluded increases and the yield decreases. There was a problem that it would. Therefore, it has been desired to provide an inspection technique that does not treat a defective product as a non-defective product and can increase the yield.
Japanese Patent Laid-Open No. 01-304739 Japanese Patent Laid-Open No. 2001-210682

  An object of the present invention is to provide a semiconductor wafer inspection apparatus, inspection method, and inspection program in which a defective product is not handled as a non-defective product and the yield can be increased.

  Means for solving the problem is expressed as follows. Technical matters appearing in the expression are appended with numbers, symbols, etc. in parentheses. The numbers, symbols, and the like are technical matters constituting at least one embodiment or a plurality of embodiments of the present invention or a plurality of embodiments, in particular, the embodiments or examples. This corresponds to the reference numbers, reference symbols, and the like attached to the technical matters expressed in the drawings corresponding to. Such reference numbers and reference symbols clarify the correspondence and bridging between the technical matters described in the claims and the technical matters of the embodiments or examples. Such correspondence or bridging does not mean that the technical matters described in the claims are interpreted as being limited to the technical matters of the embodiments or examples.

  A semiconductor wafer inspection apparatus (10) according to the present invention includes a latent defective region map creating unit (1) that creates a latent defective region map, and a forced exclusion chip file creating unit (2) that creates a forced exclusion chip file. And an exclusion chip file creation section (3) for creating an exclusion chip file. The latent defective area map creation unit (1) creates information indicating a region having a high probability of being defective as the latent defective area map based on the yield of each chip position of the semiconductor wafer that has already been tested. The compulsory exclusion chip file creation unit (2), based on the defective chip map indicating the position of the chip that has failed in the actual test of the semiconductor wafer (4) to be inspected, and the latent defective area map, An AND area that is an area where the area indicated in the latent defective area map and the area indicated in the defective chip map overlap is calculated. A forced exclusion chip area is obtained based on the AND area, and the forced exclusion chip file is created as information indicating the forced exclusion chip area. The exclusion chip file creation unit (3) combines the forcibly excluded chip area and the area indicated by the defective chip map data based on the forcibly excluded chip file and the defective chip map. Is created as a file for the excluded chip. The excluded chip file is output as information representing the area of the chip to be excluded on the semiconductor wafer (4). Here, the forcibly excluded chip file creation unit (2), when creating the forcibly excluded chip file, obtains an area that is positionally continuous with the AND area among the areas indicated in the defective chip map, It is preferable to create the forced exclusion chip file as information indicating the area around the obtained area and the AND area.

  According to the above-described configuration, in addition to the chip whose result of actual measurement of each chip of the semiconductor wafer is defective, the chip in the area indicated in the forcibly excluded chip file is also excluded. Therefore, it is possible to surely eliminate chips that may have defects even though the actual measurement results are good.

  On the other hand, since the forcibly excluded chip file is created based on the overlapping area (AND area) of the latent defective area map and the defective chip map, the chip to be removed is determined for each semiconductor wafer to be inspected. . As a result, the number of chips to be removed is reduced despite the absence of defects, and the yield can be improved.

  According to the present invention, there is provided a semiconductor wafer inspection apparatus, inspection method, and inspection program that can handle a defective product as a non-defective product and increase the yield.

  A configuration of a semiconductor wafer inspection apparatus according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a functional block diagram showing the configuration of a semiconductor wafer inspection apparatus 10. The semiconductor wafer inspection apparatus 10 includes a tester 5, a processing apparatus 6, a system PC 7, and a marking probe 8. These are connected to each other via the processing device 6 so as to be able to exchange data. Details of each component will be described below.

  The tester 5 measures the quality of the semiconductor wafer 4 to be inspected on a chip basis. When the tester 5 performs measurement for all the chips on the semiconductor wafer 4, it generates a defective chip map as data. The defective chip map is information indicating the position of the defective chip. In the following description, a defective chip area indicated in the defective chip map is referred to as a defective area. The tester 5 is connected to the processing device 6 and can send the defective chip map to the processing device 6.

  The processing device 6 is a computer having a CPU, a ROM, a RAM, and the like. The processing device 6 realizes its function by the installed program. The processing device 6 stores a defective chip map acquired from the tester 5 as data and realizes a function of transmitting it to the system PC 7. The processing device 6 is installed with an exclusion chip file creation unit 3 as a semiconductor wafer inspection program. The function of the exclusion chip file creation unit 3 will be described later.

  Similarly to the processing device 6, the system PC 7 is a computer having a hardware configuration such as a CPU, a ROM, a RAM, and a hard disk. The system PC 7 is installed with a forcibly excluded chip file creation unit 2 and a latent defective area map creation unit 1 as a semiconductor wafer inspection program. When the system PC 7 acquires the defective chip map from the processing device 6, the system PC 7 generates a forced exclusion chip file and implements a function of transmitting the forced exclusion chip file to the processing device 6.

  The system PC 7 also has a storage device. In the storage device, information (inspected wafer data 9) indicating the inspection result of the already inspected semiconductor wafer for each position of the chip is stored.

  The marking probe 8 is for marking a chip to be excluded among the chips on the semiconductor wafer 4. The marking is performed based on the excluded chip file acquired from the processing device 6. The marked chip is regarded as a chip to be excluded, and is excluded after being divided into chips.

  Next, the function of the semiconductor device inspection program installed in the processing device 6 or the system PC 7 will be described. As described above, as the semiconductor device inspection program, the processing device 6 includes the exclusion chip file creation unit 3 and the system PC 7 includes the forced exclusion chip file creation unit 2 and the latent defective area map creation unit. Installed.

  The latent defective area map creation unit 1 refers to the inspected data 9 and generates a latent defective area map. The latent defective area map is information indicating a position with a high probability of being defective on the semiconductor wafer. FIG. 4 is a diagram conceptually showing the latent defective area map. In the example shown in FIG. 4, the shaded area at the upper left of the semiconductor wafer indicates that there is a high probability of potential failure (hereinafter, referred to as a latent failure area).

  The generation of the latent defective area map is obtained, for example, by determining the yield of defective chips for each position on the semiconductor wafer and determining an area having a higher yield than a predetermined ratio as a potential defective area. be able to. In addition, a known statistical method such as using the standard deviation σ may be used.

  When the defective chip map is sent as data from the processing device 6, the forced exclusion chip file creation unit 2 uses the latent defective region map created by the latent defective region map creation unit 1 to forcibly exclude chips. Create a file. In creating the forced exclusion chip file, the forced exclusion chip file creation unit 2 first obtains an AND area. The AND area is an area where the defective area and the latent defective area overlap.

  With reference to FIG. 3 and FIG. 5, how to obtain the AND region will be described. FIG. 3 shows a conceptual diagram of a region (defective region) shown in the defective chip map. 3A to 3C, the chip on which the mark “F” is drawn is a chip that has been defective in the inspection by the tester 5. FIGS. 5A to 5C are views showing a state in which a latent defective region is superimposed on the defective region shown in FIGS. 3A to 3C. The compulsory exclusion chip file creation unit 2 obtains an AND area by superimposing maps as shown in FIG. In the example shown in FIG. 5A, the defective area and the latent defective area completely match. Therefore, the AND area is the same as the defective chip map and the latent defective area. On the other hand, in the example shown in FIG. 5B, the defective area completely includes the latent defective area, and the defective area is wider. In this case, the AND area matches the latent defective area. In the example shown in FIG. 5C, the defective area and the latent defective area do not overlap. In this case, the AND area does not exist.

  The forcibly excluded chip file creation unit 2 further creates a forcibly excluded chip file based on the obtained AND area. Specifically, when an AND area exists, an area including the AND area is obtained from consecutive areas in the defective area. That is, an area that at least partially overlaps the latent defective area is obtained. Hereinafter, this area is referred to as a continuous defective area. In the example shown in FIGS. 5A and 5B, the defective area is one continuous area. Since the defective area includes an AND area, the defective area itself is a continuous defective area. Even if there is a continuous area in the AND area in the latent defective area, this part is not particularly processed. On the other hand, in the example shown in FIG. 5C, since the AND area itself does not exist, the defective area is not a continuous defective area.

  Subsequently, the forcibly excluded chip file creation unit 2 obtains an area adjacent to the continuous defective area as the forcibly excluded chip area. FIG. 6 is a diagram illustrating a forced exclusion chip area. FIGS. 6A, 6B, and 6C correspond to examples when the AND region is FIGS. 5A, 5B, and 5C, respectively. In the example shown in FIGS. 6A and 6B, the area adjacent to the continuous defective area is the forced exclusion chip area. Here, the term “adjacent” includes not only the case where the sides are adjacent but also the case where the corners are adjacent. On the other hand, in the case as shown in FIG. 6C, since there is no continuous defective area, there is no forced exclusion chip area.

  The forcibly excluded chip file creation unit 2 generates information indicating the forcibly excluded chip area thus obtained as a forcibly excluded chip file.

  Next, the function of the excluded chip file creation unit 3 will be described. The exclusion chip file creation unit 3 determines whether the forced exclusion chip area and the defect are based on the forced exclusion chip file generated by the forced exclusion chip file creation unit 2 and the defective chip map stored in the processing device 6. A region combined with the region (hereinafter referred to as an excluded chip region) is obtained. Here, as shown in FIG. 6C, when the forcibly excluded chip area does not exist, only the defective area becomes the excluded chip area. The exclusion chip file creation unit 3 generates information indicating the exclusion chip area thus obtained as an exclusion chip file. Then, the generated exclusion chip file is output to the marking probe 8.

  In this embodiment, the case where the latent defective area map creation unit 1 and the forced exclusion chip file creation unit 2 are installed in the system PC 7 and the exclusion chip file creation unit 3 is installed in the processing device 6 has been described. However, the inspection program does not necessarily have to be installed separately on the two devices. That is, there is no problem even if the latent defective area map creation unit 1, the forced exclusion chip file creation unit 2, the exclusion chip file creation unit 3, and the inspected wafer data 9 are stored in the same computer.

  Moreover, although the case where the generation of the defective chip map is performed by the tester 5 has been described, the generation of the defective chip map may be performed on the processing device 6 side.

  Subsequently, a method for inspecting a semiconductor device according to the present embodiment will be described. FIG. 2 is a flowchart of a semiconductor device inspection method.

  First, the quality of the semiconductor wafer 4 is measured by the tester 5 (step S20). The measurement is performed for all chips on the semiconductor wafer 4. Subsequently, the tester 5 creates a defective chip map (step S30). The tester 5 transmits the generated defective chip map to the processing device 6 (step S31). Further, the processing device 6 stores the acquired defective chip map in the processing device 6 and transfers it to the system PC 7 (step S32).

  In the system PC 7, the latent defective area map creation unit 1 refers to the inspected wafer data 9 and generates a latent defective area map (step S10). Then, the forcibly excluded chip file creation unit 2 obtains an AND area based on the defective chip map and the latent defective area map (step S40). As described above, the AND area is an area where the defective area and the latent defective area overlap. The generation of the latent defective area map (S10) may be executed at any stage before the generation of the AND area (S40).

  The forcibly excluded chip file creation unit 2 that has generated the AND region further generates a forcibly excluded file (step S50). Here, the forced exclusion chip file 2 is a continuous area in the defective area, and an area including the AND area is obtained as a continuous defective area (step S501). Then, an area adjacent to the continuous defective area is obtained as a forced exclusion chip area and converted into data as a forced exclusion chip file (step S502). The forced exclusion chip file creation unit 2 transmits the generated forced exclusion chip file to the processing device 6 (step S53).

  In the processing device 6 that has acquired the forced exclusion chip file, the exclusion chip file creation unit 3 creates the exclusion chip file (step S60). Here, as described above, the exclusion chip file creation unit 3 obtains an area including the defective area and the forced exclusion chip area as an exclusion chip area, and converts it into a data for the exclusion chip file. The exclusion chip file creation unit 3 transfers the exclusion chip file to the marking probe 8 (step S61).

  Subsequently, the marking probe 8 performs marking on the chips included in the excluded chip area among the chips on the semiconductor wafer 4 based on the excluded chip file (step S62). Thereafter, the semiconductor wafer 4 is physically divided into chips (step S63). Of the divided chips, the marked chips are excluded and are not commercialized (step S70).

  As described above, according to the present embodiment, since the chip to be excluded is obtained for each semiconductor wafer to be inspected even though the measurement result is a non-defective product, there is no need to originally eliminate it. Nevertheless, the number of chips to be eliminated can be reduced. Further, in obtaining a chip to be excluded although the measurement result is a non-defective product, it is based on an area (AND area) where the latent defective area and the defective area overlap. In the vicinity of the AND region, there is a high possibility that the chip contains a defect. On the other hand, in a region which is a latent defective region but does not overlap with the defective region, the possibility that the chip has a defect is very low. In this way, by using the AND region as a reference, it is possible to accurately obtain, for each individual semiconductor wafer, a chip that may have a defect even though the measurement result is a non-defective product. Therefore, the yield in the inspection process can be improved without reducing the reliability.

It is a block diagram which shows the structure of the inspection apparatus of the semiconductor wafer which concerns on this invention. 3 is a flowchart of a semiconductor wafer inspection method according to the present invention. It is a figure showing the contents of a defective chip map. It is a figure which shows the content of the latent defective area map. It is a figure which shows the superimposition of the defective chip map and the latent defective area map. It is a figure for demonstrating a forced exclusion chip | tip area | region.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Latent defect area map preparation part 2 Compulsory exclusion chip file preparation part 3 Exclusion chip file preparation part 4 Semiconductor wafer 5 to be inspected 5 Tester 6 Processing apparatus 7 System PC
8 Marking probe 9 Inspected wafer data 10 Semiconductor wafer inspection equipment

Claims (10)

A latent defect area map creation unit for creating a latent defect area map;
A forced exclusion chip file creation unit for creating a forced exclusion chip file;
An exclusion chip file creation unit for creating an exclusion chip file;
Comprising
The latent defect area map creation unit creates information indicating a region having a high probability of being defective as the latent defect area map based on the yield of each position of a semiconductor wafer chip that has already been tested,
The compulsory exclusion chip file creation unit obtains a compulsory exclusion chip area for each semiconductor wafer to be inspected based on the latent defective area map, and uses the forced exclusion chip area as information indicating the compulsory exclusion chip area. Create a file,
The exclusion chip file creation unit indicates an area obtained by combining the forced exclusion chip area and the area indicated by the defective chip map data based on the forced exclusion chip file and the defective chip map. A semiconductor wafer inspection apparatus that creates information as an excluded chip file and outputs the excluded chip file as information representing a region of a chip to be excluded on the semiconductor wafer. A latent defect area map creation unit for creating a latent defect area map;
A forced exclusion chip file creation unit for creating a forced exclusion chip file;
An exclusion chip file creation unit for creating an exclusion chip file;
Comprising
The latent defect area map creation unit creates information indicating a region having a high probability of being defective as the latent defect area map based on the yield of each position of a semiconductor wafer chip that has already been tested,
The compulsory exclusion chip file creation unit creates a latent defect area map based on a defective chip map indicating the position of a chip that has failed in an actual test of a semiconductor wafer to be inspected and the latent defect area map. An AND area that is an area where the indicated area and the area indicated in the defective chip map overlap is calculated, a forced exclusion chip area is obtained based on the AND area, and the forced exclusion chip is used as information indicating the forced exclusion chip area Create a file for
The exclusion chip file creation unit indicates an area obtained by combining the forced exclusion chip area and the area indicated by the defective chip map data based on the forced exclusion chip file and the defective chip map. A semiconductor wafer inspection apparatus that creates information as an excluded chip file and outputs the excluded chip file as information representing a region of a chip to be excluded on the semiconductor wafer. A semiconductor wafer inspection apparatus according to claim 2,
The forced exclusion chip file creation unit
When creating the forced exclusion chip file, among the areas shown in the defective chip map, the area that is position continuous and includes the AND area as a continuous defective area,
A semiconductor wafer inspection apparatus that creates the forced exclusion chip file as information indicating an area around the continuous defective area. A semiconductor wafer inspection apparatus according to claim 3,
The peripheral area is a semiconductor wafer inspection apparatus including a chip adjacent to the continuous defective area. Based on the yield for each chip position of a semiconductor wafer that has already been tested, creating information indicating a region having a high probability of being defective as a potential defect region map,
An actual measurement step for actually measuring the quality of a semiconductor wafer to be inspected on a chip basis,
Creating a defective chip map indicating a position on the semiconductor wafer of a chip that has failed in the actual measurement step;
Based on the defective chip map and the latent defective area map, obtaining an area where the area shown in the latent defective area map and the area shown in the defective chip map overlap as an AND area;
A forced exclusion chip area calculating step for obtaining a forced exclusion chip area based on the AND area; and
Obtaining a region combining the region for forced exclusion chip and the region shown in the defective chip map as a region for exclusion chip;
Out of the chips formed on the semiconductor wafer to be inspected, excluding the chips included in the exclusion chip region; and
A semiconductor wafer inspection method comprising: A semiconductor wafer inspection method according to claim 5,
The forced exclusion chip area calculation step includes:
Of the areas indicated in the defective chip map, obtaining a continuous area and an area including the AND area as a continuous defective area;
Creating a forced exclusion chip file as information indicating a region around the continuous defective region, and a method for inspecting a semiconductor wafer. A semiconductor wafer inspection method according to claim 6,
The semiconductor wafer inspection method, wherein the surrounding area is an area including a chip adjacent to the AND area. Based on the yield for each chip position of a semiconductor wafer that has already been tested, creating information indicating a region having a high probability of being defective as a potential defect region map,
Obtaining a defective chip map indicating the position of a chip that has failed in an actual measurement test of a semiconductor wafer to be inspected, and based on the defective chip map and the latent defective area map, an area indicated in the latent defective area map; Obtaining an area that overlaps the area indicated in the defective chip map as an AND area;
A forced exclusion chip area calculating step for obtaining a forced exclusion chip area based on the AND area; and
Obtaining a region combining the region for forced exclusion chip and the region shown in the defective chip map as a region for exclusion chip;
Outputting the exclusion chip file as information representing an area of a chip to be excluded on the semiconductor wafer;
Semiconductor wafer inspection program for causing a computer to execute. A semiconductor wafer inspection program according to claim 8,
The forced exclusion chip area calculation step includes:
Of the areas indicated in the defective chip map, obtaining a continuous area and an area including the AND area as a continuous defective area;
Creating a compulsory exclusion chip file as information indicating an area around the continuous defective area. A semiconductor wafer inspection program according to claim 9,
The semiconductor wafer inspection program, wherein the surrounding area is an area including a chip adjacent to the AND area.

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