JP5023529B2 - Semiconductor device - Google Patents

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JP5023529B2
JP5023529B2 JP2006084443A JP2006084443A JP5023529B2 JP 5023529 B2 JP5023529 B2 JP 5023529B2 JP 2006084443 A JP2006084443 A JP 2006084443A JP 2006084443 A JP2006084443 A JP 2006084443A JP 5023529 B2 JP5023529 B2 JP 5023529B2
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analog switch
switch element
semiconductor device
pad
bleeder resistor
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JP2007258627A (en
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岳也 池田
淳一 相沢
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Hitachi Ltd
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    • H01—ELECTRIC ELEMENTS
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor capable of measuring electrical property of a device single body without being affected by another device loaded on the semiconductor device. <P>SOLUTION: The semiconductor device separates an analog switch and bleeder resistors electrically from each other on a semiconductor substrate, and electrically connectable pads are provided at the respective ends of them. In the case of measuring the electrical property at a wafer level, the electrical property is measured through the pad, so that the electrical property as the device single body to be measured is measured without being affected by another device. After measuring the electrical property at the wafer level, the respective pads are connected with each other by wire bonding to form a circuit. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は半導体装置に係わり、半導体基板に形成された内部回路を構成する各デバイスの電気的特性を精度良く測定できる半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of accurately measuring the electrical characteristics of each device constituting an internal circuit formed on a semiconductor substrate.

アナログスイッチ素子とブリーダー抵抗とを備えた半導体装置では、図２に示すように、半導体基板上にアナログスイッチ素子３とブリーダー抵抗７、６とを形成し、それぞれをＡｌ配線またはＣｕ配線によって接続して回路を形成している。回路の入力部、出力部には電気的に接続可能なパッド４、５、８を設け、そのパッド４、５、８を介して図２に示していないパッケージに接続される。実用上、半導体装置はパッドを介して半導体基板上の回路と接続されたパッケージの端子を用いて使用される。   In a semiconductor device provided with an analog switch element and a bleeder resistor, as shown in FIG. 2, the analog switch element 3 and the bleeder resistors 7 and 6 are formed on a semiconductor substrate and are connected to each other by Al wiring or Cu wiring. The circuit is formed. Electrically connectable pads 4, 5, 8 are provided at the input part and output part of the circuit, and connected to a package not shown in FIG. 2 via the pads 4, 5, 8. In practice, a semiconductor device is used by using a terminal of a package connected to a circuit on a semiconductor substrate through a pad.

特許文献１には、測定用パッドを備えた、半導体装置の設計シミュレーション用素子が開示されている。   Patent Document 1 discloses a design simulation element of a semiconductor device provided with a measurement pad.

特開２００２−２７０６５９号公報（図１、図２、図３、図５の記載と、（００２４）段落から（００２６）段落の記載。）Japanese Patent Application Laid-Open No. 2002-270659 (Descriptions of FIGS. 1, 2, 3, and 5 and descriptions of paragraphs (0024) to (0026))

図２に示す従来技術の半導体装置では、アナログスイッチ素子３とブリーダー抵抗６、７の電気的特性を半導体チップの上でパッド４、５、８を介して測定する際に、配線が接続している他のデバイスの影響を受けるため、測定対象のデバイスの電気的特性を高い精度で測定することが困難である。   In the conventional semiconductor device shown in FIG. 2, when the electrical characteristics of the analog switch element 3 and the bleeder resistors 6 and 7 are measured on the semiconductor chip via the pads 4, 5 and 8, the wiring is connected. Therefore, it is difficult to measure the electrical characteristics of the device to be measured with high accuracy.

本発明の目的は、半導体基板に搭載した他のデバイスの影響を受けずに、デバイス単体の電気特性を高い精度で測定できる半導体装置を提供することである。   An object of the present invention is to provide a semiconductor device capable of measuring electrical characteristics of a single device with high accuracy without being affected by other devices mounted on a semiconductor substrate.

本発明の半導体装置は、アナログスイッチとブリーダー抵抗とを電気的に切り離し、それぞれの端部に電気的に接続することを可能とするパッドを半導体基板の上に配置し、デバイス間に設けたパッドを用いて電気的特性を測定し、電気的特性の測定後にそれぞれの端部に設けたパッド同士をワイヤーボンディングで接続して、回路を形成する。   In the semiconductor device of the present invention, a pad that allows an analog switch and a bleeder resistor to be electrically disconnected and electrically connected to each end portion is disposed on a semiconductor substrate, and is provided between the devices. Is used to measure the electrical characteristics, and after measuring the electrical characteristics, the pads provided at the respective ends are connected by wire bonding to form a circuit.

本発明の半導体装置は、アナログスイッチとブリーダー抵抗の電気的特性を、それぞれのデバイスが他のデバイスの影響を受けずに精度よく測定できる。   In the semiconductor device of the present invention, the electrical characteristics of the analog switch and the bleeder resistance can be accurately measured without the respective devices being affected by other devices.

本発明の半導体装置は、アナログスイッチとブリーダー抵抗とを電気的に切り離し、それぞれの端部に電気的に接続することを可能とするパッドを設けた。以下、本発明の詳細を図面を用いながら説明する。   In the semiconductor device of the present invention, the analog switch and the bleeder resistor are electrically disconnected from each other, and a pad that enables electrical connection to each end is provided. The details of the present invention will be described below with reference to the drawings.

図１に本実施例の半導体装置を示す。図１で、符号１は、シリコン半導体基板のＩＣチップ、２はアナログスイッチの駆動回路、３はアナログスイッチ素子、４、５はアナログスイッチのパッド、６、７はブリーダー抵抗、８はＧＮＤのパッド、９、１０はブリーダー抵抗のパッドを示す。本実施例では、アナログスイッチの駆動回路２や、アナログスイッチ素子３は、シリコン支持基板の上に誘電体で絶縁分離したシリコン単結晶島を備えた誘電体分離基板や、ＳＯＩ基板のシリコン単結晶島に形成してある。   FIG. 1 shows a semiconductor device of this embodiment. In FIG. 1, reference numeral 1 is an IC chip of a silicon semiconductor substrate, 2 is an analog switch drive circuit, 3 is an analog switch element, 4 and 5 are analog switch pads, 6 and 7 are bleeder resistors, and 8 is a GND pad. , 9 and 10 indicate bleeder resistance pads. In this embodiment, the analog switch drive circuit 2 and the analog switch element 3 are composed of a dielectric isolation substrate having a silicon single crystal island insulated and isolated by a dielectric on a silicon support substrate, or a silicon single crystal of an SOI substrate. It is formed on an island.

本実施例では、図１に示すように、半導体基板上に、アナログスイッチの駆動回路２と、出力部であるアナログスイッチ素子３と、ブリーダー抵抗６、７と、パッド４、５、８、９とを備える。アナログスイッチは、図１に示すように２つのＭＯＳデバイスであるＭＯＳＦＥＴを直列に接続した。本実施例の半導体装置では、図２に示した従来技術の半導体装置とは異なり、アナログスイッチ素子３とブリーダー抵抗６、７とを電気的に切り離し、それぞれの両端にパッドを備えている。このように、シリコン半導体基板上で、アナログスイッチ素子３とブリーダー抵抗６、７とがそれぞれ電気的に分離しているので、ウエハレベルでデバイスの電気的特性を測定する場合に、他のデバイスの影響を受けずに測定でき、デバイスの特性を精度よく測定できる。ウエハレベルのデバイス特性を測定した後で、所定の範囲の特性値を満たせば、図１のパッド４とパッド９、パッド５とパッド１０とをそれぞれワイヤボンディングで接続して回路を形成し、ＩＣチップ１をエポキシ樹脂組成物などで樹脂封止する。   In this embodiment, as shown in FIG. 1, an analog switch drive circuit 2, an analog switch element 3 as an output unit, bleeder resistors 6, 7 and pads 4, 5, 8, 9 are formed on a semiconductor substrate. With. As the analog switch, as shown in FIG. 1, MOSFETs, which are two MOS devices, are connected in series. In the semiconductor device of this embodiment, unlike the prior art semiconductor device shown in FIG. 2, the analog switch element 3 and the bleeder resistors 6 and 7 are electrically disconnected, and pads are provided at both ends. Thus, since the analog switch element 3 and the bleeder resistors 6 and 7 are electrically separated on the silicon semiconductor substrate, when measuring the electrical characteristics of the device at the wafer level, Measurements can be made without being affected, and device characteristics can be measured accurately. After measuring the device characteristics at the wafer level, if the characteristic values in a predetermined range are satisfied, the circuit is formed by connecting the pads 4 and 9 and the pads 5 and 10 in FIG. The chip 1 is resin-sealed with an epoxy resin composition or the like.

図３、図４に本実施例の半導体装置を示す。本実施例の半導体装置は、アナログスイッチである。図３は、実施例１の図２に示す半導体装置を、誘電体分離基板あるいはＳＯＩ基板に形成した場合の平面模式図である。図４は、図３のアナログスイッチ出力部分１２を拡大した平面模式図である。   3 and 4 show the semiconductor device of this embodiment. The semiconductor device of this embodiment is an analog switch. FIG. 3 is a schematic plan view when the semiconductor device shown in FIG. 2 according to the first embodiment is formed on a dielectric isolation substrate or an SOI substrate. FIG. 4 is an enlarged schematic plan view of the analog switch output portion 12 of FIG.

図３で、符号１はＩＣチップ、２はアナログスイッチの駆動回路、８はＧＮＤのパッド、１１はＡｌやＣｕなどの金属の配線、１２はアナログスイッチ出力部分、１９は入力のパッドである。図４で、符号３はアナログスイッチ素子、４、５、９、１０はパッド、６、７はブリーダー抵抗、１１はＡｌやＣｕなどの金属の配線、１２はアナログスイッチ出力部分、１３、１６はアナログスイッチ素子であるＭＯＳＦＥＴのソース、１４、１７はアナログスイッチ素子であるＭＯＳＦＥＴのドレイン、１５、１８はアナログスイッチ素子であるＭＯＳＦＥＴのゲートを示す。



In FIG. 3, reference numeral 1 is an IC chip, 2 is an analog switch drive circuit, 8 is a GND pad, 11 is a metal wiring such as Al or Cu, 12 is an analog switch output portion, and 19 is an input pad. 4, reference numeral 3 is an analog switch element, 4, 5, 9, 10 are pads, 6, 7 are bleeder resistors, 11 is a metal wiring such as Al or Cu, 12 is an analog switch output part, and 13 and 16 are the source of the MOSFET is an analog switching element, 14 and 17 the drain of the MOSFET is an analog switching element, 15 and 18 shows the MOSFET gate is an analog switching element.



本実施例のアナログスイッチＩＣは図３に示すように、半導体基板上に、アナログスイッチの駆動回路２と出力部であるアナログスイッチを８チャンネル備える。図４に示すように、出力部であるアナログスイッチにはそれぞれ、アナログスイッチ素子３のパッド４、５のすぐ近くにパッド９、１０を配置したブリーダー抵抗６、７を備え、全チャンネルのブリーダー抵抗のＧＮＤの配線１１を共通にして、ＧＮＤの配線１１でチップ外周部を囲んだ。   As shown in FIG. 3, the analog switch IC according to the present embodiment includes an analog switch drive circuit 2 and an analog switch as an output unit on an semiconductor substrate. As shown in FIG. 4, each analog switch as an output unit includes bleeder resistors 6 and 7 in which pads 9 and 10 are arranged in the immediate vicinity of pads 4 and 5 of the analog switch element 3, respectively. The GND wiring 11 is shared, and the GND wiring 11 surrounds the outer periphery of the chip.

なお、本実施例では図４に示すように、アナログスイッチを構成する２つのＭＳＯＦＥＴのソース１３、１６やドレイン１４、１７を線対称に配置し、アナログスイッチ素子３のパッド４、５と、ブリーダー抵抗６、７のパッド９、１０とが１つの直線の上に並ぶように配置した。また、アナログスイッチ出力部分１２は、それぞれ図３に示すようにＩＣチップ１の対向する辺に沿って各１列に配置され、入力のパッド１９と、ＧＮＤのパッド８とは、ＩＣチップ１の別の対向する辺に沿って配置してある。アナログスイッチ出力部分１２や入力のパッド１９やＧＮＤのパッド８をこのような位置に配置した。このように各パッド４、５、９、１０を配置したので、半導体チップ上でアナログスイッチ出力部分１２電気的特性を測定する際に他のデバイスの影響をより受けにくくなる。   In this embodiment, as shown in FIG. 4, the sources 13, 16 and drains 14, 17 of the two MSOFETs constituting the analog switch are arranged symmetrically with respect to the pads 4, 5 of the analog switch element 3, and the bleeder. The pads 9 and 10 of the resistors 6 and 7 are arranged so as to be aligned on one straight line. Further, the analog switch output portions 12 are respectively arranged in one row along the opposite sides of the IC chip 1 as shown in FIG. 3, and the input pad 19 and the GND pad 8 are connected to the IC chip 1. Arranged along another opposing side. The analog switch output portion 12, the input pad 19, and the GND pad 8 are arranged at such positions. Since the pads 4, 5, 9, and 10 are arranged in this manner, the analog switch output portion 12 is less affected by other devices when measuring the electrical characteristics of the analog switch output portion 12 on the semiconductor chip.

本実施例では、アナログスイッチ素子を実施例１、実施例２のＭＯＳＦＥＴの替わりに、バイポーラトランジスタを用いた。本実施例でも実施例１、実施例２と同様の効果が得られる。   In the present embodiment, a bipolar transistor is used as the analog switch element instead of the MOSFETs of the first and second embodiments. In this embodiment, the same effects as those of the first and second embodiments can be obtained.

実施例１における半導体装置の説明図である。6 is an explanatory diagram of a semiconductor device in Example 1. FIG. 従来技術の半導体装置の説明図である。It is explanatory drawing of the semiconductor device of a prior art. 実施例２の半導体装置のＩＣチップ上の配置の説明図である。FIG. 10 is an explanatory diagram of an arrangement on an IC chip of a semiconductor device of Example 2. 図３におけるアナログスイッチ出力部分を拡大した説明図である。It is explanatory drawing which expanded the analog switch output part in FIG.

符号の説明Explanation of symbols

１…ＩＣチップ、２…アナログスイッチの駆動回路、３…アナログスイッチ素子、４、５、８、９、１０、１９…パッド、６、７…ブリーダー抵抗、１１…配線、１２…アナログスイッチ出力部分、１３、１６…ソース、１４、１７…ドレイン、１５、１８…ゲート。 DESCRIPTION OF SYMBOLS 1 ... IC chip, 2 ... Analog switch drive circuit, 3 ... Analog switch element 4, 5, 8, 9, 10, 19 ... Pad, 6, 7 ... Breeder resistance, 11 ... Wiring, 12 ... Analog switch output part , 13, 16 ... source, 14 and 17 ... drain, 15, 18 ... gate.

Claims (4)

半導体基板に、複数のアナログスイッチ素子と、該アナログスイッチ素子のブリーダー抵抗と、前記アナログスイッチ素子の駆動回路とを備えた半導体装置において、
前記アナログスイッチ素子と、前記ブリーダー抵抗と、前記アナログスイッチ素子の駆動回路とが、誘電体分離基板に形成したシリコン単結晶に形成され、
前記アナログスイッチ素子と前記ブリーダー抵抗とが、前記シリコン単結晶上に形成したパッドを介してワイヤボンディングによって接続され、
前記パッドは、前記ワイヤボンディング前において、前記アナログスイッチ素子とブリーダー抵抗とを電気的に切り離し、それぞれの端部に電気的に接続可能であり、
１つの前記アナログスイッチ素子が、２つのＭＯＳＦＥＴの直列接続体であり、
前記２つのＭＯＳＦＥＴのソース、ドレインが線対称に配置され、
前記アナログスイッチ素子のパッドと、前記ブリーダー抵抗のパッド及び前記ブリーダー抵抗とを、同じ直線の上に配置すると共に、前記ソースおよびドレインの配置に対して平行に配置することを特徴とする半導体装置。 In a semiconductor device comprising a plurality of analog switch elements, a bleeder resistance of the analog switch elements, and a drive circuit for the analog switch elements on a semiconductor substrate,
The analog switch element, the bleeder resistor, and a drive circuit for the analog switch element are formed on a silicon single crystal formed on a dielectric isolation substrate,
The analog switch element and the bleeder resistor are connected by wire bonding through a pad formed on the silicon single crystal,
Before the wire bonding, the pad is electrically disconnected from the analog switch element and the bleeder resistor, and can be electrically connected to each end,
One analog switch element is a series connection body of two MOSFETs,
The sources and drains of the two MOSFETs are arranged in line symmetry,
The analog switch element pad, the bleeder resistor pad, and the bleeder resistor are arranged on the same straight line and parallel to the arrangement of the source and drain. 請求項１に記載の半導体装置において、
前記半導体基板の対向する辺に沿って、前記複数のアナログスイッチ素子を各１列に配置したことを特徴とする半導体装置。 The semiconductor device according to claim 1,
2. A semiconductor device, wherein the plurality of analog switch elements are arranged in one row along opposite sides of the semiconductor substrate. 半導体基板に、複数のアナログスイッチ素子と、該アナログスイッチ素子のブリーダー抵抗と、前記アナログスイッチ素子の駆動回路とを備えた半導体装置において、
前記アナログスイッチ素子と、前記ブリーダー抵抗と、前記アナログスイッチ素子の駆動回路とが、ＳＯＩ基板に形成したシリコン単結晶に形成され、
前記アナログスイッチ素子と前記ブリーダー抵抗とが、前記シリコン単結晶上に形成したパッドを介してワイヤボンディングによって接続され、
前記パッドは、前記ワイヤボンディング前において、前記アナログスイッチ素子とブリーダー抵抗とを電気的に切り離し、それぞれの端部に電気的に接続可能であり、
１つの前記アナログスイッチ素子が、２つのＭＯＳＦＥＴの直列接続体であり、
前記２つのＭＯＳＦＥＴのソース、ドレインが線対称に配置され、
前記アナログスイッチ素子のパッドと、前記ブリーダー抵抗のパッド及び前記ブリーダー抵抗とを、同じ直線の上に配置すると共に、前記ソースおよびドレインの配置に対して平行に配置することを特徴とする半導体装置。 In a semiconductor device comprising a plurality of analog switch elements, a bleeder resistance of the analog switch elements, and a drive circuit for the analog switch elements on a semiconductor substrate,
The analog switch element, the bleeder resistor, and the drive circuit of the analog switch element are formed on a silicon single crystal formed on an SOI substrate,
The analog switch element and the bleeder resistor are connected by wire bonding through a pad formed on the silicon single crystal,
Before the wire bonding, the pad is electrically disconnected from the analog switch element and the bleeder resistor, and can be electrically connected to each end,
One analog switch element is a series connection body of two MOSFETs,
The sources and drains of the two MOSFETs are arranged in line symmetry,
The analog switch element pad, the bleeder resistor pad, and the bleeder resistor are arranged on the same straight line and parallel to the arrangement of the source and drain. 請求項３に記載の半導体装置において、
前記半導体基板の対向する辺に沿って、前記複数のアナログスイッチ素子を各１列に配置したことを特徴とする半導体装置。 The semiconductor device according to claim 3.
2. A semiconductor device, wherein the plurality of analog switch elements are arranged in one row along opposite sides of the semiconductor substrate.
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