JP5004431B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a nonvolatile memory cell having a floating gate and a peripheral circuit such as a logic circuit. Such a semiconductor device is applied to, for example, a semiconductor device including a divided resistor circuit, a voltage detection circuit, a constant voltage generation circuit, and the like.

  There are two types of non-volatile memories called EEPROM (Electrically Erasable Programmable Read Only Memory), roughly divided by the number of gates used, one-layer gate type and two-layer gate type. Examples of the one-layer gate type include the techniques described in Patent Document 1 and Patent Document 2, and examples of the two-layer gate type include the technique described in Patent Document 3.

FIG. 39 shows a plan view of a one-layer gate type nonvolatile memory as a conventional example.
On a P-type semiconductor substrate (P substrate) 101, N-type diffusion layers 103, 105, and 107 and a control gate 109 made of the N-type diffusion layer are formed. N-type diffusion layers 103 and 105 are formed with a gap, and N-type diffusion layers 105 and 107 are formed with a gap.
On the P substrate 101 including the region between the N-type diffusion layers 103 and 105, a part of the N-type diffusion layers 103 and 105 is overlapped, and a polysilicon film is formed through a gate oxide film (not shown). A selection gate 111 is formed.

  A floating gate 113 made of a polysilicon film is continuously formed on the P substrate 101 including the region between the N-type diffusion layers 105 and 107 and the control gate 109 via a silicon oxide film (not shown). Yes. In the region near the N-type diffusion layers 105 and 107, the floating gate 113 is partially overlapped with the N-type diffusion layers 105 and 107 via the memory gate oxide film.

  When writing to this one-layer gate type nonvolatile memory, that is, when injecting electrons into the floating gate 113, the N-type diffusion layer 103 is set to 0 V (volt), the N-type diffusion layer 107 is set to a predetermined potential Vpp, This is performed by applying a predetermined potential Vpp to the control gate 109 and the selection gate 111. As a result, the transistor constituted by the N type diffusion layers 103 and 105 and the selection gate 111 is turned on, and electrons are injected from the N type diffusion layer 105 into the floating gate 113 through the memory gate oxide film.

  When erasing the one-layer gate type nonvolatile memory, that is, when electrons are emitted from the floating gate 113, the control gate 109 is set to 0 V, the N-type diffusion layer 107 is set open, and the N-type diffusion layer 103 and the selection gate 111 are set. Is performed by applying a predetermined potential Vpp. As a result, the transistor composed of the N-type diffusion layers 103 and 105 and the selection gate 111 is turned on, and electrons injected into the floating gate 113 are extracted to the N-type diffusion layer 105 through the memory gate oxide film by the tunnel effect. It is.

FIG. 40 is a sectional view of a two-layer gate type nonvolatile memory as a conventional example.
N-type diffusion layers 117 and 119 are formed on the P substrate 101 at intervals. On the P substrate 101 between the N-type diffusion layers 117 and 119, a floating gate 123 made of a polysilicon film is formed through the memory gate oxide film 121, partially overlapping with the N-type diffusion layers 117 and 119. ing. A control gate 127 made of a polysilicon film is formed on the floating gate 123 via a silicon oxide film 125.

  When writing into this two-layer gate type nonvolatile memory, that is, when injecting electrons into the floating gate 123, the N-type diffusion layer 119 is set to 0 V, the N-type diffusion layer 117 is set to a predetermined potential Vpp, and the control gate 127 is set. Is performed by applying a predetermined potential Vpp. As a result, electrons are injected from the N-type diffusion layer 119 into the floating gate 123 through the memory gate oxide film 121.

  When erasing the two-layer gate type nonvolatile memory, that is, when electrons are emitted from the floating gate 123, the control gate 127 is set to 0 V, the N-type diffusion layer 117 is set to open, and the N-type diffusion layer 119 is set to a predetermined potential. This is done by applying Vpp. As a result, electrons injected into the floating gate 123 by the tunnel effect are extracted to the N-type diffusion layer 119 through the memory gate oxide film 121.

Non-volatile memory cells that do not include a control gate are known (see, for example, Patent Document 4 and Patent Document 5).
41A is a plan view and FIG. 41B is a cross-sectional view of a nonvolatile memory not provided with a control gate. Parts having the same functions as those in FIGS. 39 and 40 are denoted by the same reference numerals.

N-type diffusion layers 103, 105, and 107 are formed on the P substrate 101. N-type diffusion layers 103 and 105 are formed with a gap, and N-type diffusion layers 105 and 107 are formed with a gap.
On the P substrate 101 including the region between the N-type diffusion layers 103 and 105, a selection gate 111 made of a polysilicon film is partially overlapped with the N-type diffusion layers 103 and 105 through the gate oxide film 129. Thus, a selection transistor is formed.
On the P substrate 101 including the region between the N-type diffusion layers 105 and 107, a floating gate 123 made of a polysilicon film is formed via a memory gate oxide film 121, thereby forming a memory transistor. In the region near the N-type diffusion layers 105 and 107, the floating gate 123 is partially overlapped with the N-type diffusion layers 105 and 107 via the memory gate oxide film.

When the nonvolatile memory is erased, that is, when electrons are emitted from the floating gate 123, the floating gate 123 of the memory transistor is initialized to have no electric charge, for example, by irradiating the floating gate 123 with ultraviolet rays.
Further, the N-type diffusion layer 103 is set to 0V, and the N-type diffusion layer 107 and the selection gate 111 are set to a predetermined potential Vpp, for example, 7V. As a result, the selection transistor composed of the N-type diffusion layers 103 and 105 and the selection gate 111 is turned on, and electrons injected into the floating gate 123 by the tunnel effect pass through the memory gate oxide film 121. Pulled out. In this case, the N-type diffusion layer 103 and the floating gate 123 are required to be sufficiently overlapped. Therefore, a buried N-type diffusion layer is set on the N-type diffusion layer 105 side below the floating gate 123 (Patent Document 4).

  When writing into the nonvolatile memory, that is, injecting electrons into the floating gate 123, 0V is applied to the N-type diffusion layer 107, Vpp, for example, 4.5V is applied to the N-type diffusion layer 103, and the selection gate 111 is set to a predetermined potential. This is done by setting Von, for example 2V. As a result, the selection transistor including the N type diffusion layers 103 and 105 and the selection gate 111 is turned on, and electrons are injected from the N type diffusion layer 105 into the floating gate 123 through the memory gate oxide film 121. Also in this case, a buried N-type diffusion layer is necessary as in the case of erasing.

  Further, in Patent Document 5, the gate oxide film of a MOS (Metal Oxide of Silicon) transistor that constitutes a peripheral circuit such as a logic circuit has the same thickness as the gate oxide film of a selection transistor and the gate oxide film of a memory transistor. It is disclosed.

JP-A-6-85275 Japanese National Patent Publication No. 8-506669 Japanese Patent Publication No. 4-80544 JP 2004-31920 A JP 2003-168747 A

  As disclosed in Patent Document 5, when the inventor of the present application prototyped and evaluated a memory transistor, a select transistor, and a peripheral circuit transistor that do not have a control gate, it was found that the charge retention characteristics were poor. The cause was mainly due to the high impurity concentration in the polysilicon of the floating gate.

  Accordingly, an object of the present invention is to improve the charge retention characteristics of a memory transistor in a semiconductor device including a non-volatile memory cell including a memory transistor having a floating gate and not including a control gate, a selection transistor, and a peripheral circuit transistor. It is what.

  A semiconductor device according to the present invention is a memory transistor comprising a MOS transistor having a memory gate oxide film formed on a semiconductor substrate and a floating gate made of electrically floating polysilicon formed on the memory gate oxide film. A selection transistor comprising a selection gate oxide film formed on the semiconductor substrate and a selection gate comprising polysilicon formed on the selection gate oxide film, and comprising a MOS transistor connected in series to the memory transistor. A non-volatile memory cell, and a peripheral circuit transistor comprising a MOS transistor having a peripheral circuit gate oxide film formed on the semiconductor substrate and a peripheral circuit gate made of polysilicon formed on the peripheral circuit gate oxide film. The impurity concentration in the polysilicon of the floating gate is It is thinner than the impurity concentration in the polysilicon of the peripheral circuit gate.

  In the semiconductor device of the present invention, an example in which the impurity concentration in the polysilicon of the selection gate is the same as the impurity concentration in the polysilicon of the floating gate can be given.

  An example in which the impurity concentration in the polysilicon of the selection gate is the same as the impurity concentration in the polysilicon of the peripheral circuit gate can be given.

In the semiconductor device of the present invention, the thickness of the memory gate oxide film that is formed thinner than the thickness of the peripheral circuit gate oxide film.
Further, the film thickness of the selection gate oxide film to be the same as the thickness of the peripheral circuit gate oxide film.

  In the semiconductor device of the present invention, an example in which the memory transistor and the selection transistor are PMOS transistors (P-channel MOS transistors) can be given.

  As an example to which the semiconductor device of the present invention is applied, a semiconductor device including a divided resistor circuit capable of obtaining a voltage output by dividing by two or more resistor elements and adjusting the voltage output by cutting a fuse element can be given. The divided resistor circuit constituting the semiconductor device includes a plurality of resistance value adjusting resistance elements connected in series, and a plurality of fuses connected in parallel as the fuse elements corresponding to the resistance value adjusting resistance elements. Comprising a MOS transistor, the nonvolatile memory cell constituting the present invention and the peripheral circuit transistor, and a readout circuit for switching on and off the fuse MOS transistor according to the storage state of the nonvolatile memory cell, The fuse MOS transistor, the MOS transistor constituting the readout circuit, or both are constituted by the peripheral circuit transistor.

  As another example to which the semiconductor device of the present invention is applied, a divided resistor circuit for dividing an input voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and the divided resistor circuit A semiconductor device provided with a voltage detection circuit having a comparison circuit for comparing the divided voltage of the reference voltage and the reference voltage from the reference voltage generation circuit can be given. As the divided resistor circuit, the divided resistor circuit to which the present invention is applied is provided.

  As still another example to which the semiconductor device of the present invention is applied, an output driver that controls output of an input voltage, a divided resistor circuit that divides the output voltage and supplies a divided voltage, and a reference voltage A constant voltage having a comparison circuit for comparing the divided voltage from the divided resistor circuit with the reference voltage from the reference voltage generating circuit and controlling the operation of the output driver according to the comparison result A semiconductor device including a generation circuit can be given. As the divided resistor circuit, the divided resistor circuit to which the present invention is applied is provided.

In the semiconductor device of the present invention, the impurity concentration in the polysilicon of the floating gate in the semiconductor device including the non-volatile memory cell including the memory transistor having the floating gate and not including the control gate and the selection transistor and the peripheral circuit transistor is Since the impurity concentration in the polysilicon of the peripheral circuit gate is made thinner, the impurity concentration in the polysilicon of the floating gate is made thinner, for example, the substantial impurity concentration is lower than 1.0 × 10 ²⁰ atoms / cm ^3. The charge retention characteristic of the memory transistor can be improved by reducing the thickness. Further, since the impurity concentration in the polysilicon can be higher than that of the floating gate with respect to the peripheral circuit gate, the resistance of the peripheral circuit gate can be sufficiently lowered, and the processing speed of the peripheral circuit transistor is prevented from being lowered. be able to.

  In the semiconductor device of the present invention, if the impurity concentration in the polysilicon of the selection gate is the same as the impurity concentration in the polysilicon of the floating gate, both gates can be formed simultaneously. In addition, the number of manufacturing steps can be reduced as compared with the case where the peripheral circuit gates are formed in separate steps.

  Further, if the impurity concentration in the polysilicon of the selection gate is the same as the impurity concentration in the polysilicon of the peripheral circuit gate, both gates can be formed at the same time, and the selection gate, floating gate and peripheral circuit gate can be formed simultaneously. The manufacturing process can be reduced as compared with the case where each is formed in a separate process.

  By the way, as disclosed in Patent Document 5, when the gate oxide film thickness is the same in the memory transistor, the selection transistor, and the peripheral circuit transistor that do not include the control gate, the gate oxide film is set to a sub-half level, for example, 7 When formed with a film thickness of about 0.5 nm (nanometer), the memory gate oxide film of the memory transistor is similarly 7.5 nm. In this case, according to the verification by the present inventor, it was found that 6 to 7 V or more is required as Vpp in order to obtain good write characteristics.

However, it is necessary to apply a voltage of, for example, 6 to 7 V or more to the peripheral circuit transistor for applying Vpp to the memory when writing to the memory transistor. In that case, an electric field reaching 10 MV / cm (megavolt / cm) is applied to the gate oxide film of the peripheral circuit transistor having a thin film thickness of 7.5 nm, which may damage the peripheral circuit gate oxide film. There is a possibility that the yield and reliability of the apparatus may be reduced.
Further, according to the verification by the present inventor, since the snapback voltage of the NMOS transistor (N-channel MOS transistor) having a gate oxide film thickness of 7.5 nm is about 6 to 7 V, which is about the same as the above Vpp, The peripheral circuit is likely to be damaged. Also from this aspect, there is a possibility that the yield and reliability of the semiconductor device may be reduced.

  In order to prevent such a problem, even if the gate oxide films of the memory transistor, the selection transistor, and the peripheral circuit transistor are formed at a half level, for example, about 13.5 nm, the thickness of the gate oxide film is increased. Since the write voltage Vpp increases, the above problem at the sub-half level is not solved. That is, when the gate oxide film is formed with a thickness of about 13.5 nm and Vpp is set to 6 to 7 V, the peripheral circuit gate oxide film can be prevented from being damaged, but the memory gate oxide film of the memory transistor is 13.5 nm. However, since the film thickness is large, there is a possibility that good writing characteristics cannot be obtained.

Therefore, in the semiconductor device of the present invention, the thickness of the memory gate oxide film is made thinner than that of the peripheral circuit gate oxide film . As a result, the peripheral circuit gate oxide film thickness can be increased to such an extent that the peripheral circuit gate oxide film is not damaged when writing to the memory transistor, and the memory gate oxide film thickness can be decreased to such an extent that good write characteristics of the memory transistor can be obtained. Thus, the memory transistor can be satisfactorily written while preventing damage to the peripheral circuit gate oxide film and without causing snapback breakdown.

Furthermore, in the semiconductor device of the present invention, the thickness of the select gate oxide film is made the same as the thickness of the peripheral circuit gate oxide film . As a result, both gate oxide films can be formed at the same time, and the number of manufacturing steps can be reduced compared to the case where the selection gate oxide film, the memory gate oxide film, and the peripheral circuit gate oxide film are formed in separate processes. . Furthermore, since the selection gate oxide film thickness is thicker than when the selection gate oxide film thickness and the memory gate oxide film thickness are the same, the breakdown voltage of the selection transistor can be improved.

  Further, in the semiconductor device of the present invention, if the memory transistor and the selection transistor are PMOS transistors (write voltage 6 to 7V), compared to the case of using a memory transistor (write voltage 10V or so) made of an NMOS transistor, There is no need to use a so-called control gate for writing, and the writing voltage can be lowered. However, the memory transistor and the selection transistor are not limited to PMOS transistors, and both transistors may be NMOS transistors.

  In a semiconductor device having a divided resistor circuit capable of obtaining a voltage output by dividing by two or more resistor elements and adjusting the voltage output by cutting a fuse element, the divided resistor circuit is for adjusting a plurality of resistance values connected in series. A resistance element; a plurality of fuse MOS transistors connected in parallel as resistance elements for resistance value adjustment as fuse elements; a nonvolatile memory cell and a peripheral circuit transistor constituting the present invention; and a nonvolatile memory cell If a readout circuit for switching on and off the fuse MOS transistor according to the storage state is provided, and the fuse MOS transistor and / or the MOS transistor constituting the readout circuit are constituted by peripheral circuit transistors , Storage state of non-volatile memory cells with good write characteristics The output voltage of the dividing resistor circuit according can be adjusted. Furthermore, the output voltage of the divided resistor circuit can be reset by changing the storage state of the nonvolatile memory cell.

  The divided resistor circuit for dividing the input voltage and supplying the divided voltage, the reference voltage generating circuit for supplying the reference voltage, and the divided voltage from the divided resistor circuit and the reference voltage from the reference voltage generating circuit are compared. In a semiconductor device having a voltage detection circuit having a comparison circuit for the purpose, if the division resistance circuit to which the present invention is applied is provided as the division resistance circuit, the storage state of the nonvolatile memory cell is changed. The output voltage setting of the voltage detection circuit can be changed.

  An output driver for controlling the output of the input voltage; a dividing resistor circuit for dividing the output voltage to supply a divided voltage; a reference voltage generating circuit for supplying a reference voltage; and a divided voltage from the dividing resistor circuit; The present invention is applied as a divided resistor circuit in a semiconductor device having a constant voltage generation circuit having a comparison circuit for comparing a reference voltage from a reference voltage generation circuit and controlling the operation of an output driver according to the comparison result. If the divided resistor circuit is provided, the output voltage setting of the constant voltage generating circuit can be changed by changing the storage state of the nonvolatile memory cell.

1A and 1B are diagrams showing a reference example, in which FIG. 1A is a plan view of a memory cell, FIG. 1B is a plan view of a peripheral circuit transistor, and FIG. 1C is a cross-sectional view at the position AA ′. FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. This reference example will be described with reference to FIG.

  An N well 2 is formed in a predetermined region of the P substrate 1. A field oxide film 3 for element isolation is formed on the surface of the P substrate 1 with a film thickness of, for example, 450 to 700 nm, here 500 nm. P type diffusion layers 5, 7, 9 are formed in the N well 2 in a region surrounded by the field oxide film 3. The P-type diffusion layers 5 and 7 are formed with an interval, and the P-type diffusion layers 7 and 9 are formed with an interval.

On the P substrate 1 including the region between the P-type diffusion layers 5 and 7, a select gate oxide film 11 having a film thickness of, for example, 10.0 to 15.0 nm, here 13.5 nm, is formed. On the selection gate oxide film 11, a selection gate 13 made of a polysilicon film having a thickness of, for example, 250 to 450 nm, here 350 nm, is formed so as to partially overlap with the P-type diffusion layers 5 and 7. For example, phosphorus is introduced into the selection gate 13 as an N-type impurity, and the substantial phosphorus concentration is 7.0 × 10 ^{18 to} 5.0 × 10 ¹⁹ atoms / cm ³ . The P-type diffusion layers 5 and 7, the selection gate oxide film 11 and the selection gate 13 constitute a selection transistor.

On the surface of the P substrate 1 including the region between the P-type diffusion layers 7 and 9, a memory gate oxide film 15 having a film thickness of, for example, 10.0 to 15.0 nm, here 13.5 nm, is formed. A floating gate 17 made of a polysilicon film having a thickness of, for example, 250 to 450 nm, here 350 nm, is formed on the memory gate oxide film 15 so as to partially overlap with the P-type diffusion layers 7 and 9. For example, phosphorus is introduced into the floating gate 17 as an N-type impurity, and the substantial phosphorus concentration is 7.0 × 10 ^{18 to} 5.0 × 10 ¹⁹ atoms / cm ³ . P-type diffusion layers 7 and 9, memory gate oxide film 15 and floating gate 17 constitute a memory transistor.
The selection transistor and the memory transistor constitute a memory cell.

P-type diffusion layers 19 and 21 are formed in N well 2 in a region surrounded by field oxide film 3 in a region different from the memory cell. The P-type diffusion layers 19 and 21 are formed with an interval.
A peripheral circuit gate oxide film 23 having a film thickness of, for example, 10.0 to 15.0 nm, here 13.5 nm, is formed on the P substrate 1 including the region between the P-type diffusion layers 19 and 21. On the peripheral circuit gate oxide film 23, a peripheral circuit gate 25 made of a polysilicon film having a thickness of, for example, 250 to 450 nm, here 350 nm, is partially overlapped with the P-type diffusion layers 19 and 21. For example, phosphorus as an N-type impurity is introduced into the peripheral circuit gate 25 at a higher concentration than the selection gate 13 and the floating gate 17, and the substantial phosphorus concentration is 1.0 × 10 ²⁰ atoms / cm ³ or more. The P-type diffusion layers 19 and 21, the peripheral circuit gate oxide film 23, and the peripheral circuit gate 25 constitute a peripheral circuit transistor.

In this reference example , the impurity concentration of the floating gate 17 is formed thinner than the impurity concentration of the peripheral circuit gate 25, so that the charge retention characteristics of the memory transistor can be improved.
Furthermore, since the impurity concentration of the peripheral circuit gate 25 is higher than that of the floating gate 17, the resistance of the peripheral circuit gate 25 can be made sufficiently low to prevent the processing speed of the peripheral circuit transistor from being lowered. it can.

FIG. 2 is a diagram showing the results of examining the charge retention characteristics of the memory transistor. The vertical axis represents the threshold voltage of the memory transistor (unit: volts (V)), and the horizontal axis represents elapsed time (unit: time (h)). Here, the heating temperature was 250 degrees. As a sample, the substantial phosphorus concentration of the floating gate is 3.0 × 10 ¹⁹ atoms / cm ³ (invention), and as a comparative example, the substantial phosphorus concentration of the floating gate is 1.0 × 10 ²⁰ atoms / cm ^3. A cm ³ or more (conventional example) was used. Phosphorus was introduced into the floating gate of the conventional example by phosphorus deposition and thermal diffusion.

  From FIG. 2, it can be seen that the charge retention characteristics of the memory transistor of the present invention in which the phosphorus concentration of the floating gate is reduced are improved as compared with the conventional example in which phosphorus is introduced into the floating gate at a high concentration.

FIG. 3 is a circuit diagram showing an example when the memory cells of the reference example of FIG. 1 are arranged in a matrix. This circuit configuration can also be applied to each embodiment and each reference example described below.
Memory cells are arranged in a matrix. The selection gates 13 of the cells i0, i1,... Arranged in the horizontal direction (word line WL direction) are electrically connected to the common word line WLi. The P-type diffusion layer 5 is electrically connected to a common source line SLi. The P type diffusion layers 9 of the cells 0i, 1i,... Arranged in the vertical direction (bit line Bit direction) are electrically connected to the common bit line Biti. Here, i is 0 or a natural number.

At the time of erasing, all cells are erased at once by ultraviolet irradiation.
At the time of writing, for example, when writing only the cell 00, the word line WL0 and the bit line Bit0 connected to the cell 00 to be written are biased to a predetermined potential −Vpp, and other word lines WLi and other bit lines Biti or source Line SLi is biased to 0V. As a result, electrons are injected into the floating gate 17 of the cell 00 through the memory gate oxide film and written.

FIG. 4 is a process cross-sectional view for explaining an example of a manufacturing method for manufacturing the reference example of FIG. 1, and corresponds to the positions AA ′ and BB ′ of FIG. An example of this manufacturing method will be described with reference to FIGS.

(1) After the N well 2 is formed on the P substrate 1, a field oxide film 3 (see FIG. 1) is formed on the P substrate 1 by a normal LOCOS (local oxidation of silicon) method to perform element isolation. . On the surface of the active region defined by the field oxide film 3, gate oxide films 11, 15, and 23 are formed with a film thickness of 13.5 nm, for example, and channel dope implantation is performed. A non-doped polysilicon film is formed on the entire surface of the P substrate 1, and, for example, phosphorus is implanted into the non-doped polysilicon film with an implantation amount of 5.0 × 10 ¹⁵ atoms / cm ² by ion implantation to form a polysilicon film 27. (See FIG. 4A).

(2) An HTO (High Temperature Oxide) film 29 is formed on the polysilicon film 27 so as to cover the formation region of the memory transistor and the selection transistor region and to have an opening in the formation region of the peripheral circuit transistor. PSG (phospho silicate glass, not shown) is deposited on the polysilicon film 27 and the HTO film 29, and phosphorus is thermally diffused in the polysilicon film 27 in the formation region of the peripheral circuit transistor to form the polysilicon film 31. (See FIG. 4B.)

(3) After removing the PSG and the HTO film 29, the selection gate 13 is formed on the field oxide film 3 and the selection gate oxide film 11 in the selection transistor region from the polysilicon film 27 by photolithography and etching techniques. The floating gate 17 is formed on the field oxide film 3 and the memory gate oxide film 15 in the memory transistor region, and from the polysilicon film 31 onto the field oxide film 3 and the peripheral circuit gate oxide film 23 in the peripheral circuit transistor region. A peripheral circuit gate 25 is formed (see FIG. 4C).
Here, after the PSG and the HTO film 29 are removed, an HTO film is formed on the entire surface, and the HTO film and the polysilicon films 27 and 31 are patterned by photolithography and etching techniques. on the upper and the peripheral circuit gate 25 previously formed the HTO film pattern, the selection gate 13 in BF ₂ implantation step in a subsequent step, the floating gate 17 and the peripheral circuit gate 25 may be BF ₂ are not implanted. Also in each of the manufacturing method examples described later, when it is not desired to implant the impurity implantation into the polysilicon gate after patterning, an impurity implantation preventing film such as an HTO film is formed on the polysilicon film before patterning, and the impurity implantation is performed. By patterning the prevention film and the polysilicon film to form a laminated pattern of the impurity implantation prevention film and the polysilicon gate, it is possible to prevent impurity implantation from being implanted into the polysilicon gate in the post-patterning process. it can.

(4) BF ₂ is implanted by ion implantation using the selection gate 13, the floating gate 17 and the peripheral circuit gate 25 as a mask to form P type diffusion layers 5, 7, 9, 19, 21 (FIG. 1). reference.).

In the reference example of FIG. 1, since the impurity concentration of the selection gate 13 is the same as that of the floating gate 17, both the gates 13 and 17 can be formed at the same time, and the selection gate 13, the floating gate 17 and the peripheral circuit gate 25 are respectively formed. The manufacturing process can be reduced as compared with the case of forming in a separate process.

5A and 5B are diagrams illustrating a reference example, in which FIG. 5A is a plan view of a memory cell, FIG. 5B is a plan view of a peripheral circuit transistor, and FIG. FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This reference example is different from the reference example described with reference to FIG. 1 in that, for example, boron is introduced as a P-type impurity in the polysilicon of the selection gate 33 and the floating gate 35, and phosphorus is not introduced. It is. The boron concentration of the selection gate 33 and the floating gate 35 is, for example, 7.0 × 10 ^{18 to} 5.0 × 10 ¹⁹ atoms / cm ³ .

In this reference example , the impurity concentration of the floating gate 35 is formed lower than the impurity concentration of the peripheral circuit gate 25, so that the charge retention characteristics of the memory transistor can be improved.
Further, since the impurity concentration of the peripheral circuit gate 25 is higher than that of the floating gate 35, the resistance of the peripheral circuit gate 25 can be sufficiently lowered, and the processing speed of the peripheral circuit transistor can be prevented from being lowered. it can.

FIG. 6 is a process cross-sectional view for explaining an example of the manufacturing method for manufacturing the reference example of FIG. 5, and corresponds to the positions AA ′ and BB ′ of FIG. An example of the manufacturing method will be described with reference to FIGS.

(1) The N well 2, field oxide film 3 (see FIG. 5), gate oxide film 11, gate oxide film 11, P substrate 1 by the same process as the above process (1) described with reference to FIG. After forming 15 and 23 and performing channel dope implantation, a non-doped polysilicon film 37 is formed on the entire surface of the P substrate 1 (see FIG. 6A).

(2) On the non-doped polysilicon film 37, an HTO film 29 is formed which covers the formation region of the memory transistor and the selection transistor region and has an opening in the formation region of the peripheral circuit transistor. PSG (not shown) is deposited on the non-doped polysilicon film 37 and the HTO film 29, and phosphorus is thermally diffused in the non-doped polysilicon film 37 in the peripheral circuit transistor formation region to form a polysilicon film 31 (FIG. (See 6 (B).)

(3) After removing the PSG and the HTO film 29, the selection gate 33 is formed on the field oxide film 3 and the selection gate oxide film 11 in the selection transistor region from the non-doped polysilicon film 37 by photolithography and etching techniques. Then, the floating gate 35 is formed on the field oxide film 3 and the memory gate oxide film 15 in the memory transistor region, and from the polysilicon film 31 on the field oxide film 3 and the peripheral circuit gate oxide film 23 in the peripheral circuit transistor region. Then, the peripheral circuit gate 25 is formed (see FIG. 6C).

(4) BF ₂ is implanted by ion implantation at an implantation amount of, for example, 3.0 to 5.0 × 10 ¹⁵ atoms / cm ³ using the selection gate 33, the floating gate 35 and the peripheral circuit gate 25 as a mask. P-type diffusion layers 5, 7, 9, 19, and 21 are formed, and boron is implanted into the selection gate 33 and the floating gate 35 (see FIG. 5).

In the reference example of FIG. 5, since the impurity concentration of the selection gate 33 is the same as that of the floating gate 35, both the gates 33 and 35 can be formed at the same time. The selection gate 33, the floating gate 35 and the peripheral circuit gate 25 are respectively The manufacturing process can be reduced as compared with the case of forming in a separate process.

7A and 7B are diagrams showing a reference example, in which FIG. 7A is a plan view of a memory cell, FIG. 7B is a plan view of a peripheral circuit transistor, and FIG. 7C is a cross-sectional view at the position AA ′. FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This reference example is different from the reference example described with reference to FIG. 1 in that the selection gate 39 is formed at the same time as the peripheral circuit gate 25, and phosphorus is used as the N-type impurity in the selection gate 39. It is introduced at a higher concentration, and the substantial phosphorus concentration is 1.0 × 10 ²⁰ atoms / cm ³ or more.

In this reference example , the impurity concentration of the floating gate 17 is formed to be lower than the impurity concentration of the peripheral circuit gate 25 as in the above-described reference example described with reference to FIG. Can be improved.
Further, since the impurity concentration of the peripheral circuit gate 25 and the selection gate 39 is higher than that of the floating gate 17, the resistance of the peripheral circuit gate 25 and the selection gate 39 can be made sufficiently low. It is possible to prevent the processing speed from decreasing.

FIG. 8 is a process cross-sectional view for explaining an example of the manufacturing method for manufacturing the reference example of FIG. 7, and corresponds to the positions AA ′ and BB ′ of FIG. An example of this manufacturing method will be described with reference to FIGS.

(1) N well 2, field oxide film 3 (see FIG. 7), gate oxide films 11, 15 on P substrate 1 by the same process as the above process (1) described with reference to FIG. , 23 and a polysilicon film 27 are formed (see FIG. 8A).

(2) On the polysilicon film 27, an HTO film 41 is formed which covers the memory transistor formation region and has openings in the peripheral circuit transistor and selection transistor region formation regions. PSG (not shown) is deposited on the polysilicon film 27 and the HTO film 41 , and phosphorus is thermally diffused in the polysilicon film 27 in the formation region of the peripheral circuit transistor and the selection transistor region, thereby forming the polysilicon film 31. (See FIG. 8B.)

(3) After removing the PSG and the HTO film 41 , the floating gate 17 is formed on the field oxide film 3 and the memory gate oxide film 15 in the memory transistor region from the polysilicon film 27 by photolithography and etching techniques. A selection gate 39 is formed from the polysilicon film 31 on the field oxide film 3 and the selection gate oxide film 11 in the selection transistor region, and on the field oxide film 3 and the peripheral circuit gate oxide film 23 in the peripheral circuit transistor region. A peripheral circuit gate 25 is formed (see FIG. 8C).
Here, after the PSG and the HTO film 29 are removed, an HTO film is formed on the entire surface, and the HTO film and the polysilicon films 27 and 31 are patterned by photolithography and etching techniques. on the upper and the peripheral circuit gate 25 previously formed the HTO film pattern, the selection gate 39 in BF ₂ implantation step in a subsequent step, the floating gate 17 and the peripheral circuit gate 25 may be BF ₂ are not implanted.

(4) BF ₂ is implanted by ion implantation using the selection gate 13, the floating gate 17 and the peripheral circuit gate 25 as a mask to form P-type diffusion layers 5, 7, 9, 19, 21 (FIG. 7). reference.).

In the reference example of FIG. 7, since the impurity concentration of the selection gate 39 is the same as that of the peripheral circuit gate 25, both the gates 25 and 37 can be formed at the same time, and the selection gate 39, the floating gate 17 and the peripheral circuit gate 25 are formed. The number of manufacturing steps can be reduced as compared with the case of forming in separate steps.

9A and 9B are diagrams showing a reference example, in which FIG. 9A is a plan view of a memory cell, FIG. 9B is a plan view of a peripheral circuit transistor, FIG. 9C is a cross-sectional view at the position AA ′, FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIGS. 1, 5, and 7 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This reference example is different from the reference example described with reference to FIG. 5 in that the selection gate 39 is formed at the same time as the peripheral circuit gate 25, and phosphorus, for example, as an N-type impurity is added to the selection gate 39. It is introduced at a higher concentration, and the substantial phosphorus concentration is 1.0 × 10 ²⁰ atoms / cm ³ or more.

In this reference example , as in the above-described reference example described with reference to FIG. 5, the impurity concentration of the floating gate 35 is formed lower than the impurity concentration of the peripheral circuit gate 25. Can be improved.
Further, since the impurity concentration of the peripheral circuit gate 25 and the selection gate 39 is higher than that of the floating gate 35, the resistance of the peripheral circuit gate 25 and the selection gate 39 can be made sufficiently low. It is possible to prevent the processing speed from decreasing.

FIG. 10 is a process cross-sectional view for explaining an example of the manufacturing method for manufacturing the reference example of FIG. 9, and corresponds to the positions AA ′ and BB ′ of FIG. This manufacturing method example will be described with reference to FIGS.

(1) FIG. 6 (A) the same process as the above step (1) described with reference to, N-well 2, the field oxide film 3 to P substrate 1 (see FIG. 9.), A gate oxide film 11 and 15 , 23 and a non-doped polysilicon film 37 are formed (see FIG. 10A).

(2) An HTO film 41 is formed on the non-doped polysilicon film 37 so as to cover the memory transistor formation region and have openings in the peripheral circuit transistor and selection transistor region formation regions. PSG (not shown) is deposited on the non-doped polysilicon film 37 and the HTO film 41, and phosphorus is thermally diffused in the non-doped polysilicon film 37 in the formation region of the peripheral circuit transistor and the selection transistor region to form the polysilicon film 31. It is formed (see FIG. 10B).

(3) After removing the PSG and the HTO film 41, the floating gate 35 is formed on the field oxide film 3 and the memory gate oxide film 15 in the memory transistor region from the non-doped polysilicon film 37 by photolithography and etching techniques. Then, a selection gate 39 is formed from the polysilicon film 31 on the field oxide film 3 and the selection gate oxide film 11 in the selection transistor region, and on the field oxide film 3 and the peripheral circuit gate oxide film 23 in the peripheral circuit transistor region. forming a peripheral circuit gate 25 (see FIG. 10 (C).).

(4) BF ₂ is implanted by ion implantation, for example, at an implantation amount of 3.0 to 5.0 × 10 ¹⁵ atoms / cm ³ using the selection gate 39, the floating gate 35 and the peripheral circuit gate 25 as a mask. P-type diffusion layers 5, 7, 9, 19, and 21 are formed, and boron is implanted into the floating gate 35 (see FIG. 9).

In the reference example of FIG. 9, since the impurity concentration of the selection gate 39 is the same as that of the peripheral circuit gate 25, both the gates 25 and 37 can be formed at the same time, and the selection gate 39, the floating gate 35 and the peripheral circuit gate 25 are formed. The number of manufacturing steps can be reduced as compared with the case of forming in separate steps.

11A and 11B are diagrams illustrating a reference example, in which FIG. 11A is a plan view of a memory cell, FIG. 11B is a plan view of a peripheral circuit transistor, and FIG. 11C is a cross-sectional view at the position AA ′. FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

An N well 2 is formed in a predetermined region of the P substrate 1, and a field oxide film 3 is formed on the surface of the P substrate 1.
A selection transistor including P-type diffusion layers 5 and 7, a selection gate oxide film 43 and a selection gate 13 is formed in the selection transistor region.
A memory transistor including P-type diffusion layers 7 and 9, a memory gate oxide film 45 and a floating gate 17 is formed in the memory transistor region.
Peripheral circuit transistors including P-type diffusion layers 19 and 21, peripheral circuit gate oxide film 47 and peripheral circuit gate 25 are formed in the peripheral circuit transistor region.

The selection gate oxide film 43 and the memory gate oxide film 45 are formed in the same process. The peripheral circuit gate oxide film 47 is formed separately from the selection gate oxide film 43 and the memory gate oxide film 45. The thicknesses of the select gate oxide film 43 and the memory gate oxide film 45 are, for example, 6.0 to 10.0 nm, and 7.5 nm here. The film thickness of the peripheral circuit gate oxide film 47 is, for example, 10.0 to 15.0 nm, here 13.5 nm.
A silicon oxide film 49 is formed on the surface of the selection gate 13 and the surface of the floating gate 17.

In this reference example , the impurity concentration of the floating gate 17 is formed thinner than the impurity concentration of the peripheral circuit gate 25 as in the above-described reference example described with reference to FIG. Can be improved.
Further, since the impurity concentration of the peripheral circuit gate 25 is higher than that of the floating gate 17, the resistance of the peripheral circuit gate 25 can be sufficiently lowered, and the processing speed of the peripheral circuit transistor and the selection transistor is prevented from being lowered. can do.

  Furthermore, since the film thickness of the memory gate oxide film 45 is smaller than the film thickness of the peripheral circuit gate oxide film 47, the peripheral circuit gate oxide film is not damaged to the extent that the peripheral circuit gate oxide film 47 is damaged when writing to the memory transistor. By increasing the thickness, the memory gate oxide film thickness can be reduced to such an extent that good write characteristics of the memory transistor can be obtained. As a result, it is possible to perform good writing of the memory transistor while preventing damage to the peripheral circuit gate oxide film 47 and without causing snapback destruction.

FIG. 12 is a process cross-sectional view for explaining an example of the manufacturing method for manufacturing the reference example of FIG. 11, and corresponds to the positions AA ′ and BB ′ of FIG. An example of the manufacturing method will be described with reference to FIGS.

(1) After forming the N well 2 on the P substrate 1, a field oxide film 3 (see FIG. 11) is formed on the P substrate 1 by a normal LOCOS method to perform element isolation. Gate oxide films 43 and 45 are formed to a thickness of, for example, 7.5 nm on the surface of the active region defined by the field oxide film 3, and channel dope implantation is performed. A non-doped polysilicon film is formed on the entire surface of the P substrate 1, and, for example, phosphorus is implanted into the non-doped polysilicon film at a dose of 5.0 × 10 ¹⁵ atoms / cm ² by ion implantation to form a polysilicon film. . The polysilicon film is patterned by photolithography and etching techniques to form a selection gate 13 on the field oxide film 3 and the selection gate oxide film 43 in the selection transistor region, and on the field oxide film 3 in the memory transistor region. The floating gate 17 is formed on the memory gate oxide film 45. Using the field oxide film 3, select gate 13 and floating gate 17 as a mask, the oxide film on the surface of the P substrate 1 is removed. When the oxide film is removed, the selection transistor region and the memory transistor region may be covered using photolithography (see FIG. 12A).

(2) A thermal oxidation process is performed to form a gate oxide film 47 having a thickness of 13.5 nm, for example. At this time, a silicon oxide film 49 is formed on the surface of the select gate 13 and the surface of the floating gate 17. A non-doped polysilicon film is formed on the entire surface of the P substrate 1, further PSG (not shown) is deposited thereon, and phosphorus is thermally diffused in the non-doped polysilicon film to form a polysilicon film 31 (FIG. 12 ( See B).

(3) After the PSG is removed, the peripheral circuit gate 25 is formed on the field oxide film 3 and the peripheral circuit gate oxide film 47 in the peripheral circuit transistor region from the polysilicon film 31 by photolithography and etching techniques ( (See FIG. 12C).

(4) BF ₂ is implanted by ion implantation using the selection gate 13, the floating gate 17 and the peripheral circuit gate 25 as a mask to form P-type diffusion layers 5, 7, 9, 19, and 21 (FIG. 11). reference.).

In the reference example of FIG. 11, since the impurity concentration of the selection gate 13 is the same as that of the floating gate 17, both the gates 13 and 17 can be formed at the same time, and the selection gate 13, the floating gate 17 and the peripheral circuit gate 25 are respectively formed. The manufacturing process can be reduced as compared with the case of forming in a separate process.

  Further, since the thickness of the select gate oxide film 43 is the same as the thickness of the memory gate oxide film 45, both the gate oxide films 43 and 45 can be formed simultaneously. The number of manufacturing steps can be reduced as compared with the case where 45 and the peripheral circuit gate oxide film 47 are formed in separate steps.

13A and 13B are diagrams showing a reference example, in which FIG. 13A is a plan view of a memory cell, FIG. 13B is a plan view of a peripheral circuit transistor, and FIG. 13C is a cross-sectional view at the position AA ′. FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIGS. 1, 5 and 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The reference example differs from the reference example described with reference to FIG. 11 is introduced boron into the polysilicon of the selection gate 33 and the floating gate 35 as, for example, P-type impurity, that phosphorus is not introduced It is. The boron concentration of the selection gate 33 and the floating gate 35 is, for example, 7.0 × 10 ^{18 to} 5.0 × 10 ¹⁹ atoms / cm ³ .
A silicon oxide film 49 is formed on the surface of the selection gate 33 and the surface of the floating gate 35.

In this reference example , the impurity concentration of the floating gate 35 is formed lower than the impurity concentration of the peripheral circuit gate 25 as in the above-described reference example described with reference to FIG. Can be improved. Further, since the impurity concentration of the peripheral circuit gate 25 is higher than that of the floating gate 35, the resistance of the peripheral circuit gate 25 can be sufficiently lowered, and the processing speed of the peripheral circuit transistor can be prevented from being lowered. it can.

Further, similarly to the above-described reference example described with reference to FIG. 11, the memory gate oxide film 45 is formed thinner than the peripheral circuit gate oxide film 47, so that the peripheral circuit gate oxide film 47 is formed. Thus, the memory transistor can be satisfactorily written without causing a snapback breakdown.

FIG. 14 is a process cross-sectional view for explaining an example of the manufacturing method for manufacturing the reference example of FIG. 13 and corresponds to the positions AA ′ and BB ′ of FIG. 13. This manufacturing method example will be described with reference to FIGS.

(1) After forming the N well 2 on the P substrate 1, a field oxide film 3 (see FIG. 13) is formed on the P substrate 1 by a normal LOCOS method, and element isolation is performed. Gate oxide films 43 and 45 are formed to a thickness of, for example, 7.5 nm on the surface of the active region defined by the field oxide film 3, and channel dope implantation is performed. A non-doped polysilicon film is formed on the entire surface of the P substrate 1. The non-doped polysilicon film is patterned by photolithography and etching techniques to form a selection gate 33 on the field oxide film 3 and the selection gate oxide film 43 in the selection transistor region, and on the field oxide film 3 in the memory transistor region. A floating gate 35 is formed on the memory gate oxide film 45. Using the field oxide film 3, the select gate 33 and the floating gate 35 as a mask, the oxide film on the surface of the P substrate 1 is removed. When the oxide film is removed, the selection transistor region and the memory transistor region may be covered using a photoengraving technique (see FIG. 14A).

(2) A gate oxide film 47 and a silicon oxide film 49 are formed by the same process as the process (2) described with reference to FIG. 12B, and a polysilicon film 31 is further formed (FIG. 14B). )reference.).

(3) The peripheral circuit gate 25 is formed on the field oxide film 3 and the peripheral circuit gate oxide film 47 in the peripheral circuit transistor region by the same process as the process (3) described with reference to FIG. (See FIG. 14C.)

(4) BF ₂ is implanted by ion implantation at an implantation amount of, for example, 3.0 to 5.0 × 10 ¹⁵ atoms / cm ³ using the selection gate 33, the floating gate 35 and the peripheral circuit gate 25 as a mask. P-type diffusion layers 5, 7, 9, 19, and 21 are formed, and boron is implanted into the selection gate 33 and the floating gate 35 (see FIG. 13).

In the reference example of FIG. 13, since the impurity concentration of the selection gate 33 is the same as that of the floating gate 35, both the gates 33 and 35 can be formed simultaneously, and the selection gate 33, the floating gate 35, and the peripheral circuit gate 25 are respectively formed. The manufacturing process can be reduced as compared with the case of forming in a separate process.

  Further, since the thickness of the select gate oxide film 43 is the same as the thickness of the memory gate oxide film 45, both the gate oxide films 43 and 45 can be formed simultaneously. The number of manufacturing steps can be reduced as compared with the case where 45 and the peripheral circuit gate oxide film 47 are formed in separate steps.

FIGS. 15A and 15B are diagrams showing a reference example, in which FIG. 15A is a plan view of a memory cell, FIG. 15B is a plan view of a peripheral circuit transistor, and FIG. FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIGS. 1 and 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The reference example differs from the reference example described with reference to FIG. 11, the surface and (see Figure 11.) Silicon oxide film 49 on the surface of the floating gate 17 of the select gate 13 is not formed, the peripheral The silicon oxide film 51 is formed on the surface of the circuit gate 25.

In this reference example , the impurity concentration of the floating gate 17 is formed thinner than the impurity concentration of the peripheral circuit gate 25 as in the above-described reference example described with reference to FIG. Can be improved.
Further, since the impurity concentration of the peripheral circuit gate 25 is higher than that of the floating gate 17, the resistance of the peripheral circuit gate 25 can be sufficiently lowered, and the processing speed of the peripheral circuit transistor and the selection transistor is prevented from being lowered. can do.
Furthermore, since the film thickness of the memory gate oxide film 45 is formed thinner than the film thickness of the peripheral circuit gate oxide film 47, damage to the peripheral circuit gate oxide film 47 is prevented and without causing snapback breakdown. Good writing of the memory transistor can be performed.

FIG. 16 is a process cross-sectional view for explaining an example of the manufacturing method for manufacturing the reference example of FIG. 15, and corresponds to the positions AA ′ and BB ′ of FIG. An example of the manufacturing method will be described with reference to FIGS.

(1) After forming the N well 2 on the P substrate 1, a field oxide film 3 (see FIG. 15) is formed on the P substrate 1 by a normal LOCOS method to perform element isolation. A peripheral circuit gate oxide film 47 is formed with a film thickness of 13.5 nm, for example, on the surface of the active region defined by the field oxide film 15, and channel dope implantation is performed. A non-doped polysilicon film is formed on the entire surface of the P substrate 1, further PSG is deposited thereon, and phosphorus is diffused into the non-doped polysilicon film by thermal diffusion treatment. After the PSG is removed, the polysilicon film is patterned by photolithography and etching techniques to form the peripheral circuit gate 25 on the field oxide film 3 and the peripheral circuit gate oxide film 47 in the peripheral circuit transistor region. Using the field oxide film 3 and the peripheral circuit gate 25 as a mask, the oxide film on the surface of the P substrate 1 is removed. When the oxide film is removed, the peripheral circuit transistor region may be covered by photolithography (see FIG. 16A).

(2) Thermal oxidation is performed to form gate oxide films 43 and 45 with a thickness of, for example, 7.5 nm. At this time, a silicon oxide film 51 is formed on the surface of the peripheral circuit gate 25. After a non-doped polysilicon film is formed on the entire surface of the P substrate 1, for example, phosphorus is implanted into the non-doped polysilicon film at an implantation amount of 5.0 × 10 ¹⁵ atoms / cm ² by an ion implantation method to form a polysilicon film 27. It is formed (see FIG. 16B).

(3) The selection gate 13 is formed on the field oxide film 3 and the selection gate oxide film 43 in the selection transistor region from the polysilicon film 27 by the photolithography technique and the etching technique, and on the field oxide film 3 in the memory transistor area. The floating gate 17 is formed on the memory gate oxide film 45 (see FIG. 16C).
Here, before patterning the polysilicon film 27, an HTO film is formed on the entire surface, the HTO film and the polysilicon film 27 are patterned by photolithography and etching techniques, and the HTO film is formed on the selection gate 13 and the floating gate 17. A film pattern may be formed so that BF ₂ is not injected into the selection gate 13 and the floating gate 17 in a BF ₂ injection process in a later process.

(4) BF ₂ is implanted by ion implantation using the selection gate 13, the floating gate 17 and the peripheral circuit gate 25 as a mask to form P-type diffusion layers 5, 7, 9, 19, 21 (FIG. 15). reference.).

In the reference example of FIG. 15, since the impurity concentration of the selection gate 13 is the same as that of the floating gate 17, both the gates 13 and 17 can be formed at the same time, and the selection gate 13, the floating gate 17 and the peripheral circuit gate 25 are respectively formed. The manufacturing process can be reduced as compared with the case of forming in a separate process.

  Further, since the thickness of the select gate oxide film 43 is the same as the thickness of the memory gate oxide film 45, both the gate oxide films 43 and 45 can be formed simultaneously. The number of manufacturing steps can be reduced as compared with the case where 45 and the peripheral circuit gate oxide film 47 are formed in separate steps.

17A and 17B are diagrams showing a reference example, in which FIG. 17A is a plan view of a memory cell, FIG. 17B is a plan view of a peripheral circuit transistor, and FIG. 17C is a cross-sectional view at the position AA ′. FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. 1, 5, 11, and 15 are denoted by the same reference numerals, and detailed description thereof is omitted.

This reference example is different from the reference example described with reference to FIG. 15 in that, for example, boron is introduced as a P-type impurity in the polysilicon of the selection gate 33 and the floating gate 35, and phosphorus is not introduced. It is. The boron concentration of the selection gate 33 and the floating gate 35 is, for example, 7.0 × 10 ^{18 to} 5.0 × 10 ¹⁹ atoms / cm ³ .

In this reference example , the impurity concentration of the floating gate 35 is formed lower than the impurity concentration of the peripheral circuit gate 25 as in the above-described reference example described with reference to FIG. Can be improved. Further, since the impurity concentration of the peripheral circuit gate 25 is higher than that of the floating gate 35, the resistance of the peripheral circuit gate 25 can be sufficiently lowered, and the processing speed of the peripheral circuit transistor can be prevented from being lowered. it can.

Further, similarly to the above-described reference example described with reference to FIG. 11, the memory gate oxide film 45 is formed thinner than the peripheral circuit gate oxide film 47, so that the peripheral circuit gate oxide film 47 is formed. Thus, the memory transistor can be satisfactorily written without causing a snapback breakdown.

FIG. 18 is a process cross-sectional view for explaining an example of the manufacturing method for manufacturing the reference example of FIG. 17 and corresponds to the positions AA ′ and BB ′ of FIG. An example of this manufacturing method will be described with reference to FIGS.

(1) The N well 2, field oxide film 3 (see FIG. 17), and peripheral circuit gate oxide film 47 are formed on the P substrate 1 by the same process as the process (1) described with reference to FIG. Then, the peripheral circuit gate 25 is formed (see FIG. 18A).

(2) Thermal oxidation is performed to form gate oxide films 43 and 45 with a thickness of, for example, 7.5 nm. At this time, a silicon oxide film 51 is formed on the surface of the peripheral circuit gate 25. A non-doped polysilicon film 37 is formed on the entire surface of the P substrate 1 (see FIG. 18B).

(3) The selection gate 33 is formed on the field oxide film 3 and the selection gate oxide film 43 in the selection transistor region from the non-doped polysilicon film 37 by the photolithography technique and the etching technique, and the field oxide film 3 in the memory transistor area. A floating gate 35 is formed on the upper and memory gate oxide films 45 (see FIG. 18C ).

(4) BF ₂ is implanted by ion implantation at an implantation amount of, for example, 3.0 to 5.0 × 10 ¹⁵ atoms / cm ³ using the selection gate 33, the floating gate 35 and the peripheral circuit gate 25 as a mask. P-type diffusion layers 5, 7, 9, 19, and 21 are formed, and boron is implanted into the selection gate 33 and the floating gate 35 (see FIG. 17).

In the reference example of FIG. 17, since the impurity concentration of the selection gate 33 is the same as that of the floating gate 35, both the gates 33 and 35 can be formed at the same time, and the selection gate 33, the floating gate 35 and the peripheral circuit gate 25 are respectively formed. The manufacturing process can be reduced as compared with the case of forming in a separate process.

  Further, since the thickness of the select gate oxide film 43 is the same as the thickness of the memory gate oxide film 45, both the gate oxide films 43 and 45 can be formed simultaneously. The number of manufacturing steps can be reduced as compared with the case where 45 and the peripheral circuit gate oxide film 47 are formed in separate steps.

In the reference example described with reference to FIGS. 11, 13, 15, and 17, the thickness of the selection gate oxide film 43 and the memory gate oxide film 45 is different from the thickness of the peripheral circuit gate oxide film 47. The

19A and 19B are views showing the first embodiment, in which FIG. 19A is a plan view of a memory cell, FIG. 19B is a plan view of a peripheral circuit transistor, and FIG. 19C is a cross-sectional view at the position AA ′; D) is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIGS. 1, 7, and 11 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The difference between this embodiment and the reference example described with reference to FIG. 11 is that the select gate oxide film 53 is formed at the same time as the peripheral circuit gate oxide film 47. The thickness of the select gate oxide film 53 is, for example, The point is 10.0 to 15.0 nm, here 13.5 nm.
Further, the selection gate 39 is formed at the same time as the peripheral circuit gate 25. For example, phosphorus as an N-type impurity is introduced into the selection gate 39 at a higher concentration than the floating gate 17, and the substantial phosphorus concentration is 1. The point of being 0.0 × 10 ²⁰ atoms / cm ³ or more is also different from the reference example of FIG.

In this embodiment, the impurity concentration of the floating gate 17 is formed lower than the impurity concentration of the peripheral circuit gate 25 as in the above-described reference example described with reference to FIG. Can be improved.
Further, similar to the above-described reference example described with reference to FIG. 7, since the impurity concentration of the peripheral circuit gate 25 and the selection gate 39 is higher than that of the floating gate 17, the resistance of the peripheral circuit gate 25 and the selection gate 39 is increased. Of the peripheral circuit transistor and the selection transistor can be prevented from being lowered.
Further, similarly to the above-described reference example described with reference to FIG. 11, the memory gate oxide film 45 is formed thinner than the peripheral circuit gate oxide film 47, so that the peripheral circuit gate oxide film 47 is formed. Thus, the memory transistor can be satisfactorily written without causing a snapback breakdown.

Figure 20 is a process sectional view for explaining an example of a manufacturing method for manufacturing the first embodiment, which corresponds to A-A 'position and B-B' position of Fig. 19. An example of the manufacturing method will be described with reference to FIGS.

(1) The N well 2, the field oxide film 3 (see FIG. 20), and the memory gate oxide film 45 are formed on the P substrate 1 by the same process as the process (1) described with reference to FIG. Then, the floating gate 17 is formed (see FIG. 20A).

(2) Thermal oxidation is performed to form gate oxide films 47 and 53 with a thickness of 13.5 nm, for example. At this time, a silicon oxide film 49 is formed on the surface of the floating gate 17. A non-doped polysilicon film is formed on the entire surface of the P substrate 1, further PSG (not shown) is deposited thereon, and phosphorus is thermally diffused in the non-doped polysilicon film to form a polysilicon film 31 (FIG. 20 (FIG. 20). See B).

(3) After the PSG is removed, the selection gate 39 is formed on the field oxide film 3 and the selection gate oxide film 53 in the selection transistor region from the polysilicon film 31 by photolithography and etching techniques, and the peripheral circuit transistor A peripheral circuit gate 25 is formed on the field oxide film 3 and the peripheral circuit gate oxide film 47 in the region (see FIG. 20C).

(4) BF ₂ is implanted by ion implantation using the selection gate 39, the floating gate 17 and the peripheral circuit gate 25 as a mask to form P-type diffusion layers 5, 7, 9, 19, 21 (FIG. 19). reference.).

In the first embodiment, since the impurity concentration of the selection gate 39 is the same as that of the peripheral circuit gate 25, both the gates 25 and 39 can be formed at the same time, and the selection gate 39, the floating gate 17 and the peripheral circuit gate 25 are respectively formed. The manufacturing process can be reduced as compared with the case of forming in a separate process.

  Further, since the thickness of the selection gate oxide film 53 is the same as that of the peripheral circuit gate oxide film 47, both the gate oxide films 47 and 53 can be formed at the same time. The number of manufacturing steps can be reduced compared to the case where the film 45 and the peripheral circuit gate oxide film 47 are formed in separate steps.

21A and 21B are views showing a second embodiment, in which FIG. 21A is a plan view of a memory cell, FIG. 21B is a plan view of a peripheral circuit transistor, and FIG. 21C is a cross-sectional view at the AA ′ position; D) is a cross-sectional view taken along the line BB ′ in FIG. 1, 5, 7, 11, and 19 are assigned the same reference numerals, and detailed descriptions thereof are omitted.

This embodiment differs from the first embodiment described with reference to FIG. 19 in that, for example, boron is introduced as a P-type impurity in the polysilicon of the floating gate 35, and phosphorus is not introduced. . The boron concentration of the floating gate 35 is, for example, 7.0 × 10 ^{18 to} 5.0 × 10 ¹⁹ atoms / cm ³ .
A silicon oxide film 49 is formed on the surface of the floating gate 35.

In this embodiment, the impurity concentration of the floating gate 35 is formed lower than the impurity concentration of the peripheral circuit gate 25 as in the above-described reference example described with reference to FIG. Can be improved.
Further, similar to the above-described reference example described with reference to FIG. 7, since the impurity concentration of the peripheral circuit gate 25 and the selection gate 39 is higher than that of the floating gate 17, the resistance of the peripheral circuit gate 25 and the selection gate 39 is increased. Of the peripheral circuit transistor and the selection transistor can be prevented from being lowered.
Further, similarly to the above-described reference example described with reference to FIG. 11, the memory gate oxide film 45 is formed thinner than the peripheral circuit gate oxide film 47, so that the peripheral circuit gate oxide film 47 is formed. Thus, the memory transistor can be satisfactorily written without causing a snapback breakdown.

FIG. 22 is a process sectional view for explaining an example of the manufacturing method for manufacturing the second embodiment, and corresponds to the positions AA ′ and BB ′ of FIG. This manufacturing method example will be described with reference to FIGS.

(1) The N well 2, field oxide film 3 (see FIG. 21), gate oxide film 45, and gate oxide film 45 are formed on the P substrate 1 by the same process as the process (1) described with reference to FIG. A floating gate 35 is formed (see FIG. 22A).

(2) Gate oxide films 47 and 53 and a silicon oxide film 49 are formed by a process similar to the process (2) described with reference to FIG. 20B, and a polysilicon film 31 is further formed (FIG. 20). 22 (B).)

(3) A selection gate 39 is formed on the field oxide film 3 and the selection gate oxide film 53 in the selection transistor region by the same process as the process (3) described with reference to FIG. A peripheral circuit gate 25 is formed on the field oxide film 3 and the peripheral circuit gate oxide film 47 in the transistor region (see FIG. 22C).

(4) BF ₂ is implanted by ion implantation, for example, at an implantation amount of 3.0 to 5.0 × 10 ¹⁵ atoms / cm ³ using the selection gate 39, the floating gate 35 and the peripheral circuit gate 25 as a mask. P-type diffusion layers 5, 7, 9, 19, and 21 are formed, and boron is implanted into the floating gate 35 (see FIG. 21).

In the second embodiment, since the impurity concentration of the selection gate 39 is the same as that of the peripheral circuit gate 25, both the gates 25 and 39 can be formed at the same time, and the selection gate 39, the floating gate 17 and the peripheral circuit gate 25 are respectively formed. The manufacturing process can be reduced as compared with the case of forming in a separate process.

  Further, since the thickness of the selection gate oxide film 53 is the same as that of the peripheral circuit gate oxide film 47, both the gate oxide films 47 and 53 can be formed at the same time. The number of manufacturing steps can be reduced compared to the case where the film 45 and the peripheral circuit gate oxide film 47 are formed in separate steps.

23A and 23B are views showing a third embodiment, wherein FIG. 23A is a plan view of a memory cell, FIG. 23B is a plan view of a peripheral circuit transistor, and FIG. 23C is a cross-sectional view at the AA ′ position; D) is a cross-sectional view taken along the line BB ′ in FIG. 1, 7, 11, 15, and 19 are assigned the same reference numerals, and detailed descriptions thereof are omitted.

This embodiment differs from the first embodiment described with reference to FIG. 19 in that the silicon oxide film 49 (see FIG. 19) is not formed on the surface of the floating gate 17, and the peripheral circuit gate 25 and The silicon oxide film 51 is formed on the surface of the selection gate 39.

In this embodiment, the impurity concentration of the floating gate 17 is formed lower than the impurity concentration of the peripheral circuit gate 25 as in the above-described reference example described with reference to FIG. Can be improved.
Further, similar to the above-described reference example described with reference to FIG. 7, since the impurity concentration of the peripheral circuit gate 25 and the selection gate 39 is higher than that of the floating gate 17, the resistance of the peripheral circuit gate 25 and the selection gate 39 is increased. Of the peripheral circuit transistor and the selection transistor can be prevented from being lowered.
Further, similarly to the above-described reference example described with reference to FIG. 11, the memory gate oxide film 45 is formed thinner than the peripheral circuit gate oxide film 47, so that the peripheral circuit gate oxide film 47 is formed. Thus, the memory transistor can be satisfactorily written without causing a snapback breakdown.

FIG. 24 is a process cross-sectional view for explaining an example of the manufacturing method for manufacturing the third embodiment, and corresponds to the positions AA ′ and BB ′ in FIG. An example of this manufacturing method will be described with reference to FIGS.

(1) An N well 2, a field oxide film 3 (see FIG. 23), a peripheral circuit gate oxide film on the P substrate 1 by a process similar to the process (1) described with reference to FIG. 47, a selection gate oxide film 53, a peripheral circuit gate 25, and a selection gate 39 are formed (see FIG. 24A).

(2) The memory gate oxide film 45 and the silicon oxide film 51 are formed by the same process as the process (2) described with reference to FIG. 16B, and the polysilicon film 27 is further formed (FIG. 24). (See (B).)

(3) The floating gate 17 is formed on the field oxide film 3 and the memory gate oxide film 45 in the memory transistor region by the same process as the above process (3) described with reference to FIG. 24 (C).)

(4) BF ₂ is implanted by ion implantation using the selection gate 39, the floating gate 17 and the peripheral circuit gate 25 as a mask to form P-type diffusion layers 5, 7, 9, 19, 21 (FIG. 23). reference.).

In the third embodiment, since the impurity concentration of the selection gate 39 is the same as that of the peripheral circuit gate 25, both the gates 25 and 39 can be formed at the same time, and the selection gate 39, the floating gate 17 and the peripheral circuit gate 25 are respectively formed. The manufacturing process can be reduced as compared with the case of forming in a separate process.

  Further, since the thickness of the selection gate oxide film 53 is the same as that of the peripheral circuit gate oxide film 47, both the gate oxide films 47 and 53 can be formed at the same time. The number of manufacturing steps can be reduced compared to the case where the film 45 and the peripheral circuit gate oxide film 47 are formed in separate steps.

25A and 25B are diagrams showing a fourth embodiment, in which FIG. 25A is a plan view of a memory cell, FIG. 25B is a plan view of a peripheral circuit transistor, and FIG. D) is a cross-sectional view taken along the line BB ′ in FIG. 1, 5, 7, 11, 15, and 19 are assigned the same reference numerals, and detailed descriptions thereof are omitted.

This embodiment differs from the third embodiment described with reference to FIG. 23 in that, for example, boron is introduced as a P-type impurity in the polysilicon of the floating gate 35, and phosphorus is not introduced. . The boron concentration of the floating gate 35 is, for example, 7.0 × 10 ^{18 to} 5.0 × 10 ¹⁹ atoms / cm ³ .

In this embodiment, the impurity concentration of the floating gate 35 is formed lower than the impurity concentration of the peripheral circuit gate 25 as in the above-described reference example described with reference to FIG. Can be improved.
Further, similar to the above-described reference example described with reference to FIG. 7, since the impurity concentration of the peripheral circuit gate 25 and the selection gate 39 is higher than that of the floating gate 17, the resistance of the peripheral circuit gate 25 and the selection gate 39 is increased. Of the peripheral circuit transistor and the selection transistor can be prevented from being lowered.
Further, similarly to the above-described reference example described with reference to FIG. 11, the memory gate oxide film 45 is formed thinner than the peripheral circuit gate oxide film 47, so that the peripheral circuit gate oxide film 47 is formed. Thus, the memory transistor can be satisfactorily written without causing a snapback breakdown.

FIG. 26 is a process sectional view for explaining an example of the manufacturing method for manufacturing the fourth embodiment, and corresponds to the positions AA ′ and BB ′ in FIG. 25. An example of this manufacturing method will be described with reference to FIGS.

(1) N well 2, field oxide film 3 (see FIG. 25), peripheral circuit gate oxide film on P substrate 1 by the same process as the above process (1) described with reference to FIG. 47, the selection gate oxide film 53, the peripheral circuit gate 25 and the selection gate 39 are formed (see FIG. 26A).

(2) A thermal oxidation process is performed to form a memory gate oxide film 45 with a thickness of, for example, 7.5 nm. At this time, the silicon oxide film 51 is formed on the surface of the peripheral circuit gate 25 and the surface of the selection gate 39. A non-doped polysilicon film 37 is formed on the entire surface of the P substrate 1 (see FIG. 26B).

(3) The floating gate 35 is formed on the field oxide film 3 and the memory gate oxide film 45 in the memory transistor region from the non-doped polysilicon film 37 by photolithography and etching techniques (see FIG. 26C). .

(4) BF ₂ is implanted by ion implantation, for example, at an implantation amount of 3.0 to 5.0 × 10 ¹⁵ atoms / cm ³ using the selection gate 39, the floating gate 35 and the peripheral circuit gate 25 as a mask. P-type diffusion layers 5, 7, 9, 19, and 21 are formed, and boron is implanted into the floating gate 35 (see FIG. 25).

In the fourth embodiment, since the impurity concentration of the selection gate 39 is the same as that of the peripheral circuit gate 25, both the gates 25 and 39 can be formed at the same time, and the selection gate 39, the floating gate 35 and the peripheral circuit gate 25 are respectively formed. The manufacturing process can be reduced as compared with the case of forming in a separate process.

  Further, since the thickness of the selection gate oxide film 53 is the same as that of the peripheral circuit gate oxide film 47, both the gate oxide films 47 and 53 can be formed at the same time. The number of manufacturing steps can be reduced compared to the case where the film 45 and the peripheral circuit gate oxide film 47 are formed in separate steps.

27A and 27B are diagrams showing a reference example, in which FIG. 27A is a plan view of a memory cell, FIG. 27B is a plan view of a peripheral circuit transistor, and FIG. FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

An N well 2 is formed in a predetermined region of the P substrate 1, and a field oxide film 3 is formed on the surface of the P substrate 1.
A selection transistor including P-type diffusion layers 5 and 7, a selection gate oxide film 55 and a selection gate 13 is formed in the selection transistor region.
A memory transistor including P-type diffusion layers 7 and 9, a memory gate oxide film 57 and a floating gate 17 is formed in the memory transistor region.
A peripheral circuit transistor including P-type diffusion layers 19 and 21, a peripheral circuit gate oxide film 59 and a peripheral circuit gate 25 is formed in the peripheral circuit transistor region.

  The selection gate oxide film 55 and the memory gate oxide film 57 are formed by one oxidation process in the same process. The peripheral circuit gate oxide film 59 is formed by two oxidation processes. The thicknesses of the select gate oxide film 55 and the memory gate oxide film 57 are, for example, 6.0 to 10.0 nm, and 7.5 nm here. The thickness of the peripheral circuit gate oxide film 59 is, for example, 10.0 to 15.0 nm, here 13.5 nm.

In this reference example , the same effect as that of the above-described reference example described with reference to FIG. 1 can be obtained.
Further, since the thickness of the memory gate oxide film 57 is smaller than that of the peripheral circuit gate oxide film 59, the peripheral circuit gate oxide film is not damaged to the extent that the peripheral circuit gate oxide film 59 is damaged when writing to the memory transistor. By increasing the thickness, the memory gate oxide film thickness can be reduced to such an extent that good write characteristics of the memory transistor can be obtained. As a result, it is possible to perform good writing of the memory transistor while preventing damage to the peripheral circuit gate oxide film 59 and without causing snapback destruction.

28 is a process cross-sectional view for explaining an example of the manufacturing method for manufacturing the reference example of FIG. 27, and corresponds to the positions AA ′ and BB ′ of FIG. This manufacturing method example will be described with reference to FIGS.

(1) After the N well 2 is formed on the P substrate 1, a field oxide film 3 (see FIG. 27) is formed on the P substrate 1 by a normal LOCOS method to perform element isolation. A sacrificial oxide film 61 having a thickness of, for example, 6 to 16 nm is formed on the surface of the active region defined by the field oxide film 3, and channel dope implantation is performed (see FIG. 28A).

(2) A resist pattern 63 is formed to cover the peripheral circuit transistor formation region and have openings in the selection transistor region and the memory transistor formation region. The sacrificial oxide film 61 in the selection transistor region and the memory transistor region is selectively removed using the resist pattern 63 as a mask (see FIG. 28B).

(3) After removing the resist pattern 63, a thermal oxidation process is performed to form a selection gate oxide film 55 and a memory gate oxide film 57 having a film thickness of, for example, 7.5 nm on the surface of the N well 2 in the selection transistor area and the memory transistor area. Form. At this time, the thickness of the sacrificial oxide film 61 in the peripheral circuit transistor region grows to become the peripheral circuit gate oxide film 59 (see FIG. 28C).

(4) On the field oxide film 3 and the select gate oxide film 55 in the select transistor region by the same process as the above processes (1) to (3) described with reference to FIGS. 4 (A) to (C). The selection gate 13 is formed, the floating gate 17 is formed on the field oxide film 3 and the memory gate oxide film 57 in the memory transistor region, and on the field oxide film 3 and the peripheral circuit gate oxide film 59 in the peripheral circuit transistor region. Peripheral circuit gate 25 is formed. P-type diffusion layers 5, 7, 9, 19, and 21 are formed by the same process (4) described with reference to FIG. 1 (see FIG. 27).

29A and 29B are diagrams showing a reference example, in which FIG. 29A is a plan view of a memory cell, FIG. 29B is a plan view of a peripheral circuit transistor, FIG. 29C is a cross-sectional view at the position AA ′, FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIGS. 1, 5 and 27 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This reference example is different from the reference example described with reference to FIG. 27 in that, for example, boron is introduced as a P-type impurity in the polysilicon of the selection gate 33 and the floating gate 35, and phosphorus is not introduced. It is. The boron concentration of the selection gate 33 and the floating gate 35 is, for example, 7.0 × 10 ^{18 to} 5.0 × 10 ¹⁹ atoms / cm ³ .

In this reference example , after the steps (1) to (3) described with reference to FIG. 28, the same steps as the steps (1) to (4) described with reference to FIGS. 5 and 6 are performed. It can be formed by performing.

In this reference example, it is possible to obtain the same effects as those of the reference example described with reference to FIG.
Further, since the thickness of the memory gate oxide film 57 is smaller than that of the peripheral circuit gate oxide film 59, the peripheral circuit gate oxide film 59 is prevented from being damaged and without causing a snapback breakdown. Good writing of the memory transistor can be performed.

30A and 30B are diagrams showing a reference example , where FIG. 30A is a plan view of a memory cell, FIG. 30B is a plan view of a peripheral circuit transistor, and FIG. 30C is a cross-sectional view at the position AA ′. FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIGS. 1, 7 and 27 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This reference example is different from the reference example described with reference to FIG. 27 in that the selection gate 39 is formed at the same time as the peripheral circuit gate 25, and phosphorus, for example, as an N-type impurity is added to the selection gate 39. It is introduced at a higher concentration, and the substantial phosphorus concentration is 1.0 × 10 ²⁰ atoms / cm ³ or more.

In this reference example , after the steps (1) to (3) described with reference to FIG. 28, the same steps as the steps (1) to (4) described with reference to FIGS. 7 and 8 are performed. It can be formed by performing.

In this reference example , the same effect as that of the above-described reference example described with reference to FIG. 7 can be obtained.
Further, since the thickness of the memory gate oxide film 57 is smaller than that of the peripheral circuit gate oxide film 59, the peripheral circuit gate oxide film 59 is prevented from being damaged and without causing a snapback breakdown. Good writing of the memory transistor can be performed.

31A and 31B are diagrams showing a reference example, in which FIG. 31A is a plan view of a memory cell, FIG. 31B is a plan view of a peripheral circuit transistor, and FIG. 31C is a cross-sectional view at the position AA ′ FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG. 1, 5, 7, 9, and 27 are assigned the same reference numerals, and detailed descriptions thereof are omitted.

This reference example is different from the reference example described with reference to FIG. 30 in that, for example, boron is introduced as a P-type impurity in the polysilicon of the floating gate 35, and phosphorus is not introduced. The boron concentration of the floating gate 35 is, for example, 7.0 × 10 ^{18 to} 5.0 × 10 ¹⁹ atoms / cm ³ .

In this reference example , after the steps (1) to (3) described with reference to FIG. 28, the same steps as the steps (1) to (4) described with reference to FIGS. 9 and 10 are performed. It can be formed by performing.

In this reference example , the same effect as that of the above-described reference example described with reference to FIG. 9 can be obtained.
Further, since the thickness of the memory gate oxide film 57 is smaller than that of the peripheral circuit gate oxide film 59, the peripheral circuit gate oxide film 59 is prevented from being damaged and without causing a snapback breakdown. Good writing of the memory transistor can be performed.

Further, the reference example described with reference to FIG. 27, the reference example described with reference to FIG. 29, the reference example described with reference to FIG. 30, in the reference example described with reference to FIG. 31 Since the film thickness of the select gate oxide film 55 is the same as the film thickness of the memory gate oxide film 57, both the gate oxide films 55 and 57 can be formed simultaneously. In addition, the number of manufacturing steps can be reduced compared to the case where the peripheral circuit gate oxide film 59 is formed in separate steps.

32A and 32B are views showing a fifth embodiment, wherein FIG. 32A is a plan view of a memory cell, FIG. 32B is a plan view of a peripheral circuit transistor, and FIG. 32C is a cross-sectional view at the AA ′ position; D) is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIGS. 1 and 27 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The difference between this embodiment and the reference example described with reference to FIG. 27 is that the selection gate oxide film 65 is formed at the same time as the peripheral circuit gate oxide film 59 by two oxidation processes. The film thickness 65 is, for example, 10.0 to 15.0 nm, here 13.5 nm.

In this embodiment, the same effect as that of the above-described reference example described with reference to FIG. 1 can be obtained.
Further, since the thickness of the memory gate oxide film 57 is smaller than that of the peripheral circuit gate oxide film 59, the peripheral circuit gate oxide film 59 is prevented from being damaged and without causing a snapback breakdown. Good writing of the memory transistor can be performed.

FIG. 33 is a process cross-sectional view for explaining an example of the manufacturing method for manufacturing the fifth embodiment, and corresponds to the positions AA ′ and BB ′ in FIG. 32. An example of the manufacturing method will be described with reference to FIGS.

(1) N well 2, field oxide film 3 (see FIG. 32), and sacrificial oxide film 61 are formed on P substrate 1 by the same process as the above process (1) described with reference to FIG. Then, channel dope implantation is performed (see FIG. 33A).

(2) A resist pattern 67 is formed which covers the selection transistor region and the peripheral circuit transistor formation region and has an opening in the memory transistor formation region. The sacrificial oxide film 61 in the memory transistor region is selectively removed using the resist pattern 67 as a mask (see FIG. 33B).

(3) After removing the resist pattern 67, a thermal oxidation process is performed to form a memory gate oxide film 57 having a thickness of, for example, 7.5 nm on the surface of the N well 2 in the memory transistor region. At this time, the sacrificial oxide film 61 in the select transistor region and the peripheral circuit transistor region is grown to a thickness of, for example, 12 to 20 nm to become the select gate oxide film 65 and the peripheral circuit gate oxide film 59. (See (C).)

(4) On the field oxide film 3 and the select gate oxide film 65 in the select transistor region by the same steps as the above steps (1) to (3) described with reference to FIGS. The selection gate 13 is formed, the floating gate 17 is formed on the field oxide film 3 and the memory gate oxide film 57 in the memory transistor region, and on the field oxide film 3 and the peripheral circuit gate oxide film 59 in the peripheral circuit transistor region. Peripheral circuit gate 25 is formed. P-type diffusion layers 5, 7, 9, 19, and 21 are formed by the same process (4) described with reference to FIG. 1 (see FIG. 27).

34A and 34B are views showing a sixth embodiment, in which FIG. 34A is a plan view of a memory cell, FIG. 34B is a plan view of a peripheral circuit transistor, and FIG. D) is a cross-sectional view taken along the line BB ′ in FIG. 1, 5, 27, and 32 are denoted by the same reference numerals, and detailed description thereof is omitted.

This embodiment differs from the fifth embodiment described with reference to FIG. 32 in that, for example, boron is introduced as a P-type impurity in the polysilicon of the selection gate 33 and the floating gate 35, and phosphorus is not introduced. There is no point. The boron concentration of the selection gate 33 and the floating gate 35 is, for example, 7.0 × 10 ^{18 to} 5.0 × 10 ¹⁹ atoms / cm ³ .

  In this embodiment, after the steps (1) to (3) described with reference to FIG. 33, the same steps as the steps (1) to (4) described with reference to FIGS. 5 and 6 are performed. It can be formed by performing.

In this embodiment, it is possible to obtain the same effect as that of the reference example described with reference to FIG.
Further, since the thickness of the memory gate oxide film 57 is smaller than that of the peripheral circuit gate oxide film 59, the peripheral circuit gate oxide film 59 is prevented from being damaged and without causing a snapback breakdown. Good writing of the memory transistor can be performed.

FIG. 35 is a diagram showing a seventh embodiment, in which (A) is a plan view of a memory cell, (B) is a plan view of a peripheral circuit transistor, and (C) is a cross-sectional view at the position AA ′; D) is a cross-sectional view taken along the line BB ′ in FIG. The same parts as those in FIGS. 1, 7, 27 and 32 are denoted by the same reference numerals, and detailed description thereof will be omitted.

This embodiment differs from the fifth embodiment described with reference to FIG. 32 in that the selection gate 39 is formed at the same time as the peripheral circuit gate 25, and phosphorus, for example, as an N-type impurity floats on the selection gate 39. It is introduced at a higher concentration than the gate 17, and the substantial phosphorus concentration is 1.0 × 10 ²⁰ atoms / cm ³ or more.

  In this embodiment, after the steps (1) to (3) described with reference to FIG. 33, the same steps as the steps (1) to (4) described with reference to FIGS. It can be formed by performing.

In this embodiment, the same effect as that of the above-described reference example described with reference to FIG. 7 can be obtained.
Further, since the thickness of the memory gate oxide film 57 is smaller than that of the peripheral circuit gate oxide film 59, the peripheral circuit gate oxide film 59 is prevented from being damaged and without causing a snapback breakdown. Good writing of the memory transistor can be performed.

36A and 36B are views showing an eighth embodiment, in which FIG. 36A is a plan view of a memory cell, FIG. 36B is a plan view of a peripheral circuit transistor, and FIG. 36C is a cross-sectional view at the position AA ′; D) is a cross-sectional view taken along the line BB ′ in FIG. 1, 5, 7, 9, 27, and 32 are assigned the same reference numerals, and detailed descriptions thereof are omitted.

This embodiment differs from the seventh embodiment described with reference to FIG. 35 in that, for example, boron is introduced into the polysilicon of the floating gate 35 as a P-type impurity, and phosphorus is not introduced. . The boron concentration of the floating gate 35 is, for example, 7.0 × 10 ^{18 to} 5.0 × 10 ¹⁹ atoms / cm ³ .

  In this embodiment, after the steps (1) to (3) described with reference to FIG. 33, the same steps as the steps (1) to (4) described with reference to FIGS. 9 and 10 are performed. It can be formed by performing.

In this embodiment, it is possible to obtain the same effect as the above-described reference example described with reference to FIG.
Further, since the thickness of the memory gate oxide film 57 is smaller than that of the peripheral circuit gate oxide film 59, the peripheral circuit gate oxide film 59 is prevented from being damaged and without causing a snapback breakdown. Good writing of the memory transistor can be performed.

Further, referring to FIG. 36, the fifth embodiment described with reference to FIG. 32, the sixth embodiment described with reference to FIG. 34, the seventh embodiment described with reference to FIG. In the above-described eighth embodiment, since the thickness of the selection gate oxide film 65 is the same as the thickness of the peripheral circuit gate oxide film 59, both gate oxide films 59 and 65 can be formed at the same time. The number of manufacturing steps can be reduced as compared with the case where the oxide film 65, the memory gate oxide film 57, and the peripheral circuit gate oxide film 59 are formed in separate processes.

In the above-described embodiment and reference example , the memory transistor and the selection transistor are PMOS transistors (write voltage 6 to 7V), and therefore, for writing, compared with the case where a memory transistor (write voltage 10V or so) composed of an NMOS transistor is used. Therefore, it is not necessary to use a so-called control gate, and the write voltage can be lowered.
However, the memory transistor and the selection transistor may be NMOS transistors.

In the drawings for explaining the above-described embodiments and reference examples , only a PMOS transistor is shown as a peripheral circuit transistor, but an NMOS transistor as a peripheral circuit transistor may be formed in a region not shown.
The semiconductor substrate may be an N substrate.
In addition, a silicide film for reducing gate resistance may be formed on any or all of the selection gate, the memory gate, and the peripheral circuit gate.

FIG. 37 is a circuit diagram showing an embodiment provided with a divided resistor circuit and a constant voltage generating circuit.
A constant voltage generation circuit 90 is provided to stably supply power from the DC power supply 71. The constant voltage generation circuit 90 includes an input terminal (Vbat) 73 to which a DC power supply 71 is connected, a reference voltage generation circuit (Vref) 75, an operational amplifier 77, a PMOS transistor 79 constituting an output driver, division resistors 81 and 83, and an output. A terminal (Vout) 85 is provided.

The dividing resistor 83 is constituted by R0. The dividing resistor 81 includes a plurality of resistance value adjusting resistance elements R1, R2, ... Ri-1, Ri connected in series. Resistance adjusting resistor elements R1, R2, ... Ri-1 , corresponding to the Ri MOS transistors SW1 fuse, SW2, is ... SWi-1, SWi are connected in parallel.

Fuse MOS transistors SW1, SW2, ... SWi-1, SWi are provided with a read circuit 87 and a non-volatile memory cell 89 for switching on and off. The output of the readout circuit 87 is connected to the gates of the corresponding fuse MOS transistors SW1, SW2, ... SWi-1, SWi. A plurality of memory cells are arranged in the nonvolatile memory cell 89, and information for turning on or off the fuse MOS transistors SW1, SW2, ... SWi-1, SWi is stored. The read circuit 87 turns on or off the fuse MOS transistors SW1, SW2, ... SWi-1, SWi in accordance with the storage state of the nonvolatile memory cell 89.

  In the operational amplifier 77 of the constant voltage generation circuit 90, the output terminal is connected to the gate electrode of the PMOS 79, the reference voltage Vref is applied from the reference voltage generation circuit 75 to the inverting input terminal, and the output voltage Vout is divided to the non-inverting input terminal. A voltage divided by 81 and 83 is applied, and the divided voltage of the dividing resistors 81 and 83 is controlled to be equal to the reference voltage Vref.

FIG. 38 is a circuit diagram showing an embodiment provided with a divided resistance circuit and a voltage detection circuit. The same parts as those in FIG.
In the voltage detection circuit 91, the dividing resistors 81 and 83 and the oscillation preventing resistance element RH are connected in series between the input terminal 93 to which the voltage of the terminal to be measured (input voltage Vsens) is input and the ground potential. . The configuration of the dividing resistors 81 and 83 is the same as that in FIG.

Resistance adjusting resistor elements R1, R2, ... Ri-1 , corresponding to the Ri MOS transistors SW1 fuse, SW2, is ... SWi-1, SWi are connected in parallel. A readout circuit 87 is connected to the fuse MOS transistors SW1, SW2, ... SWi-1, SWi. A nonvolatile memory cell 89 is connected to the read circuit 87.

  An oscillation preventing resistance element RH is provided between the dividing resistor 83 and the ground. An N-channel oscillation prevention fuse MOS transistor SWH is connected in parallel with the oscillation prevention resistance element RH. The gate of the oscillation preventing fuse MOS transistor SWH is connected to the output of the operational amplifier 77.

  The inverting input terminal of the operational amplifier 77 is connected to the connection point between the dividing resistors 81 and 83. A reference voltage generation circuit 75 is connected to the non-inverting input terminal of the operational amplifier 77, and the reference voltage Vref is applied. The output of the operational amplifier 77 is output to the outside through an inverter 95 and an output terminal (DTout) 97.

In the voltage detection circuit 91, in the high voltage detection state, the oscillation preventing resistance element RH is in the off state, the voltage of the terminal to be measured input from the input terminal 93 is high, and the dividing resistor 81, the dividing resistor 83, and the oscillation preventing resistor When the voltage divided by the resistance element RH is higher than the reference voltage Vref, the output of the operational amplifier 77 maintains the logical value 0, and the output is inverted by the inverter 95 to the logical value 1 and output from the output terminal 97. The At this time, the divided voltage input to the inverting input terminal of the operational amplifier 77 is
{(R0) + (RH)} / {(R1) + (R2) ... + (Ri-1) + (Ri) + (R0) + (RH)} × (Vsens)
It is.

  When the voltage of the terminal to be measured drops and the voltage divided by the dividing resistor 81, the dividing resistor 83, and the oscillation preventing resistance element RH becomes equal to or lower than the reference voltage Vref, the output of the operational amplifier 77 becomes the logical value 1, and the output Is inverted by an inverter 95 to have a logical value of 0 and output from an output terminal 97.

  When the output of the operational amplifier 77 becomes a logical value 1, the oscillation preventing fuse MOS transistor SWH is turned on, the dividing resistor 83 is connected to the ground potential via the oscillation preventing fuse MOS transistor SWH, and the dividing resistor 81 And the voltage between 83 decreases. As a result, the output of the operational amplifier 77 maintains the logical value 1, and the voltage detection circuit 91 enters the low voltage detection state. As described above, the oscillation preventing resistance element RH and the oscillation preventing fuse MOS transistor SWH prevent oscillation of the output of the voltage detection circuit 91 when the input voltage Vsens decreases.

The divided voltage input to the inverting input terminal of the operational amplifier 77 in the low voltage detection state of the voltage detection circuit 91 is:
(R0) / {(R1) + (R2) ... + (Ri-1) + (Ri) + (R0)} × (Vsens)
It is. The release voltage for setting the voltage detection circuit 91 to the high voltage detection state is the input voltage Vsens at which the divided voltage input to the inverting input terminal of the operational amplifier 77 in the low voltage detection state is larger than the reference voltage Vref.

In the embodiment shown in FIGS. 37 and 38, the MOS transistors constituting the readout circuit 87, the reference voltage generation circuit 75 and the operational amplifier 77, and the fuse MOS transistors SW1, SW2, ... SWi-1, SWi and oscillation prevention. As the fuse MOS transistor SWH, a peripheral circuit transistor constituting the semiconductor device of the present invention is used. However, it is not necessary that the peripheral circuit transistors constituting the semiconductor device of the present invention are used for all the MOS transistors.

In the embodiment shown in FIGS. 37 and 38, the fuse MOS transistors SW1, SW2, ... SWi-1, SWi are selected on and off by the control of the read circuit 87 and the nonvolatile memory cell 89, and the dividing resistor is selected. The resistance value of 81 can be adjusted. Thereby, the set voltage can be adjusted for the output voltage of the constant voltage generation circuit 90 and the output voltage of the voltage detection circuit 91.

In the conventional constant voltage generation circuit and voltage detection circuit, instead of the fuse MOS transistors SW1, SW2, ... SWi-1, SWi, the readout circuit 87 and the nonvolatile memory cell 89, resistance value adjusting resistance elements R1, R2, A fuse made of polysilicon or a metal material is connected in parallel for each of Ri-1 and Ri, and the resistance value of the dividing resistor is adjusted by cutting the fuse.

In the embodiment shown in FIGS. 37 and 38, the switches (the fuse MOS transistors SW1, SW2, ... SWi-1) that are once turned off, which is difficult with a fuse, are controlled by the read circuit 87 and the nonvolatile memory cell 89. , SWi) can be turned on again, so that the set voltage can be freely changed for the output voltage of the constant voltage generation circuit 90 and the output voltage of the voltage detection circuit 91.

Further, since the fuse MOS transistors SW1, SW2, ... SWi-1, SWi can be switched on or off by writing to the nonvolatile memory cell 89, the constant voltage is maintained even after the semiconductor device is accommodated in the package. The set voltage can be adjusted and changed for the output voltage of the generation circuit 90 and the output voltage of the voltage detection circuit 91.

  In FIG. 37 and FIG. 38, the divided resistor circuit of the present invention is applied to the constant voltage generating circuit and the voltage detecting circuit. However, the present invention is not limited to this, and the divided resistor circuit of the present invention is not limited to this. It can also be applied to circuits.

  Although the embodiments of the present invention have been described above, the numerical values, shapes, materials, arrangements, and the like are examples, and the present invention is not limited to these, and is within the scope of the present invention described in the claims. Various changes can be made.

It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. It is a figure which shows the result of having investigated the electric charge retention characteristic of the memory transistor, a vertical axis | shaft shows the threshold voltage of a memory transistor, and a horizontal axis shows elapsed time. FIG. 2 is a circuit diagram showing an example when the memory cells of the reference example of FIG. 1 are arranged in a matrix. It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the reference example of FIG. It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the reference example of FIG. It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the reference example of FIG. It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the reference example of FIG. It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the reference example of FIG. It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the reference example of FIG. It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the reference example of FIG. It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing the reference example of FIG. Is a view showing the first embodiment, (A) is a plan view of a memory cell, (B) a plan view of the peripheral circuit transistor, cross-sectional view at A-A 'position of (C), the (D) is ( It is sectional drawing in the BB 'position of B). It is a process sectional view for explaining an example of a manufacturing method for manufacturing the first embodiment. It is a figure which shows 2nd Example, (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is ( It is sectional drawing in the BB 'position of B). It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing 2nd Example. It is a figure which shows 3rd Example, (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) Sectional drawing in the AA 'position, (D) is ( It is sectional drawing in the BB 'position of B). It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing 3rd Example. It is a figure which shows 4th Example, (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is ( It is sectional drawing in the BB 'position of B). It is process sectional drawing for demonstrating an example of the manufacturing method for manufacturing 4th Example. It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. It is process sectional drawing for demonstrating a part of example of the manufacturing method for manufacturing the reference example of FIG. It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. It is a figure which shows a reference example , (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is (B) It is sectional drawing in a BB 'position. Is a diagram showing a fifth embodiment, (A) is a plan view of a memory cell, (B) a plan view of the peripheral circuit transistor, cross-sectional view at A-A 'position of (C), the (D) is ( It is sectional drawing in the BB 'position of B). It is process sectional drawing for demonstrating a part of example of the manufacturing method for manufacturing 5th Example. FIG. 10 is a diagram illustrating a sixth embodiment, where (A) is a plan view of a memory cell, (B) is a plan view of a peripheral circuit transistor, (C) is a cross-sectional view at the AA ′ position, and (D) is ( It is sectional drawing in the BB 'position of B). It is a figure which shows 7th Example, (A) is a top view of a memory cell, (B) is a top view of a peripheral circuit transistor, (C) is sectional drawing in the AA 'position, (D) is ( It is sectional drawing in the BB 'position of B). FIG. 10 is a diagram illustrating an eighth embodiment, where (A) is a plan view of a memory cell, (B) is a plan view of a peripheral circuit transistor, (C) is a cross-sectional view at position AA ′, and (D) is ( It is sectional drawing in the BB 'position of B). It is a circuit diagram which shows one Example provided with the division resistance circuit and the constant voltage generation circuit. It is a circuit diagram which shows one Example provided with the division resistance circuit and the voltage detection circuit. It is a top view which shows the 1 layer gate type non-volatile memory as a prior art example. It is sectional drawing which shows the two-layer gate type non-volatile memory as a prior art example. It is a figure which shows the non-volatile memory which is not provided with the control gate, (A) is a top view, (B) is sectional drawing in the E-E 'position of (A).

Explanation of symbols

1 P substrate (semiconductor substrate)
2 N well 3 Field oxide film 5, 7, 9, 19, 21 N-type diffusion layer 11, 43 Select gate oxide film 13, 33, 39, 53, 55, 65 Select gate 15, 45, 57 Memory gate oxide film 17 , 35 Floating gates 23, 47, 59 Peripheral circuit gate oxide film 25 Peripheral circuit gates 49, 51 Silicon oxide film

Claims (7)

A memory transistor made of a MOS transistor having a memory gate oxide film formed on a semiconductor substrate and a floating gate made of electrically floating polysilicon formed on the memory gate oxide film;
Has a selection gate made of polysilicon is formed on the selection gate oxide film on said selection gate oxide film formed on a semiconductor substrate, a selection transistor composed of the MOS transistors connected in series with the memory transistor, the A non-volatile memory cell comprising:
A peripheral circuit transistor comprising a MOS transistor having a peripheral circuit gate oxide film formed on the semiconductor substrate and a peripheral circuit gate made of polysilicon formed on the peripheral circuit gate oxide film;
The film thickness of the memory gate oxide film is formed thinner than the film thickness of the peripheral circuit gate oxide film,
The thickness of the selection gate oxide film is the same as the thickness of the peripheral circuit gate oxide film,
The semiconductor device according to claim 1, wherein an impurity concentration in the polysilicon of the floating gate is lower than an impurity concentration in the polysilicon of the peripheral circuit gate.   2. The semiconductor device according to claim 1, wherein an impurity concentration in the polysilicon of the selection gate is the same as an impurity concentration in the polysilicon of the floating gate.   2. The semiconductor device according to claim 1, wherein the impurity concentration in the polysilicon of the selection gate is the same as the impurity concentration in the polysilicon of the peripheral circuit gate. The semiconductor device according to any one of the memory transistors and the selection transistors claim 1 is a PMOS transistor 3. In a semiconductor device having a divided resistor circuit capable of obtaining a voltage output by dividing by two or more resistor elements and adjusting the voltage output by cutting a fuse element,
The divided resistor circuit includes a plurality of resistance value adjusting resistance elements connected in series, and a plurality of fuse MOS transistors connected in parallel corresponding to the resistance value adjusting resistance elements as the fuse elements, Item 5: The nonvolatile memory cell according to any one of Items 1 to 4, the peripheral circuit transistor, and a read circuit for switching on and off the fuse MOS transistor according to a storage state of the nonvolatile memory cell. ,
A semiconductor device, wherein the fuse MOS transistor, the MOS transistor constituting the readout circuit, or both are constituted by the peripheral circuit transistor. A divided resistor circuit for dividing the input voltage to supply a divided voltage, a reference voltage generating circuit for supplying a reference voltage, a divided voltage from the divided resistor circuit, and a reference voltage from the reference voltage generating circuit In a semiconductor device including a voltage detection circuit having a comparison circuit for comparison,
6. A semiconductor device comprising the divided resistor circuit according to claim 5 as the divided resistor circuit. An output driver for controlling the output of the input voltage, a divided resistor circuit for dividing the output voltage and supplying a divided voltage, a reference voltage generating circuit for supplying a reference voltage, and a divided voltage from the divided resistor circuit In a semiconductor device including a constant voltage generation circuit having a comparison circuit for comparing the reference voltage from the reference voltage generation circuit and controlling the operation of the output driver according to the comparison result,
6. A semiconductor device comprising the divided resistor circuit according to claim 5 as the divided resistor circuit.

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