JP5003649B2 - Direct AC power converter and control method thereof - Google Patents

Description

  The present invention relates to a technique for performing so-called zero current commutation in a so-called direct AC power converter.

  As a main circuit configuration of the inverter, an indirect AC power converter is generally used. In an indirect AC power converter, commercial AC is converted to DC by a rectifier circuit, and further, power is supplied to the voltage source converter via a smoothing circuit, and an AC output is obtained from the voltage source converter.

  On the other hand, a direct AC power converter that performs AC-AC conversion without using a smoothing circuit, such as a matrix converter, is also known. The matrix converter performs AC-AC conversion by using commutation in the switching element group.

  However, as introduced in Patent Documents 1 and 2 below, the matrix converter is connected to a virtual AC-DC converter, a virtual DC-AC converter, and a virtual DC-AC converter via a DC link without a smoothing circuit. The commutation of the switching element group can be controlled based on the operation of the configuration in which is connected.

  In addition, as introduced in Non-Patent Document 1, a configuration in which an AC-DC converter and a DC-AC converter are coupled via a DC link without a smoothing circuit is also an aspect of a matrix converter. Proposed.

  Therefore, a circuit that performs AC power conversion without passing through a substantially smoothing circuit regardless of whether or not it has a DC link in form is referred to as a direct AC power converter in the present application.

  Such direct AC power converters do not require large capacitors and reactors that smooth out voltage pulsations due to commercial frequencies, and therefore can be expected to be smaller, and are attracting attention as next-generation power converters in recent years. .

  In Patent Document 3, a converter and an inverter are connected, the inverter is operated based on a zero vector, and the converter is commutated when no current is input to the inverter (hereinafter also referred to as “zero current commutation”). ) Has been introduced. In addition, technologies that can share carriers between converters and inverters are also introduced. Non-Patent Document 2 introduces a direct AC power converter configuration in which the number of active elements of the converter is reduced.

Lixiang Wei, Thomas.A Lipo, “A Novel Matrix Converter Topology With Simple Commutation”, IEEE IAS 2001, vol.3, 2001, pp1749-1754. Lixiang Wei, Thomas.A Lipo, Ho Chan “Matrix Converter Topology With Reduced Number of Switches”, Proc of PESC 2002, vol.1, 2002, pp57-63 JP 2004-222338 A JP 2004-364477 A JP 2007-312589 A

  6 and 7 are circuit diagrams each showing the configuration of a conventional direct AC power converter introduced in FIGS. 5 (a) and 5 (b) in Non-Patent Document 2. FIG. The reference numerals added in FIGS. 6 and 7 are the same as those used in FIGS. 5 (a) and 5 (b), although the size of the subscripts is changed. Therefore, these codes do not necessarily match those of the embodiments described later.

  In the configuration shown in FIG. 6, the converter is composed of six transistors Sap, Sbp, Scp, San, Sbn, Scn and six diodes. When a line current for one phase is input from the power supply side, the current flows through two elements (one transistor and one diode). In the configuration shown in FIG. 7, the converter comprises three transistors Sa, Sb, Sc and 12 diodes. When a line current for one phase is input from the power supply side, the current flows through three elements (one transistor and two diodes).

  Therefore, from the viewpoint of power loss, the configuration shown in FIG. 6 is more preferable than the configuration shown in FIG.

  However, in the configuration shown in FIG. 6, in order to realize commutation in the converter, in addition to the gate drive power source for driving each of the upper-arm transistors Sap, Sbp, Scp, the lower-arm transistors San, Sbn, A gate drive power supply for driving Scn is required. On the other hand, in the configuration shown in FIG. 7, a gate drive power source for driving each of the three transistors Sa, Sb, and Sc is sufficient to realize commutation in the converter. Therefore, from the viewpoint of the number of gate drive power supplies, the configuration shown in FIG. 7 is more preferable than the configuration shown in FIG.

  Therefore, the present application reduces the number of gate drive power sources necessary to realize commutation in the converter and the number of elements that are conducted in the current flow path, and further realizes a technique that realizes zero current commutation although it is pseudo. The purpose is to provide.

  A first aspect of a direct AC power converter according to the present invention includes a pair of DC power supply lines (Lp, Ln), a converter (8), and a voltage source inverter (5). The converter includes first to Nth bidirectional switches (Sr, Ss, St) and a diode bridge (4). Any of the first to N-th bidirectional switches is on-controlled and is a commutation turn-off type. The diode bridge has first to Nth input terminals (Pr, Ps, Pt) connected to each of the first to Nth bidirectional switches, and is connected to the first to Nth input terminals. The flowing input current (Ir, Is, It) is commutated to output a rectified current (Idc) between the pair of DC power supply lines. The voltage source inverter performs switching based on pulse width modulation using space vector modulation to generate an M-phase AC voltage (Vu, Vv, Vw) from the voltage (Vdc) between the pair of DC power supply lines. To do.

  A second aspect of the direct AC power converting apparatus according to the present invention is the first aspect, wherein the bidirectional switch (Sr, Ss, St) includes a photo triac (M2), the photo triac, A light emitting diode (M3) that is optically coupled and a triac (M1) that is driven by the phototriac.

  A first aspect of the method for controlling the direct AC power converter according to the present invention is a method for controlling the first aspect of the direct AC power converter. Then, two of the first to Nth bidirectional switches (Sr, Ss, St) are turned on continuously before the operation based on the zero vector (V0) of the voltage source inverter (5). Give a trigger for.

  A second aspect of the control method for the direct AC power converting apparatus according to the present invention is the first aspect, and in the voltage source inverter (5), the pulse is obtained by comparing the carrier (C) with the signal wave. Switching based on width modulation is performed, and the activated trigger continues to be activated until the carrier takes an extreme value.

  According to the first aspect of the direct AC power converting apparatus of the present invention, when the voltage source inverter operates with a zero vector, the rectified current is substantially zero. If the rectified current does not flow substantially, the input current does not flow substantially, and the commutation turn-off type first to N-th bidirectional switches are turned off without requiring external control. Therefore, compared with the conventional current source converter, the circuit configuration for commutation is simplified, and the number of elements that conduct in the path through which the current flows is reduced.

  Further, since almost no current flows when the bidirectional switch switches from on to off, the loss associated with the switching is small.

  According to the second aspect of the direct AC power converting apparatus according to the present invention, it is not necessary to prepare a power source for driving the bidirectional switch.

  According to the first aspect of the control method of the direct AC power converting apparatus according to the present invention, the first to Nth items are triggered by the transition of the voltage source inverter from the zero vector to a voltage vector other than the zero vector. The bidirectional switch is turned on when input current flows. Therefore, the rectified current is output from the beginning of the period in which the voltage vector other than the zero vector is operated.

  According to the second aspect of the control method of the direct AC power converting apparatus according to the present invention, the bidirectional switch is turned on while avoiding automatic turn-off during the period in which the zero vector is employed in the voltage source inverter.

  FIG. 1 is a circuit diagram showing a configuration of a direct power converter 9 to which the present invention is applicable. The direct power converter 9 includes a converter 8, an inverter 5, and a pair of DC power supply lines Lp and Ln that connect the converter 8 and the inverter 5.

  The converter 8 functions as a current source rectifier circuit, rectifies three-phase (here, R-phase, S-phase, and T-phase) AC voltages Vr, Vs, and Vt obtained from the AC power source 1 and a pair of DC power source lines Lp , Ln, a rectified voltage Vdc is output. The target of rectification of the converter 8 is not limited to the three-phase voltage, and may be another multiphase voltage.

  The converter 8 includes a bidirectional switch group 3 and a diode bridge 4. The bidirectional switch group 3 includes bidirectional switches Sr, Ss, and St. The diode bridge 4 has input terminals Pr, Ps, and Pt, which are connected to one ends of the bidirectional switches Sr, Ss, and St, respectively.

The bidirectional switches Sr, Ss, and St are all turned on by an external gate signal and are not turned off by the gate signal, but are turned off because the current flowing through the bidirectional switches Sr, Ss, and St is less than the holding current. That is, the bidirectional switches Sr, Ss, St are on-controlled and are commutation turn-off types. For example, a pair of thyristors connected in parallel in the opposite direction or a bidirectional thyristor is employed. Hereinafter, gate signals for turning on the bidirectional switches Sr, Ss, and St will be referred to as Sr ^* , Ss ^* , and St ^* , respectively.

  FIG. 2 is a graph schematically showing the characteristics of the bidirectional thyristor. Even if the voltage Vf applied across the bidirectional thyristor is large, if the current Ig supplied to the gate of the bidirectional thyristor is small, the current If flowing through the bidirectional thyristor is very small. The larger the current Ig, the more it turns on with a smaller voltage Vf, and the current If starts to flow more rapidly. On the other hand, if the current If becomes the holding currents Ih1 and Ih2 or less, even if the voltage Vf is large, the current is turned off. FIG. 2 also shows the breakout voltage VBO1 (or VBO2), which is the voltage Vf at which the current If is equal to or higher than the holding current Ih1 (or Ih2) even when the current Ig is zero, and is the value closest to zero.

  FIG. 3 is a circuit diagram showing a configuration that can be adopted for the bidirectional switches Sr, Ss, St. The bidirectional switch Sj is provided with terminals J1 to J4. A first bidirectional thyristor M1 and a second bidirectional thyristor M2 are provided between the terminals J1 and J2, and a light emitting diode M3 is provided between the terminals J3 and J4. The first bidirectional thyristor M1 is driven by the second bidirectional thyristor M2. Specifically, the turn-on of the first bidirectional thyristor M1 is generated when the second bidirectional thyristor M2 is turned on. The second bidirectional thyristor M2 is a photothyristor, to which the light emitting diode M3 is optically coupled. The second bidirectional thyristor M2 is turned on by an optical trigger by the light emitting diode M3.

  Therefore, by passing a current from the terminal J3 to the terminal J4, the terminals J1 and J2 are turned on. When the current flowing between the terminals J1 and J2 becomes smaller than a predetermined value (corresponding to the holding current of the bidirectional thyristor), the terminal J1 and J2 are turned off.

  Returning to FIG. 1, the description will be continued. The diode bridge 4 commutates the input currents Ir, Is, It flowing through the input terminals Pr, Ps, Pt, respectively, and outputs a rectified current Idc between the DC power supply lines Lp, Ln. Specifically, if the subscript j is used to represent the subscripts r, s, and t, and the subscript k is used to represent the subscripts p and n, a diode Djk is provided between the input terminal Pj and the DC power supply line Lk. ing. The cathode of any diode Djk is arranged on the DC power supply line Lp side, and the anode is arranged on the DC power supply line Ln side. That is, the diode bridge 4 itself does not include an active element, and natural commutation is performed.

  The bidirectional switch group 3 is connected to the three-phase power source 1, and a three-phase voltage is applied to the other end (opposite side of the diode bridge 4) of the bidirectional switches Sr, Ss, St. As shown in the figure, a filter 2 composed of a capacitor and an inductor may be interposed between the bidirectional switch group 3 and the three-phase power source 1.

  The inverter 5 is, for example, a voltage source inverter, which receives a voltage Vdc between the DC power supply lines Lp and Ln and outputs three-phase (here, U-phase, V-phase, and W-phase) AC voltages Vu, Vv, and Vw. . The output of the inverter 5 is not limited to a three-phase voltage, and may be another multiphase voltage. Here, the inverter 5 outputs the AC voltage to the load 6.

  The inverter 5 operates by pulse width modulation according to instantaneous space vector control (hereinafter simply referred to as “vector control”).

  The load 6 is an inductive load, for example, and is a motor having a three-phase coil that is Y-connected and to which AC voltages Vu, Vv, and Vw are applied. On the circuit diagram, each resistance component of the three-phase coil is described as a resistor connected in series to the coil.

  Inverter 5 has a plurality of current paths connected in parallel between DC power supply lines Lp and Ln.

  The current path of the inverter 5 corresponding to the U phase includes a pair of switching elements Sup and Sun connected in series between the DC power supply lines Lp and Ln. An output voltage Vu is obtained from a connection point between the switching elements Sup and Sun. The current path of inverter 5 corresponding to the V phase includes a pair of switching elements Svp and Svn connected in series between DC power supply lines Lp and Ln. An output voltage Vv1 is obtained from a connection point between the switching elements Svp and Svn. The current path of inverter 5 corresponding to the W phase includes a pair of switching elements Swp and Swn connected in series between DC power supply lines Lp and Ln. An output voltage Vw is obtained from a connection point between the switching elements Swp and Swn.

  The switching elements Sup, Svp, Swp are connected to the DC power supply line Lp side. Hereinafter, these switching elements are grasped as switching elements on the upper arm side. The switching elements Sun, Svn, Swn are connected to the DC power supply line Ln side. Hereinafter, these switching elements will be grasped as switching elements on the lower arm side.

  The configuration of the switching elements Sup, Svp, Swp, Sun, Svn, and Swn itself is known and exemplified in Non-Patent Document 1, for example. In FIG. 1, the parallel connection of IGBT (insulated gate bipolar transistor) and a free-wheeling diode is illustrated as a structure of these switching elements.

The inverter 5 operates under vector control. The operation of the switching elements Sup, Svp, Swp, Sun, Svn, Swn is controlled by the gate signals Sup ^* , Svp ^* , Swp ^* , Sun ^* , Svn ^* , Swn ^{* as} control signals, and these gate signals are logical values. It is assumed that the switching elements corresponding to “1” / “0” are turned on / off. If the so-called dead time is excluded, the gate signals Sup ^* , Svp ^* , Swp ^* take complementary values to the gate signals Sun ^* , Svn ^* , Swn ^* . That is, if the subscript q is used to represent the subscripts u, v, and w, the exclusive OR of the signals Sqp ^* and Sqn ^* is “1”.

The subscript x of the vector Vx (x = 0 to 7) employed in such vector control is given by 4 · Sup ^* + 2 · Svp ^* + Swp ^* . For example, if the switching elements Sup, Svp, Swp on the upper arm side are all non-conductive, all the switching elements Sun, Svn, Swn on the lower arm side are conductive. In this case, x = 0, and the inverter 5 is in one state of a zero vector called the vector V0.

  Conversely, if the switching elements Sup, Svp, Swp on the upper arm side are all turned on, all the switching elements Sun, Svn, Swn on the lower arm side are turned off. In this case, x = 7, and the inverter 5 is in a state of a zero vector different from the vector V0, ie, the vector V7.

  FIG. 4 is a block diagram showing a configuration of the gate signal generation circuit 6. The gate signal generation circuit 6 includes a converter control unit 60 and an inverter control unit 61.

Converter control unit 60 receives angle θr indicating the phase of voltage Vr as a power supply synchronization signal, and outputs gate signals Sr ^* , Ss ^* , St ^* .

The inverter control unit 61 inputs the angle θr, the command value f ^* of the operation frequency of the inverter 4, the voltage command value v ^* , and the phase command value φ ^* (collectively referred to as “inverter command value”), and Gate signals Sup ^* , Svp ^* , Swp ^* , Sun ^* , Svn ^* , Swn ^* are output.

  As the configuration of the converter control unit 60 and the inverter control unit 61, the configuration shown as “control unit 3” in Patent Document 3 can be adopted.

  Converter control unit 60 includes trapezoidal voltage command generation unit 601, intermediate phase detection unit 602, comparison unit 603, carrier generation unit 604, and current source gate logic conversion unit 609. These are “trapezoidal voltage command signal generation unit 11”, “intermediate phase detection unit 14”, “comparison unit 12”, “carrier signal generation unit 15”, and “current source gate logic conversion unit 13” as described in Patent Document 3, respectively. Fulfills the same function.

The trapezoidal voltage command generation unit 601 generates voltage commands Vr ^* , Vs ^* , and Vt ^* for the converter 8 based on the angle θr and using the voltage Vr as a reference. Each of these voltage commands has a trapezoidal waveform with a period of 360 degrees and is shifted by 120 degrees from each other. The trapezoidal waveform exhibits a trapezoidal wave having a pair of flat sections continuous at 120 degrees and a pair of inclined areas of 60 degrees connecting the pair of flat sections. For example, the slope region takes the center as the phase reference, and the minimum value and maximum value of the waveform (which appear in the flat section) are 0 and 1, respectively, (1-√3 tan θ) / 2 or (1 + √ 3 tan θ) / 2. The method of obtaining such an inclined region and its advantages are introduced in Patent Document 3 and are not directly related to the present application, and therefore the details are omitted.

The intermediate phase detection unit 602 selects the voltage command Vr ^* , Vs ^* , Vt ^* that is not the maximum phase that takes the maximum value and that is not the minimum phase that takes the minimum value, in other words, that exhibits an inclined region. Since the converter 8 is a current source rectifier, in principle, current flows through the upper arm side diode corresponding to the maximum phase and the lower arm side diode corresponding to the minimum phase, and the upper arm side diode corresponding to the intermediate phase and the lower It operates with current flowing alternately to the arm side diode.

For example, it is assumed that the voltage commands Vr ^* and Vt ^* take a flat section in which the maximum value and the minimum value are taken, and the voltage command Vs ^* takes a slope region. In the following description, it is assumed that the direct power converter 9 and the gate signal generation circuit 6 operate in such a situation unless otherwise specified. Since the voltage commands Vr ^* , Vs ^* , and Vt ^* exhibit the same waveform except for the phase shift, the generality is not lost even if such an assumption is made.

In such a case, the intermediate phase detection unit 602 selects the voltage command Vs ^* . The ratio between the value Vr ^* −Vs ^* (= 1−Vs ^* ) and the value Vs ^* −Vt ^* (= Vs ^* ) is the ratio of the period during which the diode Drp is conductive and the period during which the diode Dsp is conductive. That is, the conduction ratio for the S phase of the converter 8 is determined by the voltage command Vs ^* selected by the intermediate phase detection unit 602. The ratio of the period during which the diode Drp is conductive and the period during which the diode Dsp is conductive is represented by drt: dst (drt + dst = 1). The intermediate phase detector 602 outputs the values drt and dst.

The carrier generation unit 604 outputs a carrier C that takes the minimum and maximum values (0 and 1 in the above example) of the voltage commands Vr ^* , Vs ^* , and Vt ^* , respectively. For example, the carrier C is a triangular wave.

The comparator 603 compares the voltage commands Vr ^* , Vs ^* , Vt ^* with the carrier C. Based on the comparison result and the output of the half cycle selection circuit 608 described later, the current source signal logic conversion unit 609 outputs the gate signals Sr ^* , Ss ^* , St ^* .

  The inverter control unit 61 includes a modulation waveform generation unit 611, calculation units 612 and 613, comparison units 614 and 615, and a logical sum calculation unit 619. These perform the same functions as the “output voltage command signal generation unit 21”, “calculation units 22 and 23”, “comparison unit 24”, and “OR operation unit 25” described in Patent Document 3, respectively.

The modulation waveform generator 611 outputs phase voltage commands Vu ^* , Vv ^* , Vw ^* based on the first command value and the angle θr. These are command values for the output voltages Vu, Vv, Vw.

The arithmetic units 612 and 613 generate signal waves to be compared with the carrier based on the values drt and dst for the phase voltage commands Vu ^* , Vv ^* and Vw ^* . The generation of the signal wave will be outlined later.

The comparison unit 614 compares the result of the calculation unit 612 with the carrier C, and the comparison unit 615 compares the result of the calculation unit 613 with the carrier C. Based on these comparison results, the OR operation unit 619 outputs gate signals Sup ^* , Svp ^* , Swp ^* , Sun ^* , Svn ^* , Swn ^* .

FIG. 5 is a graph for explaining generation of the gate signals Sr ^* , Ss ^* , St ^* , Sup ^* , Svp ^* , and Swp ^* . If the dead time is ignored for simplicity, the gate signals Sun ^* , Svn ^* , Swn ^* are not shown here because they are obtained complementarily to the gate signals Sup ^* , Svp ^* , Swp ^* .

  One period ts of the carrier C is internally divided by values dst and drt indicating the commutation ratio, and is divided into a period dst · ts and a period dst · ts. The commutation of the converter 8 is performed at the divided timing. As described above, the minimum value and the maximum value of the carrier C are 0 and 1, respectively, and dst + drt = 1. Therefore, the commutation of the converter 8 is specifically performed at the timing when the carrier C takes the value drt.

The commutation of the converter 8 is actually performed by switching of the bidirectional switches Sr, Ss, St. In the commutation operation, turn-on does not occur unless the gate signals Sr ^* , Ss ^* , St ^* are activated. Therefore, in order to realize the zero current commutation, it is required that the inverter 5 adopts the zero vectors V0 and V7 in a period including the timing when the gate signals Sr ^* , Ss ^* and St ^* are activated. In other words, the inverter 5 is required to take the zero vectors V0 and V7 in a period including the timing when the carrier C takes the value drt.

More precisely, the gate signals Sr ^* , Ss ^* ,... Are used as triggers for turning on any two of the bidirectional switches Sr, Ss, St continuously before the end of the operation based on the zero vector V0 of the inverter 5. Activate St ^* . In order for the inverter 5 to perform such an operation, a signal wave and a carrier C as described later are compared.

  On the other hand, since turn-off occurs when the current flowing through itself is less than the holding current, pseudo-current commutation is realized although it is pseudo. That is, if the inverter 5 adopts the zero vectors V0 and V7 at the timing when the carrier C takes the value drt, the turn-off of the zero current commutation is naturally realized.

  Strictly speaking, it is not zero current commutation because it turns off when a current equal to or lower than the holding current flows. However, the holding current is generally small, in other words, almost no current flows when the bidirectional switches Sr, Ss, St are switched from on to off. Therefore, the loss accompanying the switching is small.

  FIG. 5 illustrates the case where the inverter 5 adopts the zero vector V0 at the timing when the carrier C takes the value drt. Normally, the transition of the voltage vector in the inverter 5 is performed by switching conduction / non-conduction between the upper arm side switching element Sqp and the lower arm side switching element Sqn in any one of the three phases.

  Since the zero vector V7 is not adopted now, if the W-phase upper arm side switching element Swp is non-conductive, the voltage vector other than the zero vector V0 can be any one of V2, V4 and V6. The transition between the voltage vectors V2 and V4 cannot be realized by switching between conduction / non-conduction between the upper arm side switching element Sqp and the lower arm side switching element Sqn in one phase. Therefore, here, the case where the voltage vectors V4 and V6 are employed in addition to the zero vector V0 is illustrated.

Of course, a pattern employing V0, V2, and V6 as the voltage vector may be used. Which of these voltage vector patterns the inverter 5 can take depends on the magnitude relationship of the output voltage commands Vu ^* , Vv ^* , Vw ^* . For simplicity, a period in which the magnitude relationship between the output voltage commands Vu ^* , Vv ^* , and Vw ^* does not change will be considered below.

  As described above, in the pattern employing the voltage vectors V0, V4 and V6, the voltage vector V0 → V4 → V6 → V4 → V0 is changed. The period in which each of these voltage vectors V0, V4, V6 is adopted in one cycle of carrier C is d0: d4: d6 (where d0 + d4 + d6 = 1).

  The period when the voltage vectors V0, V4, V6 are adopted is prorated by the periods dst · ts, drt · ts, and the timing at which the carrier C takes the value drt is included in the voltage vector V0. Adopted: drt + dst, drt + dst (d0 + d4), drt + dst · d0, drt, drt (1-d0), drt (1-d0-d4).

Since the voltage vectors V0, V4, V6 correspond to the values d0, d4, d6, respectively, the calculations based on the values drt, dst and the phase voltage commands Vu ^* , Vv ^* , Vw ^* performed in the calculation units 612, 613 are as follows. Are representatively indicated by drt + dst · V ^* and drt (1−V ^* ), respectively. Here, the symbol V ^* representatively represents a voltage vector.

The gate signal Sup ^* is a period in which the voltage vector V0 is employed, Svp ^*, any Swp ^* of not activate, the gate signal is a gate signal Sup ^* activated during a period in which the voltage vector V4 is employed Svp ^*, Swp ^* is not activated, and the gate signals Sup ^* and Svp ^* are activated and the gate signal Swp ^* is not activated during the period when the voltage vector V6 is employed. Therefore, in the pattern employing the voltage vectors V0, V4, V6, the phase voltage commands Vu ^* , Vv ^* , Vw ^* are selected as values 1-d0, 1-d0-d4 (= d6), 0, respectively.

When the value of the carrier C is C0, the gate signal Sup ^* is activated when either drt + dst · d0 ≦ C0 ≦ drt + dst = 1 and 0 ≦ C0 ≦ drt (1−d0) is satisfied, and drt + dst (d0 + d4 ) ≦ C0 ≦ drt + dst = 1 and 0 ≦ C0 ≦ drt (1−d0−d4) are satisfied, the gate signal Svp ^* is activated. The gate signal Swp ^* remains inactive. Thereby, the ratio of the periods in which each of the voltage vectors V0, V4, V6 is adopted in one cycle of the carrier C is d0: d4: d6.

  The inverter 5 operates based on the zero vector V0 while the carrier C takes the values drt (1-d0) to drt to drt + dst · d0. Therefore, before the operation based on the zero vector V0 ends, a trigger for turning on any two of the bidirectional switches Sr, Ss, St is given to the bidirectional switches Sr, Ss, St.

As described above, it is assumed that the voltage commands Vr ^* and Vt ^* take a flat section in which the maximum value and the minimum value respectively take place, and the voltage command Vs ^* takes an inclined region. Regardless of this, the bidirectional switches Ss and St are alternately conducted. Two periods drt · ts and dst · ts are defined by dividing one period ts of the carrier C by a ratio drt: dst between a period in which the diode Drp is conductive and a period in which the diode Dsp is conductive.

In the period drt · ts, the bidirectional switch Sr is turned on so that the diode Drp is turned on, and in the period dst · ts, the bidirectional switch Ss is turned on so that the diode Dsp is turned on. However, it is desirable that the gate signals Sr ^* and Ss ^* are activated more than half of each period from the start of the periods drt · ts and dst · ts, respectively.

For example, if the period during which the gate signal Sr ^* is activated is activated less than half of the period from the start of the period drt · ts, the bidirectional switch Sr may not be turned on. This is because the zero vector V0 may be employed from the start of the period drt · ts to a period less than drt · ts / 2, and the current Idc does not flow during the period in which the zero vector V0 is employed. That is, the gate signals Sr ^* and Ss ^* are automatically activated during the period in which the zero vector V0 is adopted by the inverter 5 by activating more than half of the periods from the start of the periods drt · ts and dst · ts, respectively. The bidirectional switches Sr, Ss, and St are turned on while avoiding unnecessary turn-off.

  The half cycle selection unit 608 receives the values drt and dst and the carrier C, and outputs the periods drt · ts / 2 and dst · ts / 2 to the current source gate logic conversion unit 609. However, one of the values drt and dst can be easily obtained from the other, and the period ts of the carrier C is normally set constant. Therefore, the value drt (or value dst) can be input to the half cycle selection unit 608, and the cycle ts of the carrier C can be stored in advance.

The current-type gate logic conversion unit 609 starts the activation of the gate signal Ss ^* when the carrier C reaches the value drt from less than the value drt in the comparator 603, and performs the activation at least in the period dst · ts / 2 or more. maintain. In the comparator 603, the activation of the gate signal Sr ^* is started when the carrier C becomes less than the value drt from the value drt or more, and the activation is maintained at least for the period drt · ts / 2 or more.

In the situation illustrated here, that is, when the voltage commands Vr ^* and Vt ^* take a flat section where the maximum value and the minimum value are respectively taken, the gate signal St ^* may be activated without depending on the value of the carrier C. . Alternatively, the gate signal St ^* may be obtained as a logical sum of the gate signals Sr ^* and Ss ^* . If either one of the currents Ir and Is flows, the current It flows, so the bidirectional switch St does not turn off.

More simply, the half cycle selection unit 608 may input only the carrier C. Even if the gate signals are Sr ^* and Ss ^* , they continue to be activated until the value of the carrier C takes an extreme value (peak or valley). Thereby, the gate signals Sr ^* , Ss ^* , St ^* as described above can be generated more easily.

  In other words, the trigger for turning on the bidirectional switches Sr, Ss, St is turned on before the operation based on the zero vector V0 of the inverter 5 is completed, and is activated until the carrier C used in the pulse width control of the inverter 5 takes an extreme value. It is desirable to continue.

  In the pattern that also employs the zero vector V7, the voltage vector V0 → V4 → V6 → V7 → V6 → V4 → V0 changes. In such a pattern, the zero vector V7 is adopted in these periods in both the periods drt · ts and dst · ts. However, by adopting the zero vector V7 within these periods, the current Idc does not flow, and the bidirectional switches Sr and Ss are turned off. Therefore, it is not desirable for the inverter 5 to adopt the zero vector in a period not including the timing at which the converter 8 is commutated.

  FIG. 5 shows the absolute values of the currents Ir, Is, It, Idc. In the graph showing these, hatched areas indicate areas where no current flows because no current flows through the inverter 5.

Thus, when obtaining the gate signals Sr ^* , Ss ^* , St ^* for controlling the operation of the converter 8 (more precisely, the turn-on of the bidirectional switches Sr, Ss, St), the trapezoidal voltage command Vr ^{* is obtained.} , Vs ^* , Vt ^* and carrier C are compared. When generating the gate signals Sup ^* , Svp ^* , Swp ^* , Sun ^* , Svn ^* , Swn ^* for controlling the inverter 5, the values drt and dst are calculated with the carrier C as the calculation result of the phase voltage command of the inverter 5. Compare.

  Thus, direct conversion can be performed while performing commutation of the converter 8 during the zero vector period of the inverter 5 (that is, performing zero current commutation). In the converter 8, an element that conducts in a path through which current flows (using the suffix j representing the suffixes r, s, and t) is one of the bidirectional switches Sj per phase and the diode Djk. One of them will be two. Moreover, the number of phases is sufficient for driving the bidirectional switch Sj. Therefore, as compared with the conventional current source converter shown in FIGS. 6 and 7, the circuit configuration for commutation is simplified, and the number of conductive elements in the path through which current flows is reduced.

Furthermore, by adopting the configuration shown in FIG. 3 as the bidirectional switch Sj, it is not necessary to prepare a power source for driving the bidirectional switch Sj. This is because the gate signals Sr ^* , Ss ^* and St ^* can be used as they are because the current flowing between the terminals J3 and J4 is small.

It is a circuit diagram which shows the structure of the direct power converter which can apply this invention. It is a graph which shows typically the characteristic of a bidirectional thyristor. It is a circuit diagram which shows the structure of a bidirectional switch. It is a block diagram which shows the structure of a gate signal generation circuit. It is a graph explaining the production | generation of a gate signal. It is a circuit diagram which shows the structure of the conventional direct AC power converter. It is a circuit diagram which shows the structure of the conventional direct AC power converter.

Explanation of symbols

4 Diode Bridge 5 Inverter 8 Converter 9 Direct AC Power Converter C Carrier Idc Rectified Current Ir, Is, It Input Current Lp, Ln DC Power Supply Line Pr, Ps, Pt Input Terminal Sr, Ss, St Bidirectional Switch Vdc Voltage Vu , Vv, Vw AC voltage

Claims (4)

A pair of DC power supply lines (Lp, Ln);
Any one of the first to Nth bidirectional switches (Sr, Ss, St) and the first to Nth bidirectional switches connected to each of the first to Nth bidirectional switches, which are on-controlled and are commutation turn-off types. 1 to Nth input terminals (Pr, Ps, Pt), and commutates input currents (Ir, Is, It) that flow through the first to Nth input terminals between the pair of DC power supply lines. A converter (8) having a diode bridge (4) for outputting a rectified current (Idc);
A voltage source inverter (5) that performs switching based on pulse width modulation using space vector modulation to generate an M-phase AC voltage (Vu, Vv, Vw) from a voltage (Vdc) between the pair of DC power supply lines. A direct AC power converter (9).   The bidirectional switch (Sr, Ss, St) includes a phototriac (M2), a light emitting diode (M3) optically coupled to the phototriac, and a triac (M1) driven by the phototriac. Item 4. The direct AC power converter according to Item 1. A method for controlling a direct AC power converter according to claim 1, comprising:
In order to turn on any two of the first to Nth bidirectional switches (Sr, Ss, St) continuously before the end of the operation based on the zero vector (V0) of the voltage source inverter (5). A control method for a direct AC power conversion device that gives a trigger. In the voltage source inverter (5), switching based on the pulse width modulation is performed by comparing the carrier (C) and the signal wave,
4. The control method for a direct AC power converting apparatus according to claim 3, wherein the activated trigger continues to be activated until the carrier takes an extreme value.

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