JP4974497B2 - Imaging device - Google Patents

Description

  The present invention relates to a photographing apparatus such as a digital still camera provided with a solid-state imaging device composed of a CCD or the like.

In recent years, digital still cameras having a solid-state imaging device composed of a CCD or the like have become widespread.
FIG. 2 shows a configuration of an interline transfer type solid-state imaging device (1) used in a digital still camera. In the solid-state imaging device (1), a color filter array is provided on a plurality of photosensors arranged in a matrix to form an imaging surface composed of a plurality of pixels (11), and a plurality of pixels arranged in the vertical direction. A plurality of vertical registers (12) for transferring the charges of the pixels (11) in the column in the vertical direction, and a horizontal register (1H) for outputting the charges transferred by these vertical registers (12) in a cycle of one horizontal period (1H) 13).

The solid-state imaging device (1) has an input terminal 8 for a first vertical transfer pulse Vφ1 having a first phase, an input terminal 7 for a second vertical transfer pulse Vφ2 having a second phase, and a third phase. A pair of third vertical transfer pulses Vφ3A and Vφ3B, input terminals 6 and 5, an input terminal 4 of a fourth vertical transfer pulse Vφ4 having a fourth phase, and a pair of fifth vertical transfer pulses Vφ5A and Vφ5B having a fifth phase Input terminals 3 and 2 and an input terminal 1 for a sixth vertical transfer pulse Vφ6 having a sixth phase. By supplying each vertical transfer pulse to these input terminals, the electric charge accumulated in the vertical register (12) is transferred to the horizontal register (13).
The solid-state imaging device (1) includes a pair of first horizontal transfer pulses Hφ1A and Hφ1B input terminals 21 and 16 and a pair of second horizontal transfer pulses Hφ2A obtained by inverting the first horizontal transfer pulse, respectively. Hφ2B input terminals 22 and 17 are provided. By supplying each horizontal transfer pulse to these input terminals, the charges transferred from the vertical register (12) to the horizontal register (13) are output to the outside.
Further, the solid-state imaging device (1) is provided with an input terminal 19 for a sub-pulse φSUB for executing an electronic shutter operation for sweeping out charges accumulated in the pixels before exposure on the imaging surface. Note that “electronic shutter pulse” may be used as another name for “sub-pulse” and the following “sub-timing pulse”.

  FIG. 8 shows a configuration of a conventional digital still camera including the solid-state imaging device (1). A vertical transfer drive circuit (2) and a horizontal transfer drive circuit (3) are connected to the solid-state imaging device (1), and the first vertical transfer pulse Vφ1 and the second vertical transfer pulse are supplied from the vertical transfer drive circuit (2). A transfer pulse Vφ2, a pair of third vertical transfer pulses Vφ3A, Vφ3B, a fourth vertical transfer pulse Vφ4, a pair of fifth vertical transfer pulses Vφ5A, Vφ5B, a sixth vertical transfer pulse Vφ6 and a sub-pulse φSUB are supplied and horizontal transfer is performed. A pair of first horizontal transfer pulses Hφ1A and Hφ1B and a pair of second horizontal transfer pulses Hφ2A and Hφ2B are supplied from the drive circuit (3).

A timing generator (TG) (40) is connected to the vertical transfer driving circuit (2) and the horizontal transfer driving circuit (3). The timing generator (40) uses a counter (not shown) as will be described later, and uses a first vertical timing pulse, a second vertical timing pulse, a pair of third vertical timing pulses, a fourth vertical timing pulse, and a pair of fifth vertical timings. A pulse, a sixth vertical timing pulse, a charge readout pulse, and a sub-timing pulse are generated, and these pulses are supplied to the vertical transfer driving circuit (2). In addition, a pair of first horizontal timing pulses and a pair of second horizontal timing pulses are generated using the driving clock, and these pulses are supplied to the horizontal transfer driving circuit (3).
In the vertical transfer driving circuit (2), the first to sixth vertical transfer pulses Vφ1, Vφ2, Vφ3A, Vφ3B, Vφ4, Vφ5A from the charge readout pulse obtained from the timing generator (40) and the first to sixth vertical timing pulses, Vφ5B and Vφ6 are created, and the sub-pulse φSUB is created by amplifying the sub-timing pulse, and the created pulse is supplied to the solid-state imaging device (1). On the other hand, in the horizontal transfer driving circuit (3), a pair of first horizontal transfer pulses Hφ1A, Hφ1B and a pair of first horizontal timing pulses and a pair of second horizontal timing pulses obtained from the timing generator (40) are amplified. A pair of second horizontal transfer pulses Hφ2A and Hφ2B are generated, and these pulses are supplied to the solid-state imaging device (1).

  The CCD output obtained from the solid-state imaging device (1) is a predetermined image processing such as a CDS / AGC circuit (5) comprising a sampling unit CDS and a gain control unit AGC, an A / D converter (6), and compression processing. After passing through the image processing circuit (7) for performing the above, it is output to the subsequent circuit. Sampling signals SHP and SHD for sampling the CCD output are supplied from the timing generator (40) to the CDS / AGC circuit (5), and from the timing generator (40) to the A / D converter (6). A sampling signal ADCK for A / D conversion is supplied.

A control circuit (80) is connected to the timing generator (40) and the image processing circuit (7), and a shutter button (9) is connected to the control circuit (80).
The control circuit (80) acquires the image signal (luminance signal) of the effective area of the solid-state imaging device (1) from the image processing circuit (7), detects the signal level of the image signal, and based on the detection result. The exposure time and focus adjustment value are calculated. Then, the operation of the timing generator (40) and a lens driving circuit (not shown) is controlled according to the calculation result.

FIG. 9 shows the configuration of the vertical timing pulse and sub-timing pulse generator of the timing generator (40).
The timing generator includes a horizontal counter (41) that is counted up in synchronization with a drive clock, and a vertical counter (42) that is counted up in synchronization with a horizontal synchronization pulse HD supplied from the horizontal counter (41). And a field counter (43) that counts up in synchronization with the vertical synchronizing pulse VD supplied from the vertical counter (42). The horizontal counter (41) is supplied with the vertical synchronizing pulse VD from the vertical counter (42), and the horizontal synchronizing pulse HD and the vertical synchronizing pulse VD are synchronized.

  A comparator (47) is connected to the three counters (41), (42), and (43), and the comparator (47) stores waveform information about vertical timing pulses and sub-timing pulses. A waveform information storage register (46) is connected.

The three counters (41), (42), and (43) are connected to a maximum value storage register (44). These counters (41), (42) are connected to the maximum value storage register (44). The maximum values Hmax, Vmax, and Fmax to be counted are supplied to (43), respectively.
Further, the vertical counter (42) is connected to a signal generator (SG) (45) for outputting a reference vertical synchronizing signal VDo at a period of 1/30 seconds, and from the control circuit (80) shown in FIG. A controller (49) for controlling the operation of the vertical counter (42) based on a control signal is connected. The controller (49) has a synchronization state in which a vertical synchronization pulse VD is synchronized with the reference vertical synchronization pulse VDo. A synchronous / asynchronous switching control signal for switching between asynchronous states not to be synchronized is supplied to the vertical counter (42).

Each time the count value of the horizontal counter (41) is counted up, the count value Hcount is output from the horizontal counter (41) to the comparator (47). When the count value reaches the maximum value Hmax supplied from the maximum value storage register (44), the horizontal synchronization pulse HD is output from the horizontal counter (41) to the vertical counter (42) and the comparator (47). At the same time, the count value is reset to the value “1” and the count-up is started again from the value “1”.
The vertical counter (42) is counted up in synchronization with the horizontal synchronizing pulse HD supplied from the horizontal counter (41) as described above, and the count value Vcount is output from the vertical counter (42) to the comparator (47) each time. Is done. When the count value reaches the maximum value Vmax supplied from the maximum value storage register (44), the vertical counter (42) to the comparator (47), the horizontal counter (41), and the field counter (43). While the vertical synchronization pulse VD is output, the count value is reset to the value “1”, and the count-up is started again from the value “1”.
The field counter (43) is counted up in synchronization with the vertical synchronizing pulse VD supplied from the vertical counter (42) as described above, and the count value Fcount is output from the field counter (43) to the comparator (47) each time. Is done. When the count value reaches the maximum value Fmax supplied from the maximum value storage register (44), the count value is reset to “0” and starts counting up again from the value “1”. Is done.

  In the comparator (47), the count value Hcount supplied from the horizontal counter (41), the count value Vcount supplied from the vertical counter (42), the count value Fcount supplied from the field counter (43), and waveform information storage The count value included in the waveform information supplied from the register (46) is compared, and the output of the comparator (47) switches from high to low or from low to high according to the comparison result. At this time, the horizontal synchronization pulse HD supplied from the horizontal counter (41) and the vertical synchronization pulse VD supplied from the vertical counter (42) are synchronized. In this way, a vertical timing pulse and a sub-timing pulse composed of rectangular pulses are generated. The generated sub-timing pulse is output from the timing generator (40) during a period in which the enable signal generated according to the exposure time calculated as described above is high.

In the digital still camera, it is possible to set a monitor mode for displaying a moving image (through image) photographed by the solid-state imaging device (1) on the LCD at a period of 1/30 seconds. FIG. And the sub-pulse φSUB supplied to the solid-state imaging device (1). In FIG. 10, the shutter pulse is a pulse generated when the shutter button (9) is pressed.
The solid-state imaging device (1) can set a thinning readout mode for reading out charges of a plurality of pixels at a rate of, for example, one line out of eight lines among a plurality of pixels constituting the imaging surface. The image sensor (1) is set to a thinning readout mode.
In the digital still camera, the exposure time is controlled by supplying a series of sub-pulses φSUB to the solid-state imaging device (1) in a period excluding the exposure time in one vertical period, and the monitor mode is set. In the state, in one vertical period, a series of sub-pulses φSUB is supplied to the solid-state imaging device (1), and the charges accumulated in the pixels (11) are swept away, and then the imaging surface is exposed to the next vertical. During the period, the charge accumulated in the pixel (11) by the exposure is transferred, and a process for creating a display image to be displayed on the LCD from the transferred charge (display process) is performed. Then, in the next vertical period, the created display image is displayed on the LCD. By repeating this series of operations, that is, exposure, transfer, display image creation and display, with a shift of one vertical period, an image is taken at a period of 1/30 seconds and displayed on the LCD.
In each vertical period, the calculation of the exposure time and the focus adjustment value is started based on the image signal obtained by the transfer, and the calculation is continuously performed in the next vertical period. An exposure time and a focus adjustment value are set.

  When the shutter button (9) is pressed while the monitor mode is set, a series of sub-pulses φSUB are supplied to the solid-state imaging device (1) and accumulated in the pixel (11) in the next vertical period. After the charges are swept away, the imaging surface is exposed. Thereafter, the all-pixel capture mode is set in synchronization with the vertical synchronization pulse VD, the charges of all the pixels constituting the imaging surface are transferred divided into a plurality of fields, and the image signal obtained by the transfer is recorded on the recording medium. Is done. At this time, the last image displayed in the monitor mode is continuously displayed on the LCD. Hereinafter, the last exposure performed in the monitor mode when the shutter button (9) is pressed is referred to as final exposure.

  Incidentally, the time of 1H in the monitor mode is determined by the number of pixels of the solid-state imaging device, the frequency of the driving clock (driving frequency), the pixel thinning rate, and the like. For example, in a digital still camera in which the drive frequency is 24.5454 MHz and the number of pixels in the monitor mode is represented by (3532 pixels × 225 lines + 1798 pixels), the time of 1H is 148 μsec.

FIG. 11 shows operations of the horizontal counter (41) and the vertical counter (42) of the conventional digital still camera in which the time of 1H in the monitor mode is 148 μsec.
The horizontal counter (41) counts up from the initial value “1” in synchronization with the drive clock. When the count value reaches the maximum value “3532” as shown in the drawing, the horizontal counter (41) outputs a horizontal synchronization pulse HD and counts. The value is reset to the value “1” and the count-up starts again from the value “1”. In this manner, the horizontal counter (41) repeats counting up from “1” to “3532”, and outputs a horizontal synchronization pulse HD every time the count value reaches the maximum value “3532”. On the other hand, the vertical counter (42) is counted up from the initial value “1” in synchronization with the horizontal synchronizing pulse HD. When the count value of the horizontal counter (41) reaches the maximum value “3532” for the 225th time, the count value is reset to the value “1”, and the count-up is started again from the value “1”. Thereafter, when the count value reaches the maximum value “1798”, the horizontal synchronization pulse HD is output, the count value is reset to “1”, and the count-up is started again from the value “1”. At this time, the count value of the vertical counter (42) reaches the maximum value “226”, and the vertical counter (42) outputs the vertical synchronization pulse VD and resets the count value to the value “1”. Then, counting up starts again from the value “1”.
In this way, in the monitor mode, the horizontal synchronization pulse HD is output from the horizontal counter (41) at a cycle of 148 μs, and the horizontal synchronization pulse HD, that is, the horizontal of the solid-state image pickup device (1) at a cycle of 1H. The electric charge of the register (13) is output, and the sub-pulse φSUB is supplied to the solid-state imaging device (1) with a period of 1H. Further, a vertical synchronization pulse VD is output from the vertical counter (42) at a period of 1/30 seconds, and an image is displayed on the LCD in synchronization with the vertical synchronization pulse VD.

A pulse generator that controls the timing of outputting sub-pulses and charge pulses with a single counter has been proposed (see Patent Document 1).
In addition, an imaging apparatus has been proposed in which the number of electronic shutters is set to be the same between the monitoring period and the main exposure period (see Patent Document 2).
JP-A-7-203310 [H04N 5/335] JP 2004-23208 A [H04N 5/335]

However, the conventional digital still camera has a problem that the photographing time from when the shutter button (9) is pressed to when the image recording is finished becomes long.
An object of the present invention is to provide a photographing apparatus such as a digital still camera that can shorten the photographing time from when an image photographing operation is performed to when the image recording is completed.

  Therefore, as a result of intensive studies to solve the above problems, the present inventor has used the image signal obtained by the transfer in the vertical period in which the final exposure is performed as shown in FIG. 10 to calculate the exposure time and the focus adjustment value. In addition, since the image created by the display process in the vertical period is not displayed on the LCD, it is thought that there is no need to perform the transfer process and the display process in the vertical period, and the present invention has been completed.

  An imaging device according to the present invention includes a solid-state imaging device having an imaging surface composed of a plurality of pixels, a driving device that drives the solid-state imaging device, and a control device that controls the operation of the driving device, and the driving The apparatus includes a synchronization signal generation circuit that generates a synchronization signal, and a sub-pulse supply circuit that supplies a sub-pulse for sweeping out charges accumulated in the pixels to the outside to the solid-state imaging device. Then, the imaging apparatus performs imaging in which an exposure operation for exposing the imaging surface after supplying a series of sub-pulses to the solid-state imaging device is started in synchronization with a synchronization signal generated at a constant cycle from the synchronization signal generation circuit. The mode can be set, and the control device synchronizes with a synchronization signal generated from the synchronization signal generation circuit when an image shooting operation is performed in a state where the shooting mode is set. In addition to starting exposure, the period of the synchronization signal is set to the same time as the exposure time of the imaging surface, and then the charge is read from the solid-state imaging device in synchronization with the synchronization signal generated from the synchronization signal generation circuit. Control means for starting the photographing operation is provided.

In the imaging apparatus according to the present invention, a synchronization signal is generated from the synchronization signal generation circuit at a constant period when the imaging mode is set, and a series of sub-pulses are applied to the solid-state imaging device in synchronization with the synchronization signal. The exposure operation for exposing the imaging surface is started after supplying the.
Then, when an image shooting operation is performed in a state where the shooting mode is set, exposure of the imaging surface is started in synchronization with the synchronization signal generated from the synchronization signal generation circuit, and the cycle of the synchronization signal Is set to the same time as the exposure time of the imaging surface. Therefore, a synchronization signal is generated from the synchronization signal generation circuit when the exposure time has elapsed since the exposure of the imaging surface was started. Then, a photographing operation including reading of charges from the solid-state image sensor is started in synchronization with the synchronization signal. As described above, when the image capturing operation is performed, the exposure of the imaging surface is started in synchronization with the synchronization signal. Therefore, the exposure of the imaging surface has been performed after supplying a series of subpulses to the solid-state imaging device. Compared to a digital still camera, the shooting time from when an image shooting operation is performed until image recording is completed is shorter. The same time as the above exposure time includes substantially the same time as the exposure time.

  Specifically, the control device includes an exposure time deriving unit that derives an exposure time according to the magnitude of incident light on the solid-state imaging device, and the control unit determines the period of the synchronization signal. It is set to the same time as the exposure time obtained from the exposure time deriving means.

More specifically, the synchronization signal generation circuit of the driving device counts up at a constant period and generates a synchronization signal when the count value reaches a value supplied from the outside. The control means of the apparatus calculates a value to be supplied to the synchronization signal generating circuit based on the exposure time obtained from the exposure time deriving means, and supplies the calculated value to the synchronization signal generating circuit.
In this specific configuration, the synchronization signal generation circuit generates a synchronization signal when the count value reaches a value supplied from the outside, and therefore supplies a value calculated based on the exposure time to the synchronization signal generation circuit. Thus, the period of the synchronization signal can be set to the same time as the exposure time.

More specifically, the driving device includes a horizontal synchronizing signal generating circuit that generates a horizontal synchronizing signal, and the synchronizing signal generating circuit generates a vertical synchronizing signal and is synchronized with the horizontal synchronizing signal. The control unit of the control device calculates a value to be supplied to the synchronization signal generating circuit from the exposure time obtained from the exposure time deriving unit and the period of the horizontal synchronization signal.
In this specific configuration, the synchronization signal generation circuit is counted up in synchronization with the horizontal synchronization signal, so that it should be supplied to the synchronization signal generation circuit, for example, by dividing the exposure time by the period of the horizontal synchronization signal. The value can be obtained.

More specifically, the control means of the control device supplies a sub pulse from the drive device to the solid-state image sensor at the start of exposure of the imaging surface.
In this specific configuration, when the exposure of the imaging surface is started, the charges accumulated in the pixels are swept out to the outside.

  According to the photographing apparatus of the present invention, when an image photographing operation is performed, the exposure of the imaging surface is started in synchronization with the synchronization signal. Therefore, the exposure of the imaging surface is performed after supplying a series of subpulses to the solid-state imaging device. Compared to a conventional digital still camera that has been used, it is possible to shorten the shooting time from when an image shooting operation is performed until image recording is completed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments in which the present invention is implemented in a digital still camera having a solid-state imaging device composed of a CCD will be specifically described below with reference to the drawings.
The digital still camera according to the present invention includes a solid-state imaging device (1) shown in FIG. 2, and the solid-state imaging device (1) has an input terminal 8 for a first vertical transfer pulse Vφ1 having a first phase. , An input terminal 7 of a second vertical transfer pulse Vφ2 having a second phase, a pair of third vertical transfer pulses Vφ3A and Vφ3B having a third phase, input terminals 6 and 5, a fourth vertical having a fourth phase. There are provided an input terminal 4 for the transfer pulse Vφ4, a pair of fifth vertical transfer pulses Vφ5A and Vφ5B having the fifth phase 3, 2 and an input terminal 1 for the sixth vertical transfer pulse Vφ6 having the sixth phase. It has been.
The solid-state imaging device (1) includes a pair of first horizontal transfer pulses Hφ1A and Hφ1B input terminals 21 and 16 and a pair of second horizontal transfer pulses Hφ2A and Hφ2B formed by inverting the first horizontal transfer pulse. Input terminals 22 and 17 are provided.
Further, the solid-state imaging device (1) is provided with an input terminal 19 for a sub pulse φSUB for executing an electronic shutter operation.

  FIG. 1 shows the configuration of a digital still camera according to the present invention. A vertical transfer drive circuit (2) and a horizontal transfer drive circuit (3) are connected to the solid-state imaging device (1), and the first vertical transfer pulse Vφ1 and the second transfer pulse from the vertical transfer drive circuit (2). A vertical transfer pulse Vφ2, a pair of third vertical transfer pulses Vφ3A, Vφ3B, a fourth vertical transfer pulse Vφ4, a pair of fifth vertical transfer pulses Vφ5A, Vφ5B, a sixth vertical transfer pulse Vφ6, and a sub-pulse φSUB are supplied. A pair of first horizontal transfer pulses Hφ1A and Hφ1B and a pair of second horizontal transfer pulses Hφ2A and Hφ2B are supplied from the transfer drive circuit (3).

A timing generator (TG) (4) is connected to the vertical transfer drive circuit (2) and the horizontal transfer drive circuit (3). The timing generator (4) uses a counter (not shown) as will be described later, and uses a first vertical timing pulse, a second vertical timing pulse, a pair of third vertical timing pulses, a fourth vertical timing pulse, and a pair of fifth vertical timings. A pulse, a sixth vertical timing pulse, a charge readout pulse, and a sub-timing pulse are generated, and these pulses are supplied to the vertical transfer driving circuit (2). In addition, a pair of first horizontal timing pulses and a pair of second horizontal timing pulses are generated using the driving clock, and these pulses are supplied to the horizontal transfer driving circuit (3).
In the vertical transfer driving circuit (2), the first to sixth vertical transfer pulses Vφ1, Vφ2, Vφ3A, Vφ3B, Vφ4, Vφ5A from the charge readout pulse obtained from the timing generator (4) and the first to sixth vertical timing pulses, Vφ5B and Vφ6 are created, and the sub-pulse φSUB is created by amplifying the sub-timing pulse, and the created pulse is supplied to the solid-state imaging device (1). On the other hand, the horizontal transfer driving circuit (3) amplifies the pair of first horizontal timing pulses and the pair of second horizontal timing pulses obtained from the timing generator (4) to thereby generate a pair of first horizontal transfer pulses Hφ1A, Hφ1B and A pair of second horizontal transfer pulses Hφ2A and Hφ2B are generated, and these pulses are supplied to the solid-state imaging device (1).

  The CCD output obtained from the solid-state imaging device (1) is a predetermined image processing such as a CDS / AGC circuit (5) comprising a sampling unit CDS and a gain control unit AGC, an A / D converter (6), and compression processing. After passing through the image processing circuit (7) for performing the above, it is output to the subsequent circuit. Sampling signals SHP and SHD for sampling the CCD output are supplied from the timing generator (4) to the CDS / AGC circuit (5), and from the timing generator (4) to the A / D converter (6). A sampling signal ADCK for A / D conversion is supplied.

A control circuit (8) is connected to the timing generator (4) and the image processing circuit (7), and a shutter button (9) is connected to the control circuit (8).
The control circuit (8) acquires the image signal (luminance signal) of the effective area of the solid-state imaging device (1) from the image processing circuit (7), detects the signal level of the image signal, and based on the detection result. The exposure time and focus adjustment value are calculated. Then, the operation of the timing generator (4) and a lens driving circuit (not shown) is controlled according to the calculation result.

FIG. 3 shows the configuration of the vertical timing pulse and sub-timing pulse generator of the timing generator (4).
The timing generator includes a horizontal counter (41) that is counted up in synchronization with a drive clock of 24.5454 MHz, and a vertical counter that is counted up in synchronization with a horizontal synchronization pulse HD supplied from the horizontal counter (41). (42) and a field counter (43) counted up in synchronization with the vertical synchronizing pulse VD supplied from the vertical counter (42). The horizontal counter (41) is supplied with the vertical synchronizing pulse VD from the vertical counter (42), and the horizontal synchronizing pulse HD and the vertical synchronizing pulse VD are synchronized.

  A comparator (47) is connected to the three counters (41), (42), and (43), and the comparator (47) stores waveform information about vertical timing pulses and sub-timing pulses. A waveform information storage register (46) is connected.

The three counters (41), (42), and (43) are connected to a maximum value storage register (44). These counters (41), (42) are connected to the maximum value storage register (44). The maximum values Hmax, Vmax, and Fmax to be counted are supplied to (43), respectively.
Further, the vertical counter (42) is connected to a signal generator (SG) (45) for outputting a reference vertical synchronizing signal VDo at a period of 1/30 seconds, and from the control circuit (8) shown in FIG. A controller (48) for controlling the operation of the vertical counter (42) based on a control signal is connected, and the controller (48) has a synchronization state in which a vertical synchronization pulse VD is synchronized with the reference vertical synchronization pulse VDo. A synchronous / asynchronous switching control signal for switching between asynchronous states not to be synchronized is supplied to the vertical counter (42).
The controller 48 has a maximum value Hmax ′ to be counted by the horizontal counter 41 and the vertical counter 42 from the control circuit 8 shown in FIG. 1 when the shutter button 9 is pressed. The maximum value Vmax ′ to be counted is supplied by the controller 48, and the controller 48 supplies the maximum values Hmax ′ and Vmax ′ to the horizontal counter 41 and the vertical counter 42, respectively.

Each time the count value of the horizontal counter (41) is counted up, the count value Hcount is output from the horizontal counter (41) to the comparator (47). When the count value reaches the maximum value Hmax supplied from the maximum value storage register (44) and reaches the maximum value Hmax 'supplied from the controller (48), the horizontal counter (41) The horizontal synchronizing pulse HD is output from the counter to the vertical counter (42) and the comparator (47), the count value is reset to "1", and the count-up is started again from the value "1".
The vertical counter (42) is counted up in synchronization with the horizontal synchronizing pulse HD supplied from the horizontal counter (41) as described above, and the count value Vcount is output from the vertical counter (42) to the comparator (47) each time. Is done. When the count value reaches the maximum value Vmax supplied from the maximum value storage register (44) and when the count value reaches the maximum value Vmax 'supplied from the controller (48), the vertical counter (42). Outputs a vertical sync pulse VD to the comparator (47), horizontal counter (41), and field counter (43), and the count value is reset to "1" and the count up starts again from "1". Be started.
The field counter (43) is counted up in synchronization with the vertical synchronizing pulse VD supplied from the vertical counter (42) as described above, and the count value Fcount is output from the field counter (43) to the comparator (47) each time. Is done. When the count value reaches the maximum value Fmax supplied from the maximum value storage register (44), the count value is reset to "1" and starts counting up again from the value "1". Is done.

  In the comparator (47), the count value Hcount supplied from the horizontal counter (41), the count value Vcount supplied from the vertical counter (42), the count value Fcount supplied from the field counter (43), and waveform information storage The count value included in the waveform information supplied from the register (46) is compared, and the output of the comparator (47) is switched from high to low or from low to high according to the comparison result. At this time, the horizontal synchronization pulse HD supplied from the horizontal counter (41) and the vertical synchronization pulse VD supplied from the vertical counter (42) are synchronized. In this way, a vertical timing pulse and a sub-timing pulse composed of rectangular pulses are generated. The generated sub-timing pulse is output from the timing generator (4) during a period in which the enable signal generated according to the exposure time calculated as described above is high.

In the digital still camera, as in the conventional digital still camera, it is possible to set a monitor mode for displaying a moving image (through image) photographed by the solid-state imaging device (1) on the LCD at a period of 1/30 seconds. .
The operation of the horizontal counter (41) and the vertical counter (42) when the monitor mode is set is the same as the conventional operation shown in FIG. 11, and the maximum value storage is performed from the first line to the 225th line. The maximum value “3532” is supplied from the register (44) to the horizontal counter (41) and the count-up is repeated up to the maximum value. The maximum value “1798” is supplied to the 226th line and the count-up is performed up to the maximum value. The In addition, the maximum value “226” is supplied from the maximum value storing register (44) to the vertical counter (42) and counted up to the maximum value. As a result, the horizontal synchronization pulse HD is output from the horizontal counter (41) with a period of 148 μs. Further, the vertical synchronization pulse VD is output from the vertical counter (42) at a period of 1/30 seconds.

In the digital still camera according to the present invention, the unit for calculating the exposure time is defined as 100 μsec, and when the shutter button (9) is pressed, the time of 1H is changed from 148 μsec to 100 μsec. In addition, the time of 1V is changed to the same time as the exposure time calculated from 1/30 second.
When the shutter button (9) is pressed, the control circuit (8) calculates the exposure time in units of 100 μs, and then calculates the maximum value Vmax ′ to be counted by the vertical counter from the calculated exposure time and 1H time. calculate. For example, the maximum value Vmax ′ is obtained by dividing the calculated exposure time by 100 μsec, which is a time of 1H. Thereafter, the control circuit (8) supplies the calculated maximum value Vmax ′ and the maximum value Hmax ′ “2454” to be counted by the horizontal counter to the timing generator (4). Here, the maximum value Hmax ′ to be counted by the horizontal counter is a value (Hmax′≈100 μsec × 24.5454 MHz) at which the time of 1H becomes 100 μsec.
The controller (48) of the timing generator shown in FIG. 3 supplies the maximum values Hmax ′ and Vmax ′ supplied from the control circuit (8) as described above to the horizontal counter (41) and the vertical counter (43), respectively.

FIG. 5 shows operations of the horizontal counter (41) and the vertical counter (42) when the shutter button (9) is pressed. In the following description, the calculated exposure time is 1000 μs and “10” is supplied from the control circuit (8) to the timing generator (4) as the maximum value Vmax ′ of the vertical counter (42). To do.
The horizontal counter (41) is counted up from the initial value “1” in synchronization with the drive clock, and when the count value reaches the maximum value Hmax ′ “2454” supplied from the controller (48) as shown in the figure, The horizontal synchronization pulse HD is output, the count value is reset to “1”, and the count-up is started again from the value “1”. In this manner, the horizontal counter (41) repeats counting up from “1” to “2454”, and outputs a horizontal synchronization pulse HD every time the count value reaches the maximum value “2454”. On the other hand, the vertical counter (42) is counted up from the initial value “1” in synchronization with the horizontal synchronizing pulse HD. Thereafter, when the count value of the vertical counter (42) reaches the maximum value Vmax ′ “10” supplied from the controller (48), the vertical counter (42) outputs the vertical synchronization pulse VD and count value Is reset to a value of “1”, and count-up is started again from a value of “1”.
In this way, when the shutter button (9) is pressed, the horizontal synchronization pulse HD is output from the horizontal counter (41) at a cycle of 100 μs. Further, the vertical synchronization pulse VD is output from the vertical counter (42) at a period of 1000 μsec which is the same time as the exposure time.

FIG. 6 shows the operation in the monitor mode and the sub-pulse φSUB supplied to the solid-state imaging device (1). In FIG. 6, the shutter pulse is a pulse generated when the shutter button (9) is pressed.
In the digital still camera, the exposure time is controlled by supplying a series of sub-pulses φSUB to the solid-state imaging device (1) in a period excluding the exposure time in one vertical period, and the monitor mode is set. In the state, a series of sub-pulses φSUB is supplied to the solid-state imaging device (1) in one vertical period, and the charge accumulated in the pixel (11) is swept away, and then the imaging surface is exposed to the next vertical period. In addition, the charges accumulated in the pixels (11) by the exposure are transferred, and a process for creating a display image to be displayed on the LCD from the transferred charges (display process) is performed. Then, in the next vertical period, the created display image is displayed on the LCD. By repeating this series of operations, that is, exposure, transfer, display image creation and display, with a shift of one vertical period, an image is taken at a period of 1/30 seconds and displayed on the LCD.
In addition, the calculation of the exposure time and the focus adjustment value is started based on the image signal obtained by the transfer in each vertical period, and the calculation is continuously performed in the next vertical period, and the exposure obtained by the calculation is obtained. Time and focus adjustment values are set.

When the shutter button (9) is pressed while the monitor mode is set, the maximum value Vmax ′ of the vertical counter (42) is calculated from the exposure time obtained in the vertical period at that time, and the maximum The value Vmax ′ and the maximum value Hmax ′ of the horizontal counter (41) are set, and in synchronization with the next vertical synchronization pulse VD, the sub-pulse φSUB is supplied to the solid-state imaging device (1) and accumulated in the pixel (11). The charged charges are swept away and the final exposure of the imaging surface is started.
Thereafter, when the same time as the exposure time elapses, the vertical synchronization pulse VD is output from the timing generator (4), the all-pixel capture mode is set in synchronization with the vertical synchronization pulse VD, and the imaging surface Are transferred in a plurality of fields, and an image signal obtained by the transfer is recorded on a recording medium. At this time, the last image displayed in the monitor mode is continuously displayed on the LCD.

FIG. 4 shows an exposure control procedure executed by the control circuit (8) shown in FIG. 1 when the monitor mode is set.
In the state where the monitor mode is set, as shown in the figure, first, after calculating the exposure time in step S1, it is determined in step S2 whether or not the shutter button (9) has been pressed, and it is determined to be no. In this case, the process proceeds to step S3, where the timing generator (4) executes the sub-timing pulse supply operation for the vertical transfer driving circuit (2), and then the process returns to step S1 to repeat the above procedure. In the state where the procedure is repeated, the horizontal counter (41) of the timing generator (4) repeats counting up to the maximum value Hmax supplied from the maximum value storing register (44) and repeats the horizontal in a cycle of 148 μs. In addition to outputting the synchronization pulse HD, the vertical counter (42) repeats counting up to the maximum value Vmax supplied from the maximum value storage register (44) and outputs the vertical synchronization pulse VD at a period of 1/30 seconds. . In step S3, the sub-timing pulse supply operation is started in synchronization with the vertical synchronizing pulse VD, and the sub-timing pulse is supplied to the solid-state imaging device (1) at the cycle of the horizontal synchronizing pulse HD.

  If the shutter button (9) is pressed while the above procedure is repeated, it is determined as YES in step S2, and the process proceeds to step S4. From the calculated exposure time and horizontal sync pulse period, the vertical counter (42 Then, the maximum value Vmax 'and the maximum value Hmax' of the horizontal counter (41) are supplied to the timing generator (4), and the procedure is terminated. As a result, the horizontal counter (41) of the timing generator (4) repeats counting up to the maximum value Hmax ′ and outputs a horizontal synchronization pulse HD at a cycle of 100 μs, and the vertical counter (42) Counting up to the value Vmax ′ and outputting the vertical synchronization pulse VD with the same cycle as the calculated exposure time. Then, the all-pixel capture mode is set in synchronization with the vertical synchronization pulse VD, and after the charges of all the pixels are read from the solid-state imaging device (1), the monitor mode is set again.

In the digital still camera according to the present invention, as shown in FIG. 6, when the shutter button (9) is pressed, the final exposure of the imaging surface is started in synchronization with the vertical synchronization pulse VD. Shooting from when the shutter button (9) is pressed until image recording is completed, as compared with a conventional digital still camera that performs final exposure of the imaging surface after supplying a series of sub-pulses φSUB in synchronization with the vertical synchronization pulse VD Time is shortened.
Also, by changing the time of 1H to 100 μs when the shutter button (9) is pressed, the unit is different from the 148 μs, which is the cycle in which the charge of the horizontal register (13) is output in the monitor mode. Can control the time of final exposure.
Furthermore, since only one sub-pulse is supplied to the solid-state imaging device (1) when the shutter button (9) is pressed, the number of sub-pulse outputs is reduced compared to a conventional digital still camera that supplies a series of sub-pulses. As a result, power consumption is reduced.

In addition, each part structure of this invention is not restricted to the said embodiment, A various deformation | transformation is possible within the technical scope as described in a claim.
For example, as shown in FIG. 7, when the shutter button (9) is pressed, the horizontal counter (41) and the vertical counter (42) are reset, so that the vertical synchronization pulse VD output from the vertical counter (42) is obtained. In synchronism, it is possible to supply the sub-pulse φSUB to the solid-state imaging device (1) and to start the final exposure of the imaging surface. In such a configuration, the maximum value Vmax ′ of the vertical counter (42) is calculated from the exposure time obtained when the shutter button (9) is pressed, and the maximum value Vmax ′ is obtained in the vertical period in which the final exposure is performed. The maximum value Hmax ′ of the horizontal counter (41) is set.
In the above embodiment, the time of 1H is changed to 100 μsec when the shutter button (9) is pressed. However, the time is not limited to 100 μsec and can be changed to an arbitrary time. .
Further, in the above embodiment, when the shutter button (9) is pressed, the maximum value Hmax ′ of the horizontal counter (41) is fixed to “2454” and the maximum value Vmax ′ of the vertical counter (42) is calculated. The maximum value Vmax ′ of the vertical counter (42) is fixed and the maximum value Hmax ′ of the horizontal counter (41) is changed according to the calculated exposure time. Is possible. The maximum value Hmax ′ of the horizontal counter (41) is obtained, for example, by dividing the calculated exposure time by the maximum value Vmax ′ of the vertical counter and multiplying the result by the driving frequency of the solid-state imaging device (1).
Furthermore, in the above-described embodiment, the present invention is implemented in a digital still camera including the six-phase drive type solid-state image pickup device (1) shown in FIG. It can also be implemented in a digital still camera including a four-phase drive type solid-state imaging device.

It is a block diagram showing the structure of the digital still camera which implemented this invention. It is a block diagram showing the structure of a solid-state image sensor. It is a block diagram showing the structure of the timing generator of the said digital still camera. It is a flowchart showing the exposure control procedure performed in the monitor mode of the said digital still camera. It is a time chart showing the operation of the vertical counter and horizontal counter of the timing generator. It is a time chart showing the operation at the time of pressing the shutter button of the digital still camera. It is a time chart showing the operation | movement at the time of pressing the shutter button of the digital still camera of another Example. It is a block diagram showing the structure of the conventional digital still camera. It is a block diagram showing the structure of the timing generator of the said digital still camera. It is a time chart showing the operation at the time of pressing the shutter button of the digital still camera. It is a time chart showing the operation of the vertical counter and horizontal counter of the timing generator.

Explanation of symbols

(1) Solid-state image sensor
(11) Pixel
(12) Vertical register
(13) Horizontal register
(2) Vertical transfer drive circuit
(3) Horizontal transfer drive circuit
(4) Timing generator
(41) Horizontal counter
(42) Vertical counter
(43) Field counter
(48) Controller
(5) CDS / AGC circuit
(6) A / D converter
(7) Image processing circuit
(8) Control circuit
(9) Shutter button

Claims (3)

A solid-state imaging device having an imaging surface composed of a plurality of pixels, a driving device that drives the solid-state imaging device, and a control device that controls the operation of the driving device, the driving device generating a synchronization signal An imaging apparatus comprising: a synchronization signal generating circuit; and a sub-pulse supply circuit that supplies a sub-pulse for sweeping out charge accumulated in a pixel to the outside. The imaging device includes a series of sub-pulses applied to the solid-state image sensor. In the photographing apparatus capable of setting a photographing mode in which an exposure operation for performing exposure of the imaging surface after supply is started in synchronization with a synchronization signal generated at a constant cycle from the synchronization signal generation circuit, the control device includes: When an image shooting operation is performed with the shooting mode set, exposure of the imaging surface is started in synchronization with a synchronization signal generated from the synchronization signal generation circuit. In both cases, the period of the synchronization signal is set to the same time as the exposure time of the imaging surface, and then an imaging operation including reading of charges from the solid-state imaging device is started in synchronization with the synchronization signal generated from the synchronization signal generation circuit. comprising a control means for,
The driving device includes a horizontal synchronization signal generation circuit that generates a horizontal synchronization signal, and the synchronization signal generation circuit generates a vertical synchronization signal and is counted up in synchronization with the horizontal synchronization signal, A synchronization signal is generated when the count value reaches a value supplied from the outside, and the horizontal synchronization signal generation circuit changes the period of the horizontal synchronization signal in response to the image photographing operation. Then, the control means of the control device calculates a value to be supplied to the synchronization signal generation circuit based on the exposure time and the cycle of the changed horizontal synchronization signal, and supplies the calculated value to the synchronization signal generation circuit. An imaging device, characterized by being supplied .   The control device includes an exposure time deriving unit that derives an exposure time according to the magnitude of incident light on the solid-state imaging device, and the control unit determines the period of the synchronization signal from the exposure time deriving unit. The photographing apparatus according to claim 1, wherein the photographing apparatus is set to the same time as the obtained exposure time. It said control means of the control device, imaging device according to claim 1 or claim 2 for supplying sub-pulses from the drive unit at the start of the exposure of the imaging surface in the solid-state imaging device.

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