JP4730530B2 - Imaging device - Google Patents

Description

  The present invention relates to a photographing apparatus such as a digital still camera provided with a solid-state imaging device composed of a CCD or the like.

In recent years, digital still cameras having a solid-state imaging device composed of a CCD or the like have become popular.
FIG. 2 shows a configuration of an interline transfer type solid-state imaging device (1) used in a digital still camera. In the solid-state imaging device (1), a color filter array is provided on a plurality of photosensors arranged in a matrix to form an imaging surface composed of a plurality of pixels (11), and a plurality of pixels arranged in the vertical direction. A plurality of vertical registers (12) for transferring the charges of the pixels (11) in the column in the vertical direction, and a horizontal register (13) for outputting the charges transferred by these vertical registers (12) in a cycle of one horizontal period; Is provided.

The solid-state imaging device (1) has an input terminal 8 for a first vertical transfer pulse Vφ1 having a first phase, an input terminal 7 for a second vertical transfer pulse Vφ2 having a second phase, and a third phase. A pair of third vertical transfer pulses Vφ3A and Vφ3B, input terminals 6 and 5, an input terminal 4 of a fourth vertical transfer pulse Vφ4 having a fourth phase, and a pair of fifth vertical transfer pulses Vφ5A and Vφ5B having a fifth phase Input terminals 3 and 2 and an input terminal 1 for a sixth vertical transfer pulse Vφ6 having a sixth phase. By supplying each vertical transfer pulse to these input terminals, the electric charge accumulated in the vertical register (12) is transferred to the horizontal register (13).
The solid-state imaging device (1) includes a pair of first horizontal transfer pulses Hφ1A and Hφ1B input terminals 21 and 16 and a pair of second horizontal transfer pulses Hφ2A obtained by inverting the first horizontal transfer pulse, respectively. Hφ2B input terminals 22 and 17 are provided. By supplying each horizontal transfer pulse to these input terminals, the charges transferred from the vertical register (12) to the horizontal register (13) are output to the outside.
Further, the solid-state imaging device (1) is provided with an input terminal 19 for a sub-pulse φSUB for executing an electronic shutter operation for sweeping out charges accumulated in the pixels before exposure on the imaging surface.
The vertical transfer pulse, horizontal transfer pulse, and sub pulse are rectangular pulses.

In the above digital still camera, it is possible to set a monitor mode for displaying a moving image (through image) photographed by the solid-state imaging device (1) on the LCD at a cycle of 1/30 seconds. FIG. The sub-pulse φSUB supplied to the operation and the solid-state imaging device (1) is shown. In FIG. 7, VD is a vertical synchronization pulse.
In the digital still camera, the exposure time is controlled by supplying the sub-pulse φSUB to the solid-state imaging device (1) in a period excluding the exposure time in one vertical period, and when the monitor mode is set, In one vertical period (# V1), a series of sub-pulses φSUB is supplied to the solid-state imaging device (1) and the charges accumulated in the pixels (11) are swept away, and then the imaging surface is exposed for a predetermined time. It is. Next, in the second vertical period (# V2), the charge accumulated in the pixel (11) is transferred by the exposure performed in the first vertical period, and the exposure is performed based on the image signal obtained thereby. Time is calculated. Further, after a series of sub-pulses φSUB is supplied to the solid-state imaging device (1) and the charges accumulated in the pixels are swept away, the imaging surface is exposed for a predetermined time.

Subsequently, in the third vertical period (# V3), an image obtained by the exposure performed in the first vertical period is displayed on the LCD. Further, the charge accumulated in the pixel (11) is transferred by the exposure performed within the second vertical period, and the exposure time is calculated based on the image signal obtained thereby. Further, after a series of sub-pulses φSUB is supplied to the solid-state imaging device (1) and the charges accumulated in the pixels (11) are swept away, the exposure of the imaging surface is performed for the exposure time calculated within the second vertical period. Done.
Next, in the fourth vertical period (# V4), an image obtained by the exposure performed in the second vertical period is displayed on the LCD. Further, the charge accumulated in the pixel (11) is transferred by the exposure performed within the third vertical period, and the exposure time is calculated based on the image signal obtained thereby. Further, after a series of sub-pulses φSUB is supplied to the solid-state imaging device (1) and the charges accumulated in the pixels (11) are swept away, the exposure of the imaging surface is performed for the exposure time calculated within the third vertical period. Done. Similarly, exposure of the imaging surface, transfer of charge, calculation of exposure time, and display on the LCD are performed in parallel in one vertical period.
As described above, in the monitor mode, an operation for exposing the imaging surface after supplying a series of sub-pulses to the solid-state imaging device (1) and sweeping the charges accumulated in the pixels to the outside in a cycle of one vertical period. Are repeated, and images obtained thereby are sequentially displayed on the LCD.

An electronic iris control circuit for a video camera that adjusts the shutter speed based on information of one vertical scanning period from the CCD has been proposed (see Patent Document 1).
JP-A-4-32380 [H04N 5/335]

However, in the conventional digital still camera, since the sub-pulse φSUB is supplied to the solid-state imaging device (1) in a short cycle of one horizontal period (1H) as shown in FIG. There was a problem.
An object of the present invention is to provide a photographing apparatus such as a digital still camera that can reduce power consumption as compared with the conventional art.

  Therefore, as a result of intensive studies to solve the above problems, the present inventor has paid attention to the fact that the charge does not overflow from the pixel if the sub-pulse period is equal to or shorter than the calculated exposure time. It came to.

  An imaging apparatus according to the present invention includes a solid-state imaging device having an imaging surface composed of a plurality of pixels, a driving device that drives the solid-state imaging device, and a control device that controls the operation of the driving device. The apparatus includes an exposure time deriving circuit for deriving an exposure time according to the magnitude of incident light on the solid-state image sensor, and supplies a series of sub-pulses from the driving device to the solid-state image sensor and accumulates them in a pixel. The operation of exposing the imaging surface is repeated periodically for the exposure time obtained from the exposure time deriving circuit after sweeping out the generated charges to the outside. The control device includes a control circuit that changes a pulse interval of at least a part of a series of sub-pulses in one cycle according to the exposure time obtained from the exposure time deriving circuit.

Specifically, the control circuit of the control device is:
Defining means in which the period of the sub-pulse is defined;
Determining means for determining whether the exposure time derived by the exposure time deriving circuit exceeds a period defined in the defining means;
When the derived exposure time exceeds a prescribed sub-pulse period, at least one sub-pulse period of a series of sub-pulses in one period is longer than the prescribed period and not more than the derived exposure time period. And control means for changing to.

  In the imaging apparatus according to the present invention, when the derived exposure time exceeds a specified period of subpulses, for example, one horizontal period, at least one subpulse period of a series of subpulses in one period is the specified period. Longer than the above-described derived exposure time. In this way, when the exposure time exceeds the specified period, the period of at least one sub-pulse is changed to a period longer than the specified period, so even if the exposure time exceeds the specified period, the specified period is always set. As compared with the conventional digital still camera to which the sub-pulse is supplied, the number of times the sub-pulse is output is reduced, and as a result, power consumption is reduced. Further, since the cycle after the change is a cycle equal to or shorter than the derived exposure time, the charge does not overflow from the pixel.

  Further, specifically, the control means derives the number of subpulses to be thinned out from a plurality of subpulses of a specified period based on the exposure time when the derived exposure time exceeds a specified period of the subpulse, The derived thinning-out number is supplied to the driving device, and the driving device supplies a series of subpulses obtained by thinning out the thinning-out number of subpulses supplied from the control means to a plurality of subpulses having a predetermined period to the solid-state imaging device. .

  In the specific configuration described above, the sub-pulse period is changed by thinning out the sub-pulses corresponding to the exposure time from a plurality of sub-pulses having a specified period.

  According to the photographing apparatus of the present invention, power consumption can be reduced by reducing the number of sub-pulse outputs as described above.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments in which the present invention is implemented in a digital still camera having a solid-state imaging device composed of a CCD will be specifically described below with reference to the drawings. An “electronic shutter pulse” may be used as another name for the following “sub-pulse” and “sub-timing pulse”.
The digital still camera according to the present invention includes a solid-state imaging device (1) shown in FIG. 2, and the solid-state imaging device (1) has an input terminal 8 for a first vertical transfer pulse Vφ1 having a first phase. , An input terminal 7 of a second vertical transfer pulse Vφ2 having a second phase, a pair of third vertical transfer pulses Vφ3A and Vφ3B having a third phase, input terminals 6 and 5, a fourth vertical having a fourth phase. There are provided an input terminal 4 for the transfer pulse Vφ4, a pair of fifth vertical transfer pulses Vφ5A and Vφ5B having the fifth phase 3, 2 and an input terminal 1 for the sixth vertical transfer pulse Vφ6 having the sixth phase. It has been. By supplying each vertical transfer pulse to these input terminals, the electric charge accumulated in the vertical register (12) is transferred to the horizontal register (13).
The solid-state imaging device (1) includes a pair of first horizontal transfer pulses Hφ1A and Hφ1B input terminals 21 and 16 and a pair of second horizontal transfer pulses Hφ2A and Hφ2B formed by inverting the first horizontal transfer pulse. Input terminals 22 and 17 are provided. By supplying each horizontal transfer pulse to these input terminals, the charges transferred from the vertical register (12) to the horizontal register (13) are output to the outside.
Further, the solid-state imaging device (1) is provided with an input terminal 19 for a sub-pulse φSUB for executing an electronic shutter operation for sweeping out charges accumulated in the pixels before exposure on the imaging surface.

FIG. 1 shows the configuration of a digital still camera according to the present invention. A vertical transfer drive circuit (2) and a horizontal transfer drive circuit (3) are connected to the solid-state imaging device (1), and the first vertical transfer pulse Vφ1 and the second transfer pulse from the vertical transfer drive circuit (2). A vertical transfer pulse Vφ2, a pair of third vertical transfer pulses Vφ3A, Vφ3B, a fourth vertical transfer pulse Vφ4, a pair of fifth vertical transfer pulses Vφ5A, Vφ5B, a sixth vertical transfer pulse Vφ6, and a sub-pulse φSUB are supplied. A pair of first horizontal transfer pulses Hφ1A and Hφ1B and second horizontal transfer pulses Hφ2A and Hφ2B are supplied from the transfer drive circuit (3).
A timing generator (TG) (4) is connected to the vertical transfer driving circuit (2) and the horizontal transfer driving circuit (3), and a first vertical signal is transferred from the timing generator (4) to the vertical transfer driving circuit (2). A timing pulse, a second vertical timing pulse, a pair of third vertical timing pulses, a fourth vertical timing pulse, a pair of fifth vertical timing pulses, a sixth vertical timing pulse, a sub-timing pulse, and a charge readout pulse are supplied. A pair of horizontal timing pulses and a pair of second horizontal timing pulses are supplied from the timing generator (4) to the horizontal transfer driving circuit (3).

  In the timing generator (4), using a counter (not shown), a first vertical timing pulse, a second vertical timing pulse, a pair of third vertical timing pulses, a fourth vertical timing pulse, a pair of fifth vertical timing pulses, a sub Timing pulses and charge readout pulses are generated, and these pulses are supplied to the vertical transfer drive circuit (2). In addition, a pair of first horizontal timing pulses and a pair of second horizontal timing pulses are generated using the driving clock, and these pulses are supplied to the horizontal transfer driving circuit (3).

  In the vertical transfer driving circuit (2), the first to sixth vertical transfer pulses Vφ1, Vφ2, Vφ3A, Vφ3B, Vφ4, Vφ5A from the charge readout pulse obtained from the timing generator (4) and the first to sixth vertical timing pulses, Vφ5B and Vφ6 are created and the sub-timing pulse is amplified by amplifying the sub-timing pulse, and the created pulse is supplied to the solid-state imaging device (1). On the other hand, the horizontal transfer driving circuit (3) amplifies the pair of first horizontal timing pulses and the pair of second horizontal timing pulses obtained from the timing generator (4) to thereby generate a pair of first horizontal transfer pulses Hφ1A, Hφ1B and A pair of second horizontal transfer pulses Hφ2A and Hφ2B are generated, and these pulses are supplied to the solid-state imaging device (1).

  The CCD output obtained from the solid-state imaging device (1) is a predetermined image processing such as a CDS / AGC circuit (5) comprising a sampling unit CDS and a gain control unit AGC, an A / D converter (6), and compression processing. After passing through the image processing circuit (7) for performing the above, it is output to the subsequent circuit. Sampling signals SHP and SHD for sampling the CCD output are supplied from the timing generator (4) to the CDS / AGC circuit (5), and from the timing generator (4) to the A / D converter (6). A sampling signal ADCK for A / D conversion is supplied.

A control circuit (8) is connected to the timing generator (4) and the image processing circuit (7), and a shutter button (9) is connected to the control circuit (8).
The control circuit (8) acquires the image signal (luminance signal) of the effective area of the solid-state imaging device (1) from the image processing circuit (7), detects the signal level of the image signal, and detects the detected signal level. Compare with a reference value indicating the signal level for optimal exposure. Then, after calculating the exposure time based on the comparison result between the signal level and the reference value, the operation of the timing generator (4) is controlled according to the calculation result.

  As in the conventional digital still camera, the digital still camera can be set in the monitor mode. In the monitor mode, as shown in FIG. The operation of exposing the imaging surface after the charges supplied to (1) and accumulated in the pixels are swept out to the outside is repeated, and images obtained thereby are sequentially displayed on the LCD. In each vertical period, exposure of the imaging surface, transfer of pixels, calculation of exposure time, and display on the LCD are performed in parallel.

In the monitor mode of the digital still camera according to the present invention, when the calculated exposure time is one horizontal period (1H), the sub-pulses are solid-state image sensors (1 In the case where the calculated exposure time exceeds one horizontal period, the sub-pulses are supplied in the next vertical period with the same period as the exposure time longer than one horizontal period (1). ).
The control circuit (8) shown in FIG. 1 determines whether or not the exposure time calculated as described above is a prescribed period of a sub-pulse stored in a built-in memory (not shown), that is, one horizontal period. When the time is one horizontal period, according to the exposure time, the count value of the counter at the output start time of the sub-timing pulse, the count value at the output end time, and the number of output of the sub-timing pulse, It is set in a register (not shown) constituting the timing generator (4).
On the other hand, when the calculated exposure time exceeds one horizontal period, the count value of the counter at the output start time of the sub-timing pulse, the count value at the output end time, and the sub value according to the exposure time. The number of output timing pulses is set in the register of the timing generator (4), the number of subpulses to be continuously thinned out from a plurality of subpulses of a specified period is calculated based on the exposure time, and the calculation result is Set to register.

FIG. 4 shows the operation of the timing generator (4) when the exposure time calculated by the control circuit (8) is one horizontal period. In FIG. 4, VD is a vertical synchronization pulse, and HD is a horizontal synchronization pulse.
The timing generator (4) creates an enable signal based on the two count values set in the register as described above, and outputs a sub-timing pulse to the vertical transfer drive circuit (2) while the enable signal is high. When the calculated exposure time (= 1H) has elapsed since the last sub-timing pulse was output, a charge readout pulse is output to the vertical transfer drive circuit (2). In this way, the sub-timing pulse is supplied from the timing generator (4) to the vertical transfer driving circuit (2) in a period of one horizontal period in one vertical period excluding the calculated exposure time. It will be. Note that the sub-timing pulse output operation in the above case where the calculated exposure time is one horizontal period is the same as the conventional one.
In response to this, the vertical transfer drive circuit (2) amplifies the sub-timing pulse to generate a sub-pulse φSUB and supplies it to the solid-state imaging device (1). In this manner, as shown in FIG. 8, sub-pulses are supplied to the solid-state imaging device (1) in a period of one horizontal period in a period excluding the calculated exposure time in one vertical period.

In contrast, FIG. 5 shows the operation of the timing generator (4) when the exposure time calculated by the control circuit (8) exceeds one horizontal period. In FIG. 5, VD is a vertical synchronization pulse, and HD is a horizontal synchronization pulse.
The timing generator (4) creates an enable signal based on the two count values set in the register as described above and the number of thinning out, and outputs the sub-timing pulse to the vertical transfer drive circuit (2) while the enable signal is high. ) And when the calculated exposure time has elapsed since the last sub-timing pulse was output, a charge readout pulse is output to the vertical transfer drive circuit (2). In this way, the sub-timing pulse is supplied from the timing generator (4) to the vertical transfer driving circuit (2) in the same period as the exposure time in one vertical period excluding the calculated exposure time. Will be. For example, when the calculated exposure time is two horizontal periods, the sub-timing pulse is supplied to the vertical transfer driving circuit (2) with a period of two horizontal periods.
In response to this, the vertical transfer drive circuit (2) amplifies the sub-timing pulse to generate a sub-pulse φSUB and supplies it to the solid-state imaging device (1). In this way, as shown in FIG. 3, sub-pulses are supplied to the solid-state imaging device (1) in one vertical period, excluding the calculated exposure time, with the same period as the exposure time longer than one horizontal period. Will be. Here, since the period of the sub-pulse is set to the same period as the exposure time, the charge does not overflow from the pixel.

FIG. 6 shows a series of operations in the monitor mode of the digital still camera.
First, in step S1, the timing generator (4) outputs a sub-timing pulse to the vertical transfer driving circuit (2) in a period excluding the exposure time calculated as described later in one vertical period, and in response to this, The vertical transfer drive circuit (2) supplies the sub-pulse to the solid-state imaging device (1). As a result, the imaging surface is exposed.
Next, in step S2, the timing generator (4) outputs the vertical timing pulse and the horizontal timing pulse to the vertical transfer driving circuit (2) and the horizontal transfer driving circuit (3), respectively, and in response to this, the vertical transfer driving circuit. (2) supplies the vertical transfer pulse to the solid-state imaging device (1), and the horizontal transfer driving circuit (3) supplies the horizontal transfer pulse to the solid-state imaging device (1). As a result, the charges accumulated in the pixels by exposure are transferred to the horizontal register (13) via the vertical register (12) and output to the outside.

  Subsequently, in step S3, the image processing circuit (7) performs predetermined image processing on a signal obtained from the solid-state imaging device (1) through the CDS / AGC circuit (5) and the A / D converter (6). In step S4, the control circuit (8) acquires the image signal from the image processing circuit (7), compares the signal level of the image signal with the reference value, and determines the exposure time based on the comparison result. Is calculated.

  Next, in step S5, the control circuit (8) determines whether or not it is necessary to thin out subpulses depending on whether or not the calculated exposure time is one horizontal period. Here, if the calculated exposure time is one horizontal period, it is determined NO and the process proceeds to step S8, and the count value and output at the output start time of the sub-timing pulse are output according to the calculated exposure time. After the exposure information including the count value at the end time and the number of sub-timing pulses is set in the timing generator (4), the process returns to step S1. In this case, in step S1, sub-pulses are output from the vertical transfer driving circuit (2) to the solid-state imaging device (1) at a period of one horizontal period.

  On the other hand, when the calculated exposure time exceeds one horizontal period, it is determined as YES in step S5 and the process proceeds to step S6, and the number of sub-pulses to be thinned out is calculated based on the exposure time. Here, as the number of sub-pulses to be thinned out, a value that makes the sub-pulse period the same as the exposure time is calculated by thinning out some sub-pulses from a plurality of sub-pulses in one horizontal period. Subsequently, in step S7, the control circuit (8) sets the calculated number of thinnings in the timing generator (4), and then in step S8, according to the calculated exposure time, the output timing of the sub-timing pulse is started. After setting exposure information including the count value, the count value at the end of output, and the number of sub-timing pulses to be output to the timing generator (4), the process returns to step S1. In this case, in step S1, sub-pulses are output from the vertical transfer driving circuit (2) to the solid-state imaging device (1) at the same cycle as the exposure time longer than one horizontal period.

  In the digital still camera according to the present invention, as described above, when the exposure time calculated in the monitor mode exceeds one horizontal period, the horizontal transfer drive circuit (2) to the solid-state imaging device (1) is one horizontal. Since the sub-pulses are output with a period longer than the period, even if the exposure time exceeds one horizontal period, the sub-pulses are output as compared with the conventional digital still camera in which the sub-pulse is always output with a period of one horizontal period. The number of times decreases, resulting in a reduction in power consumption.

In addition, each part structure of this invention is not restricted to the said embodiment, A various deformation | transformation is possible within the technical scope as described in a claim.
For example, it is possible to change the period of some subpulses in a series of subpulses in one period to a period longer than one horizontal period.
In the above embodiment, when the calculated exposure time exceeds one horizontal period, the sub-pulse period is changed to the same period as the exposure time. However, the period is not limited to the same period as the exposure time. It is possible to change to any cycle longer and less than the exposure time.
Furthermore, the calculation method of the exposure time is not limited to the above method of calculating based on the signal level of the image signal, and other well-known methods can be adopted.
Furthermore, in the above embodiment, the present invention is implemented in a digital still camera provided with the solid-state image pickup device (1) of the six-phase drive system shown in FIG. It can also be implemented in a digital still camera having a solid-state imaging device of a four-phase drive system.

It is a block diagram showing the structure of the digital still camera which implemented this invention. It is a block diagram showing the structure of a solid-state image sensor. It is a time chart showing operation | movement of the vertical transfer drive circuit when exposure time exceeds one horizontal period. It is a time chart showing operation | movement of a timing generator in case exposure time is 1 horizontal period. It is a time chart showing operation | movement of a timing generator when exposure time exceeds one horizontal period. It is a flowchart showing operation | movement of monitor mode. It is a time chart showing the said operation | movement. It is a timing chart showing the operation of the vertical transfer drive circuit when the exposure time is one horizontal period.

Explanation of symbols

(1) Solid-state image sensor
(11) Pixel
(12) Vertical register
(13) Horizontal register
(2) Vertical transfer drive circuit
(3) Horizontal transfer drive circuit
(4) Timing generator
(5) CDS / AGC circuit
(6) A / D converter
(7) Image processing circuit
(8) Control circuit
(9) Shutter button

Claims (3)

An imaging apparatus comprising: a solid-state imaging device having an imaging surface composed of a plurality of pixels; a driving device that drives the solid-state imaging device; and a control device that controls the operation of the driving device. An exposure time deriving circuit for deriving an exposure time according to the magnitude of incident light on the solid-state image sensor, and supplying a series of sub-pulses from the driving device to the solid-state image sensor and accumulating in the pixels In the imaging apparatus in which the operation of exposing the imaging surface for the exposure time obtained from the exposure time deriving circuit after the charge is swept out to the outside is periodically repeated, the control device is configured to expose the exposure obtained from the exposure time deriving circuit. A control circuit that changes a period of a sub pulse to be supplied to the solid-state imaging device according to time, the control circuit includes:
A specifying means in which a specified period of the sub-pulse is specified;
Determining means for determining whether or not the exposure time derived by the exposure time deriving circuit exceeds a prescribed period of the sub-pulse;
When the determination means determines that the derived exposure time exceeds a specified sub-pulse period, the sub-pulse period to be supplied to the solid-state imaging device is longer than the specified period and the derived exposure time. Control means to change to the following cycle
Imaging apparatus characterized in that it comprises and. The control means derives the number of sub-pulses to be thinned out from a plurality of sub-pulses having a prescribed period based on the exposure time when the derived exposure time exceeds a prescribed period of the sub-pulse, and drives the derived thinning-out number to the drive The imaging device according to claim 1 , wherein the driving device supplies a series of sub-pulses obtained by thinning out a number of sub-pulses supplied from the control unit to a solid-state imaging device from a plurality of sub-pulses having a predetermined period. apparatus. The photographing apparatus according to claim 1 , wherein the exposure time deriving circuit of the control device detects a signal level of an output signal of the solid-state imaging device, and derives the exposure time from the detection result.

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