JP4969257B2 - Wiring board and semiconductor device mounting structure using the same - Google Patents

Description

  The present invention relates to a wiring board and a semiconductor element mounting structure using the wiring board.

  2. Description of the Related Art Conventionally, a semiconductor element mounting structure including a semiconductor element such as an IC (Integrated Circuit) or an LSI (Large Scale Integration) and a wiring substrate on which the semiconductor element can be mounted is known.

  As the above-mentioned wiring board, a substrate in which a plurality of insulating layers and conductor layers formed on the insulating layers are stacked in the vertical direction is used in accordance with recent miniaturization of electronic devices.

Note that there are two types of conductor layers, a line-shaped signal line for transmitting a desired electrical signal and a flat ground layer connected to a reference potential, as required (see Patent Document 1 below). .
JP 2003-332746 A

  However, the above-described conventional conductor layer is formed so that the end portion thereof is generally linear and the end portion of the conductor layer is covered with an insulating layer. Therefore, the adhesive strength is weak at the end, and when heat is applied to the conductor layer and the insulating layer in the manufacturing process, the end of the conductor layer is caused by the stress caused by the difference in thermal expansion coefficient between the conductor layer and the insulating layer. There was a problem that it was easily peeled off from the insulating layer. As a result, the conductor layer is thermally deformed in a heating process such as solder reflow, and the wiring board itself is distorted, resulting in an increase in product defects and a decrease in productivity.

  This invention is made | formed in view of the subject mentioned above, Comprising: It suppresses that the edge part of a conductor layer peels from an insulating layer, and it aims at providing the wiring board excellent in productivity.

The wiring board of the present invention includes an insulating layer , a first conductor layer that is a ground layer formed on one main surface of the insulating layer, and a second conductor that is a ground layer formed on the other main surface of the insulating layer. A plurality of concavo-convex portions each having a concave portion and a convex portion in a plan view at the end portion of the first conductor layer and the end portion of the second conductor layer. The concave portion of the first conductor layer and the convex portion of the second conductor layer are arranged so as to correspond to each other through a plane.

  The wiring board according to the present invention is characterized in that the insulating layer is made of polyparaphenylene benzbisoxazole resin.

The wiring board of the present invention, concave portions and convex portions of the first conductive layer, characterized in that it is formed along the outer periphery of the first conductor layer.

In the wiring board according to the present invention, the first conductor layer has an opening formed in a central region, and a second unevenness including a second recess and a second protrusion along an end of the opening. A plurality of the portions are formed continuously. In the wiring board of the present invention, the pitch between the recesses adjacent on the outer periphery of the first conductor layer is the pitch between the second recesses adjacent at the end of the opening of the first conductor layer. It is characterized by being larger than. The wiring board of the present invention is characterized in that the convex portion has a trapezoidal shape in plan view, and the concave portion has an inverted trapezoidal shape in plan view. The wiring board of the present invention further includes a signal line formed on the one main surface of the insulating layer, and an end portion of the first conductor layer adjacent to the signal line is the first conductor layer. The uneven portion is less than the end portion not adjacent to the signal line. The wiring board of the present invention further includes a signal line formed on the one main surface of the insulating layer, and an end portion of the first conductor layer adjacent to the signal line is formed in a straight line, An end portion of the first conductor layer that is not adjacent to the signal line has the uneven portion.

  The semiconductor element mounting structure of the present invention is characterized in that the semiconductor element is connected to the wiring board via a bump.

  According to the present invention, the contact area between the end portion of the conductor layer and the insulating layer can be increased by continuously forming a plurality of concave and convex portions including concave portions and convex portions at the end portion of the conductor layer. And by improving the adhesive force between the end portion of the conductor layer and the insulating layer, peeling of the conductor layer and the insulating layer can be suppressed, deformation of the conductor layer is reduced, and a wiring board and a semiconductor using the same The productivity of the element mounting structure can be improved.

  DESCRIPTION OF EMBODIMENTS Embodiments of a wiring board according to the present invention and a semiconductor element mounting structure using the wiring board will be described below in detail with reference to the drawings. Such a wiring board and a semiconductor element mounting structure using the wiring board are used for electronic devices such as various audiovisual devices, home appliances, communication devices, computer devices, and peripheral devices thereof.

  FIG. 1 is a plan view of a semiconductor element mounting structure according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the semiconductor element mounting structure shown in FIG.

  The semiconductor element mounting structure according to this embodiment includes a wiring board 1 and a rectangular semiconductor element 2 made of, for example, silicon such as an IC or LSI mounted on the wiring board 1. Here, the semiconductor element 2 is mounted on the wiring board 1 via bumps 3 such as solder. The semiconductor element 2 is disposed at the center of the wiring substrate 1 in plan view.

  The wiring substrate 1 includes a core substrate 4, an insulating layer 5 and a conductor layer 6 laminated on the upper and lower surfaces of the core substrate 4.

  The core substrate 4 is formed by, for example, laminating and solidifying a sheet impregnated with a thermosetting resin such as an epoxy resin, a bismaleimide triazine resin, or a cyanate resin on a base material made of glass cloth in which glass fibers are woven vertically and horizontally. Produced.

  Moreover, the core substrate 4 can also be produced from a fiber resin without using a base material. As the fiber resin, for example, low thermal expansion resin such as polyparaphenylene benzbisoxazole resin, wholly aromatic polyamide resin, wholly aromatic polyester resin, polyimide resin or liquid crystal polymer resin can be used. Among these, it is desirable to use a polyparaphenylene benzbisoxazole resin. The polyparaphenylene benzbisoxazole resin has a low coefficient of thermal expansion of −5 ppm / ° C. to 5 ppm / ° C., and the thermal expansion of the core substrate 4 itself can be suppressed by using such a low thermal expansion resin.

  In the core substrate 4, a through hole 8 that penetrates the core substrate 4 in the vertical direction is formed. A through-hole conductor 9 made of conductive copper plating or the like is formed on the inner wall surface of the through-hole 8. The through hole 8 is filled with an insulator 10 made of an insulating resin in order to improve the flatness of the core substrate 4. The through-hole conductor 9 electrically connects the conductor layers 6 formed on the upper surface or the lower surface of the core substrate 4. Further, by filling the through hole 8 with the insulator 10, the via conductor 7 can be formed immediately above or directly below the through hole 8, which contributes to the miniaturization of the wiring board 1.

  The insulating layer 5 disposed on both main surface sides of the core substrate 4 is configured by laminating an adhesive layer 5a and a film layer 5b vertically.

  The adhesive layer 5a is for fixing the film layer 5b to the conductor layer 6, and a thermosetting resin or a thermoplastic resin can be used. As the thermosetting resin, for example, at least one of polyimide resin, acrylic resin, epoxy resin, urethane resin, cyanate resin, silicon resin, and bismaleimide triazine resin can be used. Further, as the thermoplastic resin, since it is necessary to have heat resistance capable of withstanding heating during solder reflow, it is desirable that the softening temperature of the constituent material is 200 ° C. or higher, and polyether ketone resin is used. The thermal expansion coefficient of the adhesive layer 5a made of these materials is, for example, 20 ppm / ° C. to 80 ppm / ° C. In addition, the thermal expansion coefficient in this specification measured the target object which measures a thermal expansion coefficient from the wiring board, and measured the target object with the TMA apparatus (thermomechanical characteristic analyzer).

  In addition, the adhesive layer 5a is laminated to the core substrate 4 and the conductor layer 6 with the film layer 5b bonded together, and is fixed by heating, for example, using a heating press apparatus and then cooling. Is done. The adhesive layer 5a is set so that the thickness after drying is, for example, 1 μm to 10 μm.

  The adhesive layer 5a may contain a spherical nonmetallic inorganic filler. Such a non-metallic inorganic filler is made of an inorganic material such as silica (silicon dioxide) or aluminum oxide. The coefficient of thermal expansion of the nonmetallic inorganic filler is, for example, 0.5 ppm / ° C. to 9 ppm / ° C. Since the thermal expansion coefficient of the nonmetallic inorganic filler is smaller than the thermal expansion coefficient of the adhesive layer 5a, the thermal expansion of the insulating layer 5 can be reduced when the nonmetallic inorganic filler is contained in the adhesive layer 5a.

  The thickness dimension of the film layer 5b is precisely controlled. The film layer 5b has heat resistance and hardness in order to prevent the thickness dimension from being changed by applied temperature or pressure when the core layer 4 or the conductor layer 6 is bonded via the adhesive layer 5a. It is desirable that the material has excellent properties. As the film layer 5b having such characteristics, for example, at least one of polyparaphenylene benzbisoxazole resin, wholly aromatic polyamide resin, wholly aromatic polyester resin, polyimide resin or liquid crystal polymer resin is used. it can. The film layer 5b is desirably a mixed resin of a polyparaphenylene benzbisoxazole resin and a polyimide resin in order to maintain the strength of the film layer 5b. Further, the thickness dimension of the film layer 5b is set to be, for example, 1 μm to 10 μm. The thermal expansion coefficient of the film layer 5b is, for example, from −5 ppm / ° C. to 5 ppm / ° C.

  By using a low thermal expansion resin such as polyparaphenylene benzbisoxazole resin for the film layer 5b, even if heat is applied to the film layer 5b, the film layer 5b is hardly thermally expanded. It is difficult to deform, and problems such as bending of the wiring board 1 can be reduced.

  A via conductor 7 is formed in the insulating layer 5 including the adhesive layer 5a and the film layer 5b. The via conductor 7 is for electrically connecting the conductor layers 6 having different vertical positions, and has conductivity. The via conductor 7 is made of a metal material such as copper, silver, gold, aluminum, nickel, or chromium.

  The conductor layer 6 includes a line-shaped signal line 6 a having a function of transmitting an electric signal and a flat ground layer 6 b having a function of sharing the reference potential of the semiconductor element 2. The signal line 6a and the ground layer 6b are arranged so as to face each other with the insulating layer 5 interposed therebetween. The signal line 6a and the ground layer 6b may be formed on the same plane. Further, the end of the signal line 6 a is electrically connected through the conductor layer 6 and the via conductor 7 having different vertical positions.

  The conductor layer 6 is formed at least on the upper surface or the lower surface of the core substrate 4 and is partially formed on the surface of the core substrate 4. The conductor layer 6 has a portion formed by being sandwiched between the core substrate 4 and the insulating layer 5 or the insulating layers 5. The conductor layer 6 is covered with an adhesive layer 5a. A ground layer 6 b is formed on the surface in contact with the core substrate 4, and a signal line 6 a is formed on the surface on which the semiconductor element 2 of the wiring substrate 1 is mounted. The conductor layer 6 is made of a metal material such as copper, silver, gold, aluminum, nickel, or chromium. The thermal expansion coefficient of the conductor layer 6 made of these materials is, for example, 6 ppm / ° C. to 24 ppm / ° C., and the thermal expansion coefficient is set larger than that of the film layer 5 b.

  The thermal expansion coefficient of the insulating layer 5 is set smaller than the thermal expansion coefficient of the conductor layer 6. The adhesive layer 5a has a coefficient of thermal expansion greater than that of the conductor layer 6, but the thickness dimension of the adhesive layer 5a is smaller than the thickness dimension of the film layer 5b, and the thickness of the adhesive layer 5a constituting the insulating layer 5 with respect to the film layer 5b. By controlling the size ratio to be small, the thermal expansion coefficient of the insulating layer 5 can be made smaller than the thermal expansion coefficient of the conductor layer 6. More specifically, for example, the ratio of the thickness dimension of the film layer 5b made of polyparaphenylene benzbisoxazole resin to the thickness dimension of the adhesive layer 5a made of polyimide resin is 1.0 to 0.1 or more, It can be realized by setting the ratio to less than 1.0 to 1.0.

  Further, an adhesive layer 5 a is formed on one surface of the film layer 5 b, and the contact area between the two is the entire plane of the wiring board 1. Furthermore, since both the film layer 5b and the adhesive layer 5a are made of resin, the adhesive force between them is strong.

  The film layer 5b is not easily deformed by heat, and the adhesive layer 5a that is in contact with the film layer 5b is firmly adhered to one surface of the film layer 5b, whereby the thermal expansion of the adhesive layer 5a can be suppressed. Further, as described above, the adhesive layer 5a can be further prevented from thermal expansion by making the thickness dimension of the adhesive layer 5a smaller than the thickness dimension of the film layer 5b. As a result, it is possible to prevent the adhesive layer 5a from peeling from the conductor layer 6 by making the adhesive layer 5a difficult to thermally expand.

  In recent years, due to the stress caused by the difference between the thermal expansion coefficient of the semiconductor element 2 made of silicon and the thermal expansion coefficient of the wiring board 1, the semiconductor element 2 is easily peeled off from the wiring board 1, and the mounting reliability of the semiconductor element 2 is improved. Corresponding to the finding of a tendency to decrease, the reduction of the thermal expansion of the wiring board 1 has been studied. Therefore, the insulating layer 5 constituting the wiring board 1 also tends to employ a resin having a low thermal expansion. When a resin having a low thermal expansion is used for the insulating layer 5, the contraction of the conductor layer 6 may be larger than that of the insulating layer 5 during cooling from a temperature of about 200 ° C. at which the resin of the insulating layer 5 is cured. The end of the layer 6b tends to peel from the insulating layer 5.

  FIG. 3 or FIG. 4 is a plan view of the ground layer 6b, and both show layers having different vertical positions. In FIG. 3 or FIG. 4, only the ground layer 6b is shown, and the signal line 6a is omitted. As shown in FIG. 3 or FIG. 4, the ground layer 6b, which is a flat conductor layer, has a plurality of concavo-convex portions 16 each including a concave portion 11 and a convex portion 12 in a plan view. Has been.

  The uneven part 16 is formed along at least one side of the wiring board 1. The recess 11 and the protrusion 12 are preferably formed so as to meander continuously in order to reduce the concentration of stress applied to the end A thereof.

  By forming the concave portion 11 and the convex portion 12 to meander continuously, the contact area between the ground layer 6b and the adhesive layer 5a can be increased, and the end A of the ground layer 6b and the adhesive layer 5a Can be effectively improved to effectively prevent peeling between the end A of the ground layer 6b and the adhesive layer 5a.

  Further, by setting the pitch W between the adjacent recesses 11 to be equal, even if heat is applied to the conductor layer and the insulating layer in the manufacturing process, the gap between the end A of the ground layer 6b and the adhesive layer 5a. Can be evenly distributed, and peeling between the end A of the ground layer 6b and the adhesive layer 5a can be effectively suppressed.

  As described above, the contact area between the adhesive layer 5a and the end portion A of the ground layer 6b is formed by continuously forming a plurality of concave and convex portions 16 including the concave portions 11 and the convex portions 12 at the end portion A of the ground layer 6b. Can be increased, and the adhesive force between the adhesive layer 5a and the ground layer 6b can be improved. As a result, even when heat is applied to the ground layer 6b and the ground layer 6b tends to contract, the concave portion 11 and the convex portion 12 at the end A of the ground layer 6b are fixed to the adhesive layer 5a. It is possible to suppress the peeling of 6b from the adhesive layer 5a, and it is possible to manufacture a wiring substrate 1 having excellent productivity and a semiconductor element mounting structure using the wiring substrate 1.

  FIG. 5 is a transmission plan view in which two layers of the ground layer 6b are stacked one above the other. The lower ground layer 6b is indicated by a dotted line.

  Further, as shown in FIG. 5, the end portion A of the ground layer 6b is disposed so that the concave portion 11 and the convex portion 12 of the different layers (first conductor layer and second conductor layer) correspond to each other through a plane. Yes. The shape of the concave portion 11 and the convex portion 12 at the end of the ground layer 6b is different between the stacked ground layers 6b in different vertical positions, so that the ground layer 6b transmitted from the ground layer 6b to the insulating layer 5 The contracting force can be distributed without being concentrated at a certain point. As a result, peeling of the ground layer 6b from the adhesive layer 5a can be suppressed, and shrinkage of the ground layer 6b can be reduced.

  In addition, when the signal line 6a and the ground layer 6b are formed on the same plane, it is desirable that a concave portion and a convex portion are not formed at the end A of the ground layer 6b adjacent to the signal line 6a. That is, it is desirable that the end A of the ground layer 6b along the signal line 6a is formed in a straight line with little unevenness. When transmitting a high-frequency electrical signal to the signal line 6a, if the end A of the adjacent ground layer 6b has irregularities, a phenomenon may occur in which noise occurs in the signal line 6a when a current flows through the irregularities. . For this reason, unevenness is not formed on the end A of the ground layer 6b adjacent to the signal line 6a.

  The ground layer 6b has an opening 13 in the central region. The opening 13 is formed at a location overlapping the semiconductor element 2 in plan view. The semiconductor element 2 mounted on the wiring board 1 is disposed so as to be accommodated in the opening 13 in plan view. A ground layer 6b is disposed around the semiconductor element 2 so as to surround the semiconductor element 2, and irregularities are continuously formed at the end A of the ground layer 6b. As a result, the ground layer 6b is formed on the entire wiring board 1 in plan view, and the unevenness is formed on the end A thereof, whereby distortion of the entire wiring board 1 can be reduced.

  The ground layer 6 b is continuously formed along the end B of the opening 13 with the second uneven portion 17 including the second concave portion 14 and the second convex portion 15. As described above, the contact area between the ground layer 6b and the adhesive layer 5a is formed by forming irregularities at the end B of the opening 13 along the outer periphery of the semiconductor element 2 mounted on the wiring board 1 in plan view. , The separation between the ground layer 6b and the adhesive layer 5a can be suppressed, and the shrinkage of the ground layer 6b when heat is applied to the ground layer 6b can be suppressed.

  The boundary BD1 between the concave portion 11 and the convex portion 12 will be described with reference to FIG. As shown in FIG. 3, a tangent line connecting the apexes (P1 and Q1) of the adjacent convex portions 12 is X1, and a tangent line connecting the apexes (P2 and Q2) of the adjacent concave portions 11 is X2. The boundary BD1 is between X1 and X2 and is on a line equidistant from X1 and X2.

  The end A of the ground layer 6b can have various shapes. For example, as shown in FIG. 6A, a trapezoidal convex portion 12a in a plan view and an inverted trapezoidal concave portion 11a in a plan view may be formed continuously. The length of the upper base L1 of the convex portion 12a is set to be 80 μm to 120 μm. Also, the length of the upper base L2 of the recess 11a is set to be 80 μm to 120 μm, similarly to L1. The boundary BD2 between the convex portion 12a and the concave portion 11a in this case will be described. The side along the concave portion 11a is X3, and the side along the convex portion 12a is X4. The boundary BD2 is on a line between X3 and X4 and equidistant from X3 and X4.

  Further, as shown in FIG. 6B, the end A of the ground layer 6b may be formed by discontinuously forming a semicircular protrusion 18. The radius R of the semicircular protrusion 18 is set to be 20 μm to 30 μm. In other words, the convex portion 12b of the ground layer 6b has an arc shape a at the end thereof, and the concave portion 11b of the ground layer 6b has an arc shape b, a straight line c, and an arc d continuous at the end portion. May be combined. The boundary BD3 between the convex portion 12b and the concave portion 11b in this case will be described. The side along the concave portion 11b is X5, and the tangent line connecting the apexes (P3 and Q4) of the adjacent convex portion 12b is X6. The boundary BD3 is on a line between X5 and X6 and equidistant from X5 and X6.

  The end A of the ground layer 6b is not limited to the trapezoidal shape or the semicircular shape as described above, and may be a triangular shape, a rectangular shape, a polygonal shape, or the like.

  The wiring board 1 according to this embodiment is manufactured through the following steps, for example.

  First, the core substrate 4 is prepared. The core substrate 4 is formed by hot pressing a sheet of glass cloth in which glass fibers are woven vertically and horizontally and impregnated with a thermosetting resin such as an epoxy resin and a bismaleimide triazine resin or a cyanate resin together with a copper foil. . Further, in order to reduce the thermal expansion of the wiring board 1, a low thermal expansion fiber such as wholly aromatic polyamide, wholly aromatic polyester, or liquid crystal polymer may be used. The core substrate 4 has a thickness dimension set to, for example, 0.3 mm or more and 1.5 mm or less.

  Next, a through hole 8 is formed in the thickness direction in the core substrate 4 by a known drilling process, and a through hole conductor 9 is formed on the inner peripheral surface of the through hole 8 by electrolytic plating or the like. A plurality of through holes 8 are formed, and the diameter is set to, for example, 0.1 mm or more and 1 mm or less. Thereafter, a resin such as polyimide is filled in the through hole 8 to form the insulator 10. Next, the material constituting the conductor layer 6 is deposited on the upper and lower surfaces of the core substrate 4 by a conventionally known vapor deposition method, CVD method, sputtering method, or the like. Then, a resist is applied to the surface, and after exposure and development, an etching process is performed to form a ground layer 6b (first conductor layer) on the upper and lower surfaces of the core substrate 4.

  Further, the end portion A of the ground layer 6b is formed with a plurality of concavo-convex portions 16 including the concave portions 11 and the convex portions 12 continuously. Specifically, a resist is applied on the conductor layer 6, and the resist is exposed and developed to form unevenness at the end of the resist, and the end of the conductor layer 6 is exposed. Then, an etching solution is immersed in the exposed end portion of the conductor layer 6 to etch the exposed end portion. As a result, a plurality of concave and convex portions 16 including the concave portions 11 and the convex portions 12 are continuously formed at the end A of the ground layer 6b.

  Further, when forming irregularities on the end A of the ground layer 6b, a conventionally known thin film forming technique such as a CVD method, a sputtering method or a spin coating method, or a thin film processing technique such as an etching technique or a photolithography technique is adopted. Thus, the opening 13 can be formed in the central region of the ground layer 6b where the semiconductor element 2 is mounted. Moreover, the 2nd uneven part 17 which consists of the 2nd recessed part 14 and the 2nd convex part 15 can be formed in the edge part B of the opening part 13 using the technique mentioned above.

  Next, the film layer 5b is prepared. The film layer 5b is a sheet made of a fiber resin using at least one of, for example, a polyparaphenylene benzbisoxazole resin, a wholly aromatic polyamide resin, a wholly aromatic polyester resin, a polyimide resin, or a liquid crystal polymer resin. .

  And the polyimide which comprises the contact bonding layer 5a is adhere | attached with the conventionally well-known spin coat method etc. with respect to the upper surface of the conductor layer 6, and the film layer 5b prepared on the adherence layer is bonded together. Further, by solidifying the adherent layer, the film layer 5b is fixed on the conductor layer 6 via the adhesive layer 5a, and the insulating layer 5 is formed. The thickness dimension of the film layer 5b is, for example, 7.5 μm, and the thickness dimension of the adhesive layer 5a is set to 3 μm. And the insulating layer 5 which consists of the film layer 5b and the contact bonding layer 5a can be formed.

Next, a through hole is formed in the insulating layer 5 using, for example, a YAG laser device or a CO ₂ laser device. The through hole is formed by irradiating the surface of the insulating layer 5 with laser light from a direction perpendicular to the surface of the insulating layer 5. Furthermore, the via conductor 7 is formed by, for example, performing a conventionally known plating process on the through hole and filling the through hole with a conductive material.

  Further, the material constituting the signal line 6a is applied to the upper surface of the film 5b by a conventionally known vapor deposition method, CVD method, sputtering method or the like. And after apply | coating a resist to the surface and performing exposure development, the etching process is performed and the signal track | line 6a is formed. The signal line 6a is formed on the upper surface of the film layer 5b at a location facing the ground layer 6b via the adhesive layer 5a.

  Furthermore, the insulating layer 5 can be formed on the signal line 6a by forming the film layer 5b via the adhesive layer 5a as described above. Then, the ground layer 6b (second conductor layer) is formed on the insulating layer 5 as described above. The unevenness of the end of the ground layer 6b (second conductor layer) is shifted alternately with respect to the unevenness of the ground layer 6b (first conductor layer) formed on the upper surface of the core substrate 4 in plan view. ing. That is, the concave portion 11 of the first conductor layer and the convex portion 12 of the second conductor layer are arranged so as to correspond to each other through a plane.

  Furthermore, the wiring board 1 can be produced by repeating the above-described lamination process. A semiconductor element mounting structure can be realized by mounting the semiconductor element 2 on the wiring board 1 via the bumps 3.

  In addition, the thermal expansion of the whole insulating layer 5 can be reduced by making the contact bonding layer 5a contain a nonmetallic inorganic filler previously, and forming the insulating layer 5. FIG.

  In addition, this invention is not limited to the above-mentioned form, A various change, improvement, etc. are possible in the range which does not deviate from the summary of this invention.

It is a top view of the mounting structure of the semiconductor element concerning the embodiment of the present invention. It is sectional drawing of the mounting structure of the semiconductor element which concerns on embodiment of this invention. It is a top view of the ground layer concerning the embodiment of the present invention. It is a top view of the ground layer concerning the embodiment of the present invention. It is the permeation | transmission top view which laminated | stacked two layers of the ground layer based on embodiment of this invention up and down. It is an edge part of the ground layer which concerns on embodiment of this invention, Comprising: (a) or (b) is a top view which shows the variation of the edge part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring board 2 Semiconductor element 3 Bump 4 Core board 5 Insulating layer 5a Adhesive layer 5b Film layer 6 Conductor layer 6a Signal line 6b Ground layer 7 Via conductor 8 Through hole 9 Through hole conductor 10 Insulator 11 Concave part 12 Convex part 13 Opening part 16 Concavity and convexity A end B end

Claims (9)

A wiring comprising: an insulating layer; a first conductor layer that is a ground layer formed on one main surface of the insulating layer; and a second conductor layer that is a ground layer formed on the other main surface of the insulating layer. A substrate,
The end portion of the first conductor layer and the end portion of the second conductor layer are formed with a plurality of concavo-convex portions including a concave portion and a convex portion in plan view,
The wiring board, wherein the concave portion of the first conductor layer and the convex portion of the second conductor layer are arranged so as to correspond to each other through a plane. The wiring board according to claim 1,
The wiring board, wherein the insulating layer is made of polyparaphenylene benzbisoxazole resin. In the wiring board according to claim 1 or 2,
The wiring board, wherein the uneven portion of the first conductor layer is formed along an outer periphery of the first conductor layer. The wiring board according to claim 3,
The first conductor layer has an opening formed in a central region, and a plurality of second concavo-convex portions including a second concave portion and a second convex portion are continuously formed along an end portion of the opening portion. A wiring board characterized by the above. The wiring board according to claim 4,
The pitch between the recesses adjacent on the outer periphery of the first conductor layer is larger than the pitch between the second recesses adjacent at the end of the opening of the first conductor layer. substrate. The wiring board according to any one of claims 1 to 5,
The convex portion is trapezoidal in plan view,
The wiring board according to claim 1, wherein the concave portion has an inverted trapezoidal shape in plan view. The wiring board according to any one of claims 1 to 6,
A signal line formed on the one principal surface of the insulating layer;
The wiring board according to claim 1, wherein an end portion of the first conductor layer adjacent to the signal line has fewer uneven portions than an end portion of the first conductor layer not adjacent to the signal line. The wiring board according to any one of claims 1 to 6,
A signal line formed on the one principal surface of the insulating layer;
The end of the first conductor layer adjacent to the signal line is formed in a straight line,
An end of the first conductor layer that is not adjacent to the signal line has the uneven portion. A wiring board according to any one of claims 1 to 8, and a semiconductor element mounted on the wiring board,
The semiconductor element mounting structure, wherein the semiconductor element is connected to the wiring board via a bump.

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