JP2008277392A - Substrate having built-in component and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a substrate having a built-in component capable of improving a bonding force between a semiconductor element and a wiring board, and simplifying its manufacturing process. <P>SOLUTION: This substrate 1 having the built-in component is provided with a wiring board 2 having a concave portion 14, a semiconductor element 3 housed in the concave portion 14, and an insulating layer 8 for covering the semiconductor element 3. At least either the lower surface of the semiconductor element 3 or the bottom surface of the concave portion 14 is formed to be uneven, and one part of the insulating layer 8 is filled in a gap between the lower surface of the semiconductor element 3 and the bottom surface of the concave portion 14. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a component-embedded substrate incorporating a semiconductor element such as an IC (Integrated Circuit) or LSI (Large Scale Integration), and a method for manufacturing the same.

  2. Description of the Related Art Conventionally, a component-embedded board including a wiring board and a semiconductor element such as an IC or LSI that can be built in the wiring board is known (see Patent Document 1 below).

  In the component-embedded substrate described in Patent Document 1, the built-in semiconductor element is bonded to the wiring board via bumps, and an insulating layer is formed on the semiconductor element so as to cover the semiconductor element. .

  In addition, the semiconductor element is connected to the wiring board by interposing the bump between the semiconductor element and the wiring board. Then, an underfill made of, for example, an epoxy resin is formed in the gap between the semiconductor element and the substrate formed by interposing the bumps, and the adhesive force between the two is maintained.

The semiconductor element filled with underfill and the surface of the wiring substrate are formed flat.
JP 2004-63583 A

  However, since the component-embedded substrate described in Patent Document 1 described above has a flat surface on the surface of the semiconductor element filled with the underfill and the wiring substrate, sufficient adhesion between the two due to the underfill cannot be ensured. There was a thing. As a result, the semiconductor element may be displaced with respect to the wiring board and the semiconductor element may not operate normally, which may reduce the reliability of the component built-in board.

  In the method for manufacturing a component-embedded board described in Patent Document 1 described above, an underfill is filled between the wiring board and the semiconductor element, and then an adhesive is applied on the wiring board so as to cover the semiconductor element. In order to fabricate the component built-in substrate, the semiconductor element is fixed to the component built-in substrate through two steps. Therefore, the manufacturing process has become complicated.

  The present invention has been made in view of the above-described problems, and includes a component-embedded substrate that can improve the adhesive force between a semiconductor element and a wiring substrate, and a component-embedded substrate that can simplify a manufacturing process. An object is to provide a manufacturing method.

  In order to solve the above problems, a component-embedded substrate of the present invention is a component-embedded substrate comprising a wiring substrate having a recess, a semiconductor element accommodated in the recess, and an insulating layer covering the semiconductor element. In addition, at least one of the lower surface of the semiconductor element or the bottom surface of the recess is formed in an uneven shape, and a part of the insulating layer is filled in a gap between the lower surface of the semiconductor element and the bottom surface of the recess. It is characterized by.

  In the component-embedded substrate of the present invention, the maximum height (Rz) of the lower surface of the semiconductor element is 0.1 μm to 1 μm.

  In the component-embedded substrate of the present invention, the maximum height (Rz) of the bottom surface of the recess is 1 μm to 10 μm.

  In the component-embedded substrate of the present invention, a part of the insulating layer is filled in a gap between the inner wall surface of the recess and the end surface of the semiconductor element.

  In the component-embedded substrate of the present invention, the wiring substrate includes a core substrate having a base material in which fibers are woven vertically and horizontally, and an insulating member formed on an upper surface or a lower surface of the core substrate and provided with the recess. It is characterized by having.

  In the component-embedded substrate of the present invention, the insulating layer has a structure in which a film layer is laminated on the wiring substrate via an adhesive layer, and fills a gap between the lower surface of the semiconductor element and the bottom surface of the recess. A part of the insulating layer is made of the adhesive layer.

  In the component-embedded substrate of the present invention, the film layer is formed with a tapered through hole having a lower width than the upper portion, and a part of the adhesive layer is also filled in the through hole. It is characterized by that.

  In the component-embedded substrate of the present invention, the film layer is made of a polyparaphenylene benzbisoxazole resin.

  The method for manufacturing a component-embedded substrate of the present invention includes a step of preparing a substrate having a recess, a semiconductor element is accommodated in the recess, and a gap is formed between the lower surface of the semiconductor element and the bottom surface of the recess. A step of bonding a film layer on the substrate via an adhesive so as to cover the semiconductor element, pressing the film layer toward the substrate, and a part of the adhesive is Flowing into the gap, filling the gap with a part of the adhesive, and curing the adhesive in a state where the gap is partially filled with the adhesive, And a step of adhering to the substrate.

  The method for manufacturing a component-embedded substrate according to the present invention further includes a step of filling a part of the adhesive into a gap between the inner wall surface of the recess and the end surface of the semiconductor element. .

  In the method for producing a component-embedded substrate of the present invention, a through hole is formed in the film layer, and when the film layer is pressed against the substrate, a part of the adhesive is formed between the gap and the through hole. It is characterized by flowing into the hole.

  In the method of manufacturing a component-embedded substrate according to the present invention, the through hole has a tapered shape whose width is lower than the upper part, and a part of the adhesive flows from the lower part to the upper part of the through hole. It is characterized by doing.

In the method of manufacturing a component-embedded substrate according to the present invention, the viscosity of the adhesive flowing into the gap is from 10 ² Pa · s to 10 ⁵ Pa · s.

  Moreover, the manufacturing method of the component built-in substrate of the present invention is characterized in that the pressure for pressing the film layer against the substrate is 0.5 MPa to 5 MPa.

Moreover, the manufacturing method of the component built-in substrate according to the present invention is characterized in that an atmosphere when the film layer is pressed toward the substrate is 10 Pa to 10 ⁴ Pa.

  ADVANTAGE OF THE INVENTION According to this invention, the component built-in board | substrate which can improve the adhesive force of a semiconductor element and a wiring board can be provided. In addition, it is possible to provide a method for manufacturing a component-embedded substrate that can simplify the manufacturing process.

  Embodiments of a component built-in substrate according to the present invention will be described below in detail with reference to the drawings. Such a component-embedded substrate is used for electronic devices such as various audiovisual devices, home appliances, communication devices, computer devices, and peripheral devices.

  FIG. 1 is a plan view of a component built-in substrate according to the present embodiment, and FIG. 2 is a cross-sectional view of the component built-in substrate according to the present embodiment.

  The component-embedded substrate 1 according to the present embodiment includes a wiring substrate 2 and a semiconductor element 3 such as an IC or an LSI incorporated in the wiring substrate 2.

  On the wiring board 2, a mounting element 5 is formed via a bump 4 such as solder in the center of the wiring board 2 in plan view.

  The wiring substrate 2 includes a core substrate 6, a conductor layer 7 and an insulating layer 8 laminated on the main surface and other main surfaces of the core substrate 6. A part of the insulating layer 8 is used as an insulating member for forming a concave portion 14 to be described later.

  The core substrate 6 is impregnated with a thermosetting resin such as an epoxy resin, a bismaleimide triazine resin or a cyanate resin in a base material in which glass fiber, polyparaphenylene benzbisoxazole resin, wholly aromatic polyamide resin or the like is woven vertically and horizontally. It is produced by laminating and solidifying the laminated sheets.

  The core substrate 6 can also be made from a resin without using a base material. As the resin, for example, low thermal expansion resin such as polyparaphenylene benzbisoxazole resin, wholly aromatic polyamide resin, wholly aromatic polyester resin, polyimide resin or liquid crystal polymer resin can be used. Among these, it is desirable to use a polyparaphenylene benzbisoxazole resin. The polyparaphenylene benzbisoxazole resin has a low coefficient of thermal expansion of −5 ppm / ° C. to 5 ppm / ° C., and by using such a low thermal expansion resin, the thermal expansion of the core substrate 6 itself can be suppressed.

  The core substrate 6 is formed with a through hole 9 that penetrates the core substrate 6 in the vertical direction. A through-hole conductor 10 made of conductive copper plating or the like is formed on the inner wall surface of the through-hole 9. The through hole 9 is filled with an insulator 11 made of an insulating resin in order to improve the flatness of the core substrate 6. The through-hole conductor 10 electrically connects the conductor layers 7 formed on the main surface or other main surface of the core substrate 6. Further, by filling the through hole 9 with the insulator 10, a via conductor 12 to be described later can be formed immediately above or directly below the through hole 9, which contributes to downsizing of the wiring board 1.

  The conductor layer 7 has a plate-like signal line 7a having a function of transmitting a predetermined electric signal and a flat plate-like function having a function of setting a power supply potential connected to the mounting element 5 to a common potential, for example, a ground potential. And a ground layer 7b.

  The signal line 7a is disposed so as to face the ground layer 7b with the insulating layer 8 interposed therebetween. The circuit wiring K is composed of the signal line 7a and the ground layer 7b facing the signal line 7a. Moreover, the conductor layer 7 consists of metal materials, such as copper, silver, gold | metal | money, aluminum, nickel, or chromium, for example.

    The insulating layer 8 is formed by vertically laminating an adhesive layer 8a and a film layer 8b. The insulating layer 8 is formed with via conductors 12 penetrating in the vertical direction. The via conductor 12 is for electrically connecting conductor layers 7 having different vertical positions. The via conductor 12 is formed in a wide reverse taper shape from the main surface side of the core substrate 6 toward the main surface side of the wiring substrate 2 (from the other main surface side of the core substrate 6 to the other main surface side of the wiring substrate 2). For example, it is made of a conductive material such as copper, silver, gold, aluminum, nickel, or chromium.

  The adhesive layer 8a is for fixing the film layer 8b to the core substrate 6 or the conductor layer 7, and an adhesive such as a thermosetting resin or a thermoplastic resin is used. The adhesive becomes the adhesive layer 8a after curing. As the thermosetting resin, for example, at least one of polyimide resin, acrylic resin, epoxy resin, urethane resin, cyanate resin, silicon resin, and bismaleimide triazine resin can be used. As the thermoplastic resin, since it is necessary to have heat resistance that can withstand heating during solder reflow, it is desirable that the softening temperature of the constituent material is 200 ° C. or higher. Polyether ketone resin, polyethylene terephthalate resin, polyphenylene ether Resin or the like can be used.

  The adhesive is laminated by being laminated on the core substrate 6 and the conductor layer 7 with the film layer 8b bonded together, and is cured by applying pressure while heating using, for example, a heating press, and then cooling. The adhesive layer 8a is set so that the thickness dimension is, for example, 1 μm to 10 μm.

  The thickness of the film layer 8b is precisely controlled in order to bring the thickness dimension of the insulating layer 8 close to a predetermined value and ensure flatness. The film layer 8b is desirably a material having excellent heat resistance and hardness in order to prevent the thickness dimension of the film layer 8b from being changed by the applied temperature and pressure. As the film layer 8b having such characteristics, for example, at least one of polyparaphenylene benzbisoxazole resin, wholly aromatic polyamide resin, wholly aromatic polyester resin, polyimide resin or liquid crystal polymer resin is used. it can. The film layer 8b is preferably a mixed resin of a polyparaphenylene benzbisoxazole resin and a polyimide resin in order to maintain the strength of the film layer 8b. Further, the thickness dimension of the film layer 8b is set to be, for example, 1 μm to 10 μm.

  The film layer 8b is formed with a through hole 13 that penetrates from the upper surface to the lower surface. The through-hole 13 is formed in a narrow taper shape from the main surface side of the core substrate 6 toward the main surface side of the wiring substrate 2 (from the other main surface side of the core substrate 6 to the other main surface side of the wiring substrate 2). ing. In other words, the through hole 13 between the mounting element 5 and the core substrate 6 is formed in a tapered shape whose lower part is wider than its upper part. The diameter of the through hole 13 is set to, for example, 50 μm to 2 mm. Here, the diameter of the through hole 13 is the diameter of the upper end of the through hole 13. The through-hole 13 is filled with a part of the adhesive layer 8a. Therefore, the adhesive layer 8a filled in the through-hole 13 can increase the adhesive force between the two by increasing the contact area between the adhesive layer 8a and the film layer 8b, making it difficult to peel them off. it can.

  When the adhesive flows into the recess 14 described later, the thickness dimension of the adhesive layer 8a located immediately above the recess 14 is deformed, but the region that does not overlap the recess 14 in plan view with respect to the film layer 8b. By forming the through hole 13 in the hole, an amount of adhesive equivalent to the adhesive flowing into the recess 14 can be caused to flow into the through hole 13 and the thickness dimension of the adhesive layer 8a can be adjusted.

  Further, as described above, the film layer 8b is formed with the holes of the reverse-tapered via conductor 12, so that the internal stress of the film layer 8b becomes unbalanced and the film layer 8b is easily bent. By forming the tapered through hole 13 in the layer 8b, the internal stress of the film layer 8b can be adjusted to be balanced, and the film layer 8b can be made difficult to bend.

  Further, when the film layer 8b is placed on the upper side, the conductor layer 7 is placed on the lower side, and the side on which the through-hole 13 is widened faces downward, the film layer 8b is pressed against the conductor layer 7 with an adhesive. The adhesive tends to flow into the widened through hole 13. Further, the adhesive that has flowed into the through hole 13 is less likely to flow out from the upper surface of the film layer 8b due to the narrowing of the through hole 13, and it is possible to suppress the resin from flowing out from the upper surface of the film layer 8b more than necessary. it can.

  Moreover, the through-hole 13 is formed more in the edge part of the film layer 8b than the center of the film layer 8b. By providing many through holes 13 at the end of the film layer 8b, when the film layer 8b is bonded to the adhesive and pressed, the remainder of the adhesive that flows out from the center of the substrate toward the end of the substrate is It tends to flow toward the through hole 13 formed at the end of the film layer 8b. As a result, the through-hole 13 is filled with the remainder of the adhesive, and the thickness dimension of the adhesive can be adjusted.

Adhesive flows into the recess 14 to be described later, a through hole 13 which the thickness of the adhesive layer 8a is formed in order to suppress the deformation, from the viewpoint of adjusting the characteristic impedance Z _O which will be described later, the ground layer 7b and the signal It is formed so as not to be located directly below the signal line 7a between the line 7a. In other words, the through hole 13 is formed so as not to overlap the signal line 7a in plan view. Here it will be described the characteristic impedance _{Z O.} The characteristic impedance Z _O represents the signal transmission characteristic of the circuit wiring K in the wiring board 2 on which the mounting element 5 is mounted, and is expressed by the relative dielectric constant of the resin interposed between the signal line 7a and the ground layer 7b. Dependent.

It is desirable that the signal line 7a is not formed across the through hole 13 of the film layer 8b in plan view. If the film layer 8b and the adhesive layer 8a filled in the through-hole 13 are continuously formed on the plane immediately below the signal line 7a, the relative permittivity of both (relative permittivity X, relative permittivity) Since Y) is different, it is difficult to adjust the characteristic impedance of the circuit wiring K. That is, the transmission signal transmitted along the signal line 7a is, for the relative dielectric constant X area from the relative permittivity of the proceeds to the region of the Y, the value of the characteristic impedance Z _O is changed, decrease the quality of the transmission signal Resulting in. Therefore, by not forming the through hole 13 immediately below the signal line 7a, it is possible to suppress the deterioration of the transmission signal of the signal line 7a.

  In addition, a recess 14 is formed in at least one of the plurality of insulating layers 8. FIG. 3A is a plan view of the recess 14 in which the semiconductor element 3 is accommodated, and FIG. 3B is a cross-sectional view of the recess 14 in which the semiconductor element 3 is accommodated.

  As shown in FIG. 3, the recess 14 is large enough to accommodate the semiconductor element 3. In addition, with the semiconductor element 3 housed in the recess 14, an adhesive is applied so as to cover the semiconductor element 3, and the adhesive flows between the inner wall surface of the recess 14 and the end face of the semiconductor element 3. Therefore, a gap k is provided between the inner wall surface of the recess 14 and the end surface of the semiconductor element 3.

  The gap k is formed in at least a part of the periphery of the semiconductor element 3 accommodated in the recess 14 in plan view. Further, the gap k is formed so as to be connected to a part of a gap g formed between a lower surface of the semiconductor element 3 and a bottom surface of the recess 14 which will be described later. Therefore, the adhesive that has flowed into the gap k can enter the gap g along the end face of the semiconductor element 3 from the gap k and further flow into the gap g.

  Further, in a plan view, the distance L of the vertical line from the end surface of the semiconductor element 3 to the inner wall surface of the recess 14 in the gap k is preferably set to 50 μm to 0.5 mm. By setting the distance L to 50 μm or more, the melted adhesive can easily flow into the gap k. Furthermore, an adhesive can flow into the gap g described later. Further, by setting the distance L to 0.5 mm or less, the semiconductor element 3 is not greatly displaced in the recess 14, and the semiconductor element 3 can be arranged in a desired region in the recess 14. Thereby, the semiconductor element 3 and the conductor layer 7 can be appropriately electrically connected, and the semiconductor element 3 can be operated normally.

  Further, as shown in FIG. 4, the gap k is preferably provided at a large portion corresponding to the corner of the recess 14 in plan view. When the gaps k are provided at the four corners of the concave portion 14, the adhesive can surely flow into the four corners of the concave portion 14, so that all four corners of the semiconductor element 3 can be fixed to the concave portion 14. As a result, the four corners of the semiconductor element 3 can be made difficult to peel from the recess 14, and the semiconductor element 3 and the conductor layer 7 can be appropriately electrically connected without being displaced in the recess 14. Can do. Further, when external mechanical stress is transmitted to the wiring board 2, stress is generated inside the wiring board 2, but this stress is easily concentrated at the four corners of the recess 14, and cracks are generated in this portion. There is a risk of lowering the insulation of the wiring board 2, but by providing large gaps k at the four corners of the recess 14, stress concentration is reduced at the four corners of the recess 14, and cracks are generated at those locations. Can be reduced.

  The recess 14 is not limited to the shape as described above, and may be a polygonal shape or the like as long as the semiconductor element 3 can be accommodated.

  Further, the recess 14 is formed at a location overlapping the mounting element 5 in plan view. The distance between the semiconductor element 3 and the mounting element 5 is shortened, and the positions of the pads formed on the semiconductor element 3 and the mounting element 5 are formed in correspondence with each other so that the distance between the wirings connecting them is not short. Therefore, it is possible to prevent the wiring from becoming long, and the wiring layout can be simplified.

  The lower surface of the semiconductor element 3 is formed in an uneven shape. Since the lower surface of the semiconductor element 3 is formed in an uneven shape, a gap g is formed between the lower surface of the semiconductor element 3 and the bottom surface of the recess 14 when the semiconductor element 3 is mounted in the recess 14. It will be. That is, the gap g is generated due to the difference in level of the irregularities on the lower surface of the semiconductor element when the semiconductor element 3 is placed with the lower surface facing the bottom surface of the recess 14.

  The unevenness formed on the lower surface of the semiconductor element 3 can be provided by, for example, an etching method, a polishing method (polishing with a diamond grindstone, polishing by blowing abrasive grains, etc.), a laser processing method, or the like. Moreover, it is preferable that the maximum height (Rz) according to JISB0601-2001 is set to 0.1 micrometer to 1 micrometer for the lower surface of the semiconductor element 3. FIG.

  By setting the maximum height (Rz) to 0.1 μm or more, the adhesive can flow uniformly into the gap g between the lower surface of the semiconductor element 3 and the bottom surface of the recess 14. Further, when the maximum height (Rz) is set to 1 μm or less, a force sufficient to break the semiconductor element 3 with respect to the semiconductor element 3 is conducted even when unevenness is formed on the lower surface of the semiconductor element 3 by a polishing method. There is nothing to do. Therefore, by setting the maximum height (Rz) within this range, even if the concave and convex portions are formed on the lower surface of the semiconductor element 3 by the polishing method, the semiconductor element 3 is not destroyed, and the semiconductor element 3 is moved into the concave portion 14. The gap g into which the adhesive can sufficiently flow can be formed between the semiconductor element 3 and the bottom surface of the recess 14.

  The irregular shape formed on the lower surface of the semiconductor element 3 is regular or irregular as long as a part of the adhesive can flow between the lower surface of the semiconductor element 3 and the bottom surface of the concave portion 14. It does not matter which is a typical shape. FIG. 5 is an irregular plan view having regularity formed on the lower surface of the semiconductor element 3. In addition, the recessed part is set as the dent H. As shown in FIGS. 5 (a) to 5 (d), a regular shape can be used, for example, a stripe shape, a matrix shape, a meandering shape, a dot shape, or the like. Further, the uneven shape may be a combination of these shapes.

  Further, since the gap g is partially filled with the adhesive layer 8a, the lower surface of the semiconductor element 3 can be fixed to the bottom surface of the concave portion 14, and the semiconductor element 3 can be bonded to the layer located immediately below the semiconductor element 3. The power can be improved. As a result, the semiconductor element 3 can be prevented from being displaced with respect to the wiring board 2, and the semiconductor element 3 can be operated normally without causing an electrical malfunction due to the displacement. The reliability of the component built-in substrate 1 can be improved.

  The semiconductor element 3 is made of a material that approximates the coefficient of thermal expansion of the insulating layer 8. For example, silicon, germanium, gallium arsenide, gallium arsenide phosphorus, gallium nitride, silicon carbide, or the like can be used. In addition, the thickness dimension of the semiconductor element 3 can use the thing of 0.1 mm to 1 mm, for example. As the mounting element 5 to be mounted on the wiring substrate 2, for example, silicon, germanium, gallium arsenide, gallium arsenide phosphorus, gallium nitride, silicon carbide, or the like can be used as in the semiconductor element 3.

  As described above, according to this embodiment, the lower surface of the semiconductor element 3 is formed in an uneven shape, and the bonding area between the lower surface and the adhesive flowing between the lower surface of the semiconductor element 3 and the bottom surface of the recess 14 is increased. By doing so, both adhesiveness can be improved and the adhesive force of the semiconductor element 3 and the wiring board 2 can be improved.

  Next, a method for manufacturing the above-described component built-in substrate 1 will be described.

  First, a substrate having a recess is prepared.

  As a pre-stage for preparing a substrate having a recess, a core substrate 6 is produced as shown in FIGS. 6 (a) to 6 (e). As an example of a specific method for producing the core substrate 6, first, as shown in FIG. 6A, a plurality of sheets in which a base material is impregnated with a thermosetting resin are prepared, and the sheets are laminated. The laminated structure S is solidified by hot pressing.

  Next, as shown in FIG. 6B, through holes 9 are formed in the vertical direction on the core substrate 6 produced by solidifying the laminated structure S by a conventionally known drilling process or the like. Then, as shown in FIG. 6C, the surface of the core substrate 6 is deposited by electroless plating or the like, and the through-hole conductor 10 is formed on the inner peripheral surface of the through-hole 9. A plurality of through holes 9 are formed, and the diameter is set to 0.1 mm to 1 mm, for example. After that, as shown in FIG. 6D, the through hole 9 is filled with a resin such as polyimide to form the insulator 11. Further, as shown in FIG. 6E, a material constituting the conductor layer is deposited by a conventionally known vapor deposition method, CVD method, sputtering method, or the like so as to cover just above the insulator 11. The core substrate 6 has a thickness dimension set to, for example, 0.3 mm to 1.5 mm.

  Next, as shown in FIG. 7A, the material constituting the conductor layer is deposited on the upper and lower surfaces of the core substrate 6 by a conventionally known vapor deposition method, CVD method, sputtering method, or the like. Then, a resist is applied to the surface, and after exposure and development, an etching process is performed to form a ground layer 7 b on the upper and lower surfaces of the core substrate 6.

  Next, a film layer 8b to which an adhesive is applied is prepared. The adhesive is made of, for example, a polyimide resin and can be deposited on the film layer 8b by a conventionally known spin coating method or the like.

  The film layer 8b has a size corresponding to the design dimension of the wiring board 2 to be manufactured, and the through-hole 13 is previously formed at a predetermined position on the surface to which the adhesive is applied by a known laser processing. Keep it. Further, the through hole 13 can be formed in a tapered shape as described above by adjusting the output of the laser.

  The through-hole 13 formed in the film layer 8b has a tapered shape that is wide open on the adhesive side, so that a large amount of the adhesive adhered to the film layer 8b can be removed. Therefore, since the amount of the adhesive can be removed while reducing the number of the through holes 13 formed in the film layer 8b, the amount of the adhesive can be adjusted efficiently and the productivity can be improved. it can.

  Then, as shown in FIG. 7B, the film layer 8b is bonded to the ground layer 7b via an adhesive 8a '. At this time, the film layer 8b is bonded from the upper side to the lower side with the ground layer 7b disposed below. In the film layer 8b, the film layer 8b is bonded to the ground layer 7b via the adhesive 8a 'in a state where the through hole 13 is tapered so that the lower part is wider than the upper part. As a result, the adhesive 8a 'hardly flows out from the upper surface of the film layer 8b, and the film layer 8b can be bonded to the ground layer 7b.

  The film layer 8 b is pressed toward the ground layer 7 b, and a part of the adhesive 8 a ′ is caused to flow into the through hole 13. Then, with the through hole 13 partially filled with the adhesive 8a ′, the adhesive 8a ′ is cured by applying heat to the adhesive with, for example, a heating press device, and the film layer 8b is grounded. It adheres to 7b. Furthermore, the adhesive layer 8a can be formed by curing the adhesive 8a '. The thickness dimension of the film layer 8b is set to 6.5 μm to 8.0 μm, for example, and the thickness dimension of the adhesive layer 8a is set to 2.5 μm to 3.5 μm, for example. And the insulating layer 8 which consists of the film layer 8b and the contact bonding layer 8a can be formed.

Next, as shown in FIG. 7C, via holes are formed in the insulating layer 8 using, for example, a YAG laser device or a CO ₂ laser device. The via hole is formed by irradiating laser light from the direction perpendicular to the upper surface of the insulating layer 8 toward the upper surface of the insulating layer 8. Further, as shown in FIG. 7D, the via conductor 12 is formed by, for example, performing a conventionally known plating process on the via hole and filling the via hole with a conductive material.

  Next, the material constituting the signal line 7a is deposited on the upper surface of the film layer 8b by a conventionally known vapor deposition method, CVD method, sputtering method or the like. Then, as shown in FIG. 7E, a resist is applied to the surface, and after exposure and development, an etching process is performed to form a signal line 7a. The signal line 7a is formed so as not to overlap the through hole 13 in plan view. The signal line 7a is formed on the upper surface of the film layer 8b at a location facing the ground layer 7b via the adhesive layer 8a.

  Next, a film layer 8bx obtained by cutting out a portion where the semiconductor element 3 is to be accommodated in advance is prepared. Then, as shown in FIG. 8 (a), the film layer 8bx is fixed on the film layer 8b with an adhesive to form a recess 14 surrounded by the punched portion and the upper surface of the film layer 8b. can do.

Then, in the same manner as described above, as shown in FIG. 8B, via holes are formed in the insulating layer 8 including the film layer 8bx using, for example, a YAG laser device or a CO ₂ laser device. Further, as shown in FIG. 8C, the via conductor 12 is formed by filling the via hole with, for example, a well-known plating process and filling a conductive material. Then, as shown in FIG. 8D, the conductor layer 7 is formed on the upper surface of the via conductor 12 by a conventionally known vapor deposition method, CVD method, sputtering method or the like.

  In this way, a substrate having a recess can be manufactured.

  Next, as shown in FIG. 9, the semiconductor element 3 is accommodated in the recess 14, and a gap g between the lower surface of the semiconductor element 3 and the bottom surface of the recess 14 is formed.

The surface of the semiconductor element 3 accommodated in the recess 14 that faces the bottom surface of the recess 14 is formed in an uneven shape using, for example, a laser processing method. Such irregularities are formed using, for example, a YAG laser device, a CO ₂ laser device, or an excimer laser device, and are formed by adjusting the energy per pulse of the laser beam. In the case of a YAG laser device, for example, 1 μJ / pulse to 15 μJ / pulse, for a CO ₂ laser device, for example, 0.5 mJ / pulse to 5 mJ / pulse, and for an excimer laser device, for example, 0.02 J / pulse to 0.1 J / pulse. Is used. With this energy, one shot is irradiated with a laser beam to one place on the lower surface of the semiconductor element 3. Recesses processed with laser light are processed so that they are in contact with adjacent recesses in at least one direction, and each recess is made continuous to form a flow path through which the adhesive can flow along the continuous recesses. The adhesive can easily enter the gap g between the lower surface of the semiconductor element 3 and the bottom surface of the recess 14.

  The semiconductor element 3 processed in advance in this way is accommodated in the recess 14, and a gap g is provided between the lower surface of the semiconductor element 3 and the bottom surface of the recess 14.

  Next, the film layer 8by is bonded to the substrate via an adhesive so as to cover the semiconductor element 3.

  FIG. 10 is a cross-sectional view showing a state in which the film layer 8by to which the adhesive 8a 'is applied is positioned on the concave portion 14 in which the semiconductor element 3 is accommodated. As shown in FIG. 10, a film layer 8 by is disposed opposite to the semiconductor element 3 with an adhesive 8 a ′ interposed therebetween.

  FIG. 11 is a cross-sectional view showing a state in which the film layer 8by is bonded to the substrate in which the semiconductor element 3 is accommodated in the recess 14 via the adhesive 8a '. As shown in FIG. 11, a film layer 8by is bonded via an adhesive 8a 'so as to cover the semiconductor element 3.

  FIG. 12 is a cross-sectional view showing a state in which the film layer 8by is pressed against the substrate containing the semiconductor element 3 in the recess 14 via the adhesive 8a '. As shown in FIG. 12, the film layer 8by is pressed against the substrate containing the semiconductor element 3 in the recess 14 under the conditions described later (resin viscosity condition, pressure condition, atmospheric pressure condition), and an adhesive 8a ′. Is introduced from the gap k to enter between the inner wall surface of the recess 14 and the end face of the semiconductor element 3. Further, a part of the adhesive 8 a ′ that has entered enters the gap g between the lower surface of the semiconductor element 3 and the bottom surface of the recess 14. Further, when the film layer 8by is pressed toward the substrate, a part of the adhesive 8a 'also flows into the tapered through hole 13 whose lower part is wider than the upper part formed in the film layer 8by. By pressing the film layer 8by toward the substrate, the adhesive 8a 'can flow into the gap k and the gap g, and the adhesive 8a' can flow into the through hole 13. Therefore, in the step of pressing the film layer 8by, the gap 8 and the gap g and the through hole 13 can be filled with the adhesive 8a ′, and apart from the step of flowing the adhesive 8a ′ into the gap k and the gap g, Since a process of flowing the adhesive 8a ′ into the through hole 13 is not required, the manufacturing process can be simplified. Note that a part of the adhesive 8a 'flows from the lower part to the upper part of the through hole 13, so that the adhesive 8a' easily flows into the widened through hole. Further, by narrowing the through hole 13, it is possible to suppress the adhesive 8a 'from flowing out from the upper surface of the film layer 8by more than necessary.

The viscosity condition of the adhesive 8a ′ when the film layer 8by is pressed toward the conductor layer 7 is preferably 10 ² Pa · s to 10 ⁵ Pa · s. If the viscosity of the adhesive 8a ′ is less than 10 ² Pa · s, the viscosity of the adhesive 8a ′ is too low, so that the adhesive 8a ′ easily flows out from the end of the substrate toward the outside of the substrate, and the insulating layer 8 It is difficult to adjust the thickness dimension. Conversely, if the adhesive 8a ′ has a viscosity of 10 ² Pa · s or more when pressed, the adhesive 8a ′ has an appropriate viscosity, so the amount of the adhesive 8a ′ flowing out of the substrate is reduced. The thickness of the insulating layer 8 can be adjusted to a desired dimension. Further, by setting the viscosity of the adhesive 8a ′ at the time of pressing to 10 ⁵ Pa · s or less, the adhesive 8a ′ can be uniformly introduced into the gap k and the gap g. Note that the temperature of the adhesive 8a ′ when pressed against the conductor layer 7 is set to a temperature range of 80 ° C. to 150 ° C., for example.

  Moreover, it is preferable that the pressure conditions when pressing the film layer 8by with a film laminating machine (laminator) is set to 0.5 MPa to 5 MPa. If the pressure condition is 0.5 MPa or more, the adhesive 8a 'corresponding to the above viscosity condition can be easily allowed to flow into the gap k and the gap g. Moreover, if a pressure condition is 5 Mpa or less, the breakage | damage and deformation | transformation of a board | substrate can be suppressed.

The atmosphere when pressing the film layer 8by is preferably a reduced pressure atmosphere. By pressing in a reduced-pressure atmosphere, it is easy to remove bubbles that may be contained in the adhesive 8a ′, the risk of bubbles remaining in the adhesive 8a ′ can be reduced, and bubbles are generated during heating such as during reflow. Can be prevented from expanding and breaking the wiring board. More specifically, the degree of vacuum in the reduced-pressure atmosphere is preferably set to 10 Pa to 10 ⁴ Pa. If the degree of vacuum is 10 ⁴ Pa or less, bubbles that may be contained in the adhesive 8a ′ can be more reliably removed. On the other hand, if the degree of vacuum is 10 Pa or more, the components of the curing agent contained in the adhesive 8a ′ are less likely to volatilize, and the adhesive 8a ′ can be cured well. In addition, this reduced pressure atmosphere is maintained in the state until, for example, 5 to 15 minutes elapses after reaching the set pressure condition after the start of pressing.

  Next, the adhesive 8a 'is cured while the gap g is partially filled with the adhesive 8a', and the film layer 8by is fixed to the substrate.

  FIG. 13 is a cross-sectional view showing a state where a part of the adhesive 8a ′ is filled in the through hole 13 and the gap g of the film layer 8by. As shown in FIG. 13, heat of 150 ° C. to 200 ° C. is applied to the adhesive 8a ′ while the through-hole 13 and the gap g of the film layer 8by are partially filled with the adhesive 8a ′. Then, the adhesive 8a ′ is cured, and the film layer 8by is fixed to the substrate in which the semiconductor element 3 is accommodated. The adhesive 8 a ′ has a function as an underfill filling between the semiconductor element 3 and the substrate, and covers the connection portion between the semiconductor element 3 and the substrate, thereby Circuit elements can be protected from dust and moisture.

  As described above, since the adhesive 8a ′ can be filled in the gap g at the same time as the insulating layer 8 is formed on the semiconductor element 3, it is possible to perform the manufacturing process without requiring a separate underfill operation. Simplification can be achieved.

  Next, a via hole is formed immediately above the semiconductor element 3 as described above, and the via hole is filled with a conductive material, and a via conductor 12 is formed on the semiconductor element 3. The via conductor 12 is for electrically connecting the semiconductor element 3 and the mounting element 5 to be mounted on the substrate, and is formed in a region overlapping with the mounting element 5 to be mounted later. The distance of the wiring to which the mounting element 5 is connected can be shortened. As a result, the wiring pattern can be simplified by shortening the routing of the wiring. Moreover, generation | occurrence | production of an unnecessary electrical noise can be suppressed because the length of wiring becomes short.

  Furthermore, the wiring board 2 can be produced by repeating the above-described lamination process. The component-embedded substrate 1 can be manufactured by mounting the mounting element 5 on the wiring substrate 2 via the bumps 4.

  FIG. 14 is a cross-sectional view of a component built-in substrate according to another embodiment of the present invention. In the above-described embodiment, the bottom surface of the semiconductor element 3 is formed in an uneven shape n, and the gap g is formed between the bottom surface of the semiconductor element 3 and the bottom surface of the recess 14. However, as shown in FIG. A gap g ′ may be formed between the lower surface of the semiconductor element 3 and the bottom surface of the recess 14 by forming irregularities on the surface. Concavities and convexities are formed on the place where the semiconductor element 3 is placed by a conventionally known etching method, laser processing method, or the like. In such a case, it is not necessary to perform laser processing on the semiconductor element 3, so that the semiconductor element 3 is not broken and the manufacturing yield can be improved. In addition, it is preferable that the maximum height (Rz) of the surface roughness according to JISB0601-2001 is set to 1 micrometer to 10 micrometers for the bottom face of the recessed part 14.

  When the maximum height (Rz) of such irregularities is less than 1 μm, there are the following problems. Since the film layer 8b is formed of a resin, when the molten adhesive flows into the concave portion 14, heat is also applied to the bottom surface of the concave portion 14, and the bottom surface of the concave portion 14 is deformed by the heat. The unevenness of the adhesive tends to be flat, making it difficult for the adhesive to flow. Conversely, by setting the maximum height (Rz) of the unevenness to 1 μm or more, even if the unevenness on the bottom surface of the recess 14 is somewhat deformed by heat, the unevenness can exist on the bottom surface of the recessed portion 14 after deformation, A gap g ′ through which an adhesive can sufficiently flow can be formed between the semiconductor element 3 having a flat bottom surface and the bottom surface of the recess 14.

  In addition, when the maximum height (Rz) of the unevenness exceeds 10 μm, the semiconductor element 3 is likely to be inclined with respect to the bottom surface of the recess 14, and an electrical connection failure between the via conductor 12 and the semiconductor element 3 occurs. Sometimes. In that case, the semiconductor element 3 may not operate normally. Conversely, if the maximum height (Rz) of the unevenness is set to 10 μm or less, the electrical connection between the via conductor 12 and the semiconductor element 3 can be ensured without the inclination of the semiconductor element 3 being greatly inclined with respect to the bottom surface of the recess 14. The semiconductor element 3 can be operated normally.

  Further, the unevenness formed on the bottom surface of the recess 14 is formed in a region overlapping the semiconductor element 3 in plan view, and is formed in at least a part of the region along the end of the semiconductor element 3. As a result, it is possible to allow the adhesive to flow from the end of the semiconductor element 3 toward the gap g ′ between the semiconductor element 3 and the recess 14 with the semiconductor element 3 facing the bottom surface of the recess 14. The semiconductor element 3 can be effectively fixed to the bottom surface of the recess 14.

  In addition, this invention is not limited to the above-mentioned form, A various change, improvement, etc. are possible in the range which does not deviate from the summary of this invention.

  Further, in the above-described embodiment, the film layer 8b to which the adhesive 8a ′ is previously applied is bonded to the conductor layer 7 to produce the wiring board 2. However, in the state where the semiconductor element 3 is accommodated in the recess 14, The adhesive 8a ′ may be deposited on the recess 14 so as to cover the semiconductor element 3, and the film layer 8b may be bonded to the adhesive 8a ′.

It is a top view of the component built-in board concerning the embodiment of the present invention. It is sectional drawing of the component built-in board | substrate which concerns on embodiment of this invention. 1A is a plan view of a recess housing a semiconductor element, and FIG. 2B is a cross-sectional view of the wiring board according to the embodiment of the present invention. 1A is a plan view of a recess housing a semiconductor element, and FIG. 2B is a cross-sectional view of the wiring board according to the embodiment of the present invention. It is a top view which concerns on the lower surface of the semiconductor element which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing process of the component built-in board which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing process of the component built-in board which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing process of the component built-in board which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing process of the component built-in board which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing process of the component built-in board which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing process of the component built-in board which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing process of the component built-in board which concerns on embodiment of this invention. It is sectional drawing explaining the manufacturing process of the component built-in board which concerns on embodiment of this invention. It is sectional drawing of the wiring board which concerns on other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Component built-in board 2 Wiring board 3 Semiconductor element 4 Bump 5 Mounting element 6 Core board 7 Conductive layer 7a Signal line 7b Ground layer 8 Insulating layer 8a Adhesive layer 8a 'Adhesive 8b Film layer 9 Through-hole 10 Through-hole conductor 11 Insulator 12 via conductor 13 through hole 14 hole g gap k gap

Claims (15)

A component-embedded substrate comprising: a wiring board having a recess; a semiconductor element housed in the recess; and an insulating layer covering the semiconductor element,
At least one of the lower surface of the semiconductor element or the bottom surface of the recess is formed in an uneven shape,
Part of the insulating layer is filled in a gap between a lower surface of the semiconductor element and a bottom surface of the recess. The component built-in substrate according to claim 1,
The component-embedded substrate, wherein the maximum height (Rz) of the lower surface of the semiconductor element is 0.1 μm to 1 μm. The component built-in substrate according to claim 1,
The component-embedded substrate, wherein a maximum height (Rz) of a bottom surface of the recess is 1 μm to 10 μm. In the component-embedded substrate according to any one of claims 1 to 3,
Part of the insulating layer is filled in a gap between an inner wall surface of the recess and an end surface of the semiconductor element. In the component built-in substrate according to any one of claims 1 to 4,
The wiring board has a core substrate having a base material in which fibers are woven vertically and horizontally, and
And an insulating member formed on the upper surface or the lower surface of the core substrate and provided with the recess. In the component-embedded substrate according to any one of claims 1 to 5,
The insulating layer is a structure in which a film layer is laminated on the wiring board via an adhesive layer,
A component-embedded substrate, wherein a part of the insulating layer filled in a gap between a lower surface of the semiconductor element and a bottom surface of the recess is made of the adhesive layer. The component built-in substrate according to claim 6,
In the film layer, a tapered through hole having a lower width than the upper portion is formed,
A component-embedded substrate, wherein a part of the adhesive layer is also filled in the through hole. In the component-embedded substrate according to claim 6 or 7,
The component-embedded substrate, wherein the film layer is made of a polyparaphenylene benzbisoxazole resin. Preparing a substrate having a recess;
A step of accommodating a semiconductor element in the recess and forming a gap between a lower surface of the semiconductor element and a bottom surface of the recess;
Bonding the film layer on the substrate via an adhesive so as to cover the semiconductor element;
Pressing the film layer toward the substrate, allowing a part of the adhesive to flow into the gap, and filling the gap with a part of the adhesive;
In a state where a part of the adhesive is filled in the gap, a step of curing the adhesive and fixing the film layer to the substrate;
A method of manufacturing a component-embedded substrate, comprising: In the manufacturing method of the component built-in substrate according to claim 9,
A method for manufacturing a component-embedded board, further comprising a step of filling a part of the adhesive into a gap between an inner wall surface of the recess and an end surface of the semiconductor element. In the manufacturing method of the component built-in substrate according to claim 9 or 10,
A through hole is formed in the film layer,
A method of manufacturing a component-embedded substrate, wherein when the film layer is pressed against the substrate, a part of the adhesive flows into the gap and the through hole. In the manufacturing method of the component built-in substrate according to claim 11,
The through hole has a tapered shape in which the lower part is wider than the upper part,
A part of the adhesive flows from the lower part to the upper part of the through-hole, and the method for manufacturing a component-embedded board. In the manufacturing method of the component built-in substrate according to any one of claims 9 to 12,
The method of manufacturing a component-embedded board, wherein the adhesive flowing into the gap has a viscosity of 10 ² Pa · s to 10 ⁵ Pa · s. In the manufacturing method of the component built-in substrate according to claim 13,
The method for producing a component-embedded substrate, wherein a pressure for pressing the film layer against the substrate is 0.5 MPa to 5 MPa. In the manufacturing method of the component built-in substrate according to any one of claims 9 to 14,
The manufacturing method of a component built-in substrate, wherein an atmosphere when the film layer is pressed toward the substrate is 10 Pa to 10 ⁴ Pa.

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