JP4962402B2 - Electro-optical device drive circuit, electro-optical device, and electronic apparatus - Google Patents

Description

  The present invention relates to a drive circuit for an electro-optical device, an electro-optical device, and an electronic apparatus using the electro-optical device for a display device.

  An active matrix type liquid crystal panel is known as an example of an electro-optical device. In this active matrix type liquid crystal panel, liquid crystal as an electro-optical material is sealed between an element substrate and a counter substrate. FIG. 10 is a block diagram showing a configuration of a liquid crystal panel 1 which is an example of this type of active matrix liquid crystal panel. FIG. 10 shows a timing signal generation circuit 2 and a γ correction circuit 3 as peripheral circuits in addition to the liquid crystal panel 1. These peripheral circuits are constituted by one or a plurality of semiconductor integrated circuits.

  Prior to describing the configuration of the liquid crystal panel 1, these peripheral circuits will be described. The timing signal generation circuit 2 is a circuit that generates various timing signals for controlling the operation timing of each part in the liquid crystal panel 1. Among the timing signals generated by the timing signal generation circuit 2, there are a scanning line selection pulse G, a data line selection pulse DS, and selection signals SELA and SELB. Here, one scanning line selection pulse G is output from the timing signal generation circuit 2 for each one frame (one vertical scanning) period. Further, one data line selection pulse DS is output for each horizontal scanning period in each frame period. The selection signals SELA and SELB are signals that are switched exclusively in synchronization with the horizontal scanning period. If the selection signal SELA is at a high level in, for example, an odd-numbered horizontal scanning period, the selection signal SELB is an even number. It becomes high level in the first horizontal scanning period.

  The γ correction circuit 3 is a circuit that performs γ correction of the analog image signal supplied to the liquid crystal panel 1. That is, the pixel (described later) in the liquid crystal panel 1 has a characteristic that the gradation of display changes nonlinearly with respect to the applied voltage. The non-linear conversion (γ correction) having the above relationship is applied to the analog image signal in advance and supplied to the liquid crystal panel 1 so that the display gradation is changed linearly with respect to the analog image signal.

  Next, the liquid crystal panel 1 will be described. As described above, the liquid crystal panel 1 is obtained by sealing liquid crystal as an electro-optical material between an element substrate and a counter substrate. Here, on the element substrate of the liquid crystal panel 1, as shown in FIG. 10, M parallel scanning lines 11-i (i = 1 to M) and N parallel data lines 12 intersecting with these scanning lines 11-i. -J (j = 1 to N) is formed. Then, pixels Qij (i = 1 to M) each having M rows and N columns at the intersections of the scanning lines 11-i (i = 1 to M) and the data lines 12-j (j = 1 to N). , J = 1 to N) and switching transistors Tij (i = 1 to M, j = 1 to N) are formed.

  Each pixel Qij (i = 1 to M, j = 1 to N) is sandwiched between a pixel electrode provided on the element substrate, a counter electrode provided on the counter substrate, and the pixel electrode and the counter electrode. And liquid crystal. The switching transistors Tij (i = 1 to M, j = 1 to N) are TFTs (Thin Film Transistors) formed on the element substrate.

  Each data line 12-j is a wiring for transmitting an analog image signal for determining a display gradation in a pixel, and is connected to sources of M switching transistors Tij (i = 1 to M) having the same column. ing. Each scanning line 11-i is a wiring for transmitting a selection voltage for instructing writing of an analog image signal, and is connected to the gates of N switching transistors Tij (j = 1 to N) in the same row. It is connected. The drain of each switching transistor Tij (i = 1 to M, j = 1 to N) is connected to the pixel electrode of the pixel Qij (i = 1 to M, j = 1 to N). Each switching transistor Tij (i = 1 to M, j = 1 to N) becomes conductive when a selection voltage is applied to the gate through the corresponding scanning line 11-i, and is connected to each source. The analog image signal on the data line 12-j is applied to the pixel electrode of the pixel Qij.

  On the element substrate of the liquid crystal panel 1, in addition to the above-described elements, a scanning line driving circuit 13, a data line driving circuit 14, and N sampling circuits 15-j (j = 1 to N) are formed. ing.

  The scanning line driving circuit 13 controls the selection voltage Gi on the scanning lines 11-i (i = 1 to M) for each horizontal scanning period within one frame (one vertical scanning) period under the control of the timing signal generation circuit 2. This circuit sequentially supplies (i = 1 to M). The scanning line driving circuit 13 can be configured by a shift register that sequentially shifts the scanning line selection pulse G, for example. When this shift register is used, a pulse obtained from each stage of the shift register may be supplied to the scanning lines 11-i (i = 1 to M).

  The data line driving circuit 14 is a circuit that sequentially outputs N sampling pulses SPj (j = 1 to N) while a selection voltage is being output to each scanning line. The data line driving circuit 14 can be constituted by, for example, a shift register that sequentially shifts the data line selection pulse DS. When this shift register is used, the sampling pulse SPj (j = 1 to N) may be extracted from each stage of the shift register.

  The sampling circuits 15-j (j = 1 to N) are provided corresponding to the data lines 12-j (j = 1 to N), respectively. Selection signals SELA and SELB are supplied to each sampling circuit 15-j (j = 1 to N). Each sampling circuit 15-j (j = 1 to N) is given a corresponding one of the sampling pulses SPj (j = 1 to N) for each horizontal period.

  Each sampling circuit 15-j includes analog switches SA-j, SB-j, SC-j, SD-j and SS-j, voltage follower type buffers BUFA-j and BUFB-j, and capacitors CA-j and CB. -J is connected as shown in the figure.

  Each analog switch SA-j or the like is an analog switch switch composed of TFTs on the element substrate. Here, the analog switch SS-j becomes conductive when a high level sampling pulse SPj is applied. The analog switch SA-j is conductive only while the selection signal SELA is at a high level, and the analog switch SB-j is conductive only while the selection signal SELA is at a low level. The analog switch SC-j is conductive only while the selection signal SELB is at a high level, and the analog switch SD-j is conductive only while the selection signal SELB is at a low level.

  FIG. 11 is a time chart showing the operation of the liquid crystal panel described above. The operation of the conventional active matrix liquid crystal display device will be described below with reference to this time chart.

  As shown in FIG. 11, in each frame period, selection voltages G1, G2,... Are sequentially output for each horizontal scanning period. The levels of the selection signals SELA and SELB are exclusively switched in synchronization with the horizontal scanning period.

  In the example shown in FIG. 11, the selection signal SELA is set to the high level and the selection signal SELB is set to the low level in the first horizontal scanning period in which the selection voltage G1 is output. Therefore, in each sampling circuit 15-j (j = 1 to N), the analog switches SA-j and SD-j are turned on, and the analog switches SB-j and SC-j are turned off.

  In this state, when the sampling pulse SPj (j = 1 to N) is sequentially output from the data line driving circuit 14, the analog switch SS-j (j = 1) of each sampling circuit 15-j (j = 1 to N). To N) are sequentially conducted. The analog image signal corresponding to each pixel sequentially output from the γ correction circuit 3 is supplied to the capacitor CA− via the analog switches SS-j (j = 1 to N) and SA-j (j = 1 to N). j is sequentially applied to j (j = 1 to N) and held by each capacitor.

  During this time, the voltage written in the capacitor CB-j (j = 1 to N) of each sampling circuit 15-j (j = 1 to N) in the immediately preceding horizontal scanning period is changed to the analog switch SD-j (j = 1 to 1). N), the data is output to the data line 12-j (j = 1 to N). Each output voltage on the data line 12-j (j = 1 to N) is output from the pixel Q1j in the first row via the switching transistor T1j (j = 1 to N) while the selection voltage G1 is at a high level. It is applied to each pixel electrode (j = 1 to N). In FIG. 11, among the voltages output from the capacitor CB-j (j = 1 to N) to the data line 12-j (j = 1 to N), the voltage is applied to each pixel electrode of the pixel Q1j (j = 1 to N). The parts to be processed are indicated by diagonal lines.

  Next, in the second horizontal scanning period in which the selection voltage G2 is output, the selection signal SELA is set to low level and the selection signal SELB is set to high level. Therefore, in each sampling circuit 15-j (j = 1 to N), the analog switches SB-j and SC-j are turned on, and the analog switches SA-j and SD-j are turned off.

  In this state, when the sampling pulse SPj (j = 1 to N) is sequentially output from the data line driving circuit 14, the analog switch SS-j (j = 1) of each sampling circuit 15-j (j = 1 to N). To N) are sequentially conducted. The analog image signal corresponding to each pixel sequentially output from the γ correction circuit 3 is supplied to the capacitor CB− via the analog switches SS-j (j = 1 to N) and SB-j (j = 1 to N). j is sequentially applied to j (j = 1 to N) and held by each capacitor.

  During this time, each voltage written in the capacitor CA-j (j = 1 to N) of each sampling circuit 15-j (j = 1 to N) in the immediately preceding horizontal scanning period is converted to the analog switch SC-j (j = 1). To N), the data is output to the data line 12-j (j = 1 to N). Each output voltage on the data line 12-j (j = 1 to N) is a pixel in the second row through the switching transistor T2j (j = 1 to N) while the selection voltage G2 is at a high level. Q2j (j = 1 to N) is applied to each pixel electrode. In FIG. 11, among the voltages output from the capacitor CA-j (j = 1 to N) to the data line 12-j (j = 1 to N), the voltage is applied to each pixel electrode of the pixel Q1j (j = 1 to N). The parts to be processed are indicated by diagonal lines.

  In the subsequent horizontal scanning periods, the same operation is repeated, whereby each analog image signal corresponding to all pixels for one screen is converted into pixels Qij (i = 1 to M, j = 1 to 1) in the liquid crystal panel 1. N) to each pixel electrode.

  In each pixel Qij (i = 1 to M, j = 1 to N), the orientation of the liquid crystal sandwiched between the pixel electrode and the counter electrode changes according to the applied voltage, and the transmittance of the pixel changes. As a result, each pixel is displayed with gradation corresponding to the analog image signal.

  Incidentally, in the conventional liquid crystal panel described above, an analog image signal input from the outside is held in the liquid crystal panel as an analog signal and supplied to each pixel. Therefore, in the holding and supplying process, the sampling switch SS It is easily affected by noise generated by switching of −j (j = 1 to N). For this reason, it is difficult to apply the analog image signal to each pixel as it is, and this has been an obstacle to improving the quality of the display image.

  In particular, in a large liquid crystal panel, a very large parasitic capacitance is interposed in each data line, and some capacitance values reach the order of nF. Such a large liquid crystal panel requires a large driving force to drive the data lines. In the liquid crystal panel 1 shown in FIG. 10, the buffers BUFA-j (j = 1 to N) and BUFB-j (j = 1 to N) are used because the data lines have such a large parasitic capacitance. This is for driving 12-j (j = 1 to N). Here, in order to perform high-quality image display, a voltage that exactly corresponds to an analog image signal applied to the liquid crystal panel 1 is applied to these data lines 12-j (j = 1 to N), and the pixel Should be used for driving.

  However, in the case of a liquid crystal panel using TFTs, these buffers are constituted by operational amplifiers using TFTs. Here, the TFT has a large manufacturing variation in the threshold value or so-called k parameter (parameter obtained by dividing the mutual conductance by the channel width / channel length of the transistor). For this reason, offsets caused by manufacturing variations in TFT threshold values and k parameters occur in the buffers BUFA-j (j = 1 to N) and BUFB-j (j = 1 to N), and correspond to the original analog image signals. The voltage deviated from the voltage is applied to the data line, and the quality of the image display is deteriorated.

  In order to avoid such inconvenience, it is necessary to take measures such as providing a circuit for canceling the offset of the operational amplifier in the liquid crystal panel or performing trimming for canceling the offset of the operational amplifier for each liquid crystal panel. However, when such measures are taken, another problem of increased manufacturing costs arises.

  Further, in the conventional liquid crystal panel 1, an analog signal is supplied to the capacitors CA-j (j = 1 to N) or CB-j (j = 1 to N) by the sampling pulse SPj (j = 1 to N) in a certain horizontal scanning period. After the image signals are sequentially written, these analog image signals are applied to the data lines 12-j (j = 1 to N) in the next horizontal scanning period. During this time, the analog image signal held in the capacitor CA-j (j = 1 to N) or CB-j (j = 1 to N) is attenuated due to leakage, but if the attenuation is large, the display image is displayed. This leads to a decrease in contrast. In addition, as illustrated in FIG. 11, for example, in the capacitor CA-1 corresponding to the pixel in the first column, the analog image signal is written first in the horizontal scanning period, so that the next horizontal scanning period starts. In contrast, the analog image signal is significantly attenuated until the capacitor CA-N corresponding to the pixel in the Nth column, for example, so that the analog image signal is written at the end of the horizontal scanning period. There is relatively little attenuation of the analog image signal until the start of the scanning period. As described above, when the analog image signal is attenuated by a different attenuation amount according to the order of the pixels constituting one row, the contrast of the display image is inclined in the horizontal direction of the screen.

  In order to avoid such a problem, the analog image held in the capacitors CA-j (j = 1 to N) or CB-j (j = 1 to N) over a long period of one horizontal scanning period. It is necessary to keep the signal substantially constant, and in order to do so, it is necessary to increase these capacities. However, when these capacitors are increased, the operation of writing the analog image signal to each capacitor becomes slow, which makes it difficult to drive the liquid crystal panel at high speed.

  The present invention has been made in view of the circumstances described above, and can accurately supply a voltage corresponding to an analog image signal to a pixel without being affected by switching noise or leakage, and the analog image signal. It is an object of the present invention to provide an electro-optical device capable of high-speed sampling and an electronic apparatus using the same as a display device.

According to the present invention, in the driving circuit of an electro-optical device that displays an image by driving a plurality of pixels formed in a matrix on a substrate based on an analog image signal , the analog signal input within one horizontal scanning period is provided. A plurality of sampling circuits that sequentially sample image signals according to sampling pulses, a timing control circuit that outputs a timing control signal at a predetermined timing from the sampling pulses, and a plurality of sampling circuits according to the timing control signals A plurality of A / D converters for converting each held analog image signal into a digital signal; a plurality of storage means for storing each of the digital signals; and the digital signal stored in each of the plurality of storage means A plurality of D / A conversions for converting the signals into analog signals and supplying the signals to the plurality of pixels There is provided a driving circuit of an electro-optical device characterized by comprising and.
According to another aspect of the invention, there is provided a driving circuit for the electro-optical device, wherein one sampling circuit is selected from the plurality of sampling circuits by the sampling pulse and then the one sampling circuit is selected next. In this period, the timing control circuit supplies the timing control signal to the A / D converter connected to the one sampling circuit.
The present invention is the drive circuit for the electro-optical device described above, wherein the storage unit holds each of the digital signals output from the plurality of A / D converters according to the first latch pulse. A plurality of first-stage latches, and a second-stage latch for simultaneously holding the digital signals held in the plurality of first-stage latches in response to a second latch pulse applied every one horizontal scanning period The timing control circuit supplies the first latch pulse to each of the plurality of first stage latches after outputting the timing control signal.
The present invention is the drive circuit for the above electro-optical device, wherein the timing control circuit outputs the timing control signal and the first latch pulse after the sampling pulse is output. And within one horizontal scanning period.
The present invention is the drive circuit for the electro-optical device described above, wherein the plurality of sampling circuits include k sampling circuits, and the plurality of A / D converters include the k sampling circuits. K A / D converters, and the plurality of first stage latches have k first stage latches corresponding to the k A / D converters, and the sampling pulse Are simultaneously supplied to the k sampling circuits, and the timing control circuit outputs timing control signals to the k A / D converters, and outputs the timing control signals to the k first-stage latches. 1 latch pulse is output.
An A / D that converts the analog image signal into a digital signal in a drive circuit of an electro-optical device that displays an image by driving a plurality of pixels formed in a matrix on the substrate based on the analog image signal. The substrate comprises conversion means, storage means for storing the digital signal, and D / A conversion means for converting the digital signal stored in the storage means into an analog signal and supplying the analog signal to the pixel. An electro-optical device driving circuit is provided.

  According to the driving circuit of the electro-optical device, the input analog image signal is converted into a digital signal and stored in the storage unit as a digital signal until the supply timing to the pixel. Therefore, the input analog image signal can be supplied to the pixels without deterioration.

  The drive circuit of the electro-optical device further includes a plurality of sampling circuits on the substrate that sequentially sample and hold the analog image signals input within one horizontal scanning period, and the A / D conversion unit includes: A plurality of A / D converters for converting the respective analog image signals held in the plurality of sampling circuits into digital signals, and the storage means includes a plurality of digital signals obtained from the plurality of A / D converters; The signal is stored, and the D / A conversion means includes a plurality of D / A converters that convert a plurality of digital signals stored in the storage means into analog signals and supply the analog signals to a plurality of pixels, respectively. There may be.

  In this case, the plurality of A / D converters and the storage means convert the analog image signals held in the plurality of sampling circuits into digital signals within a time shorter than one horizontal scanning period after each of the analog image signals is held. You may make it memorize | store and convert.

  Further, the A / D conversion means is not constituted by a plurality of A / D converters, but the storage means stores a plurality of digital signals obtained from the A / D conversion means within a certain period, and the D The / A conversion unit may include a plurality of D / A converters that convert the plurality of digital signals stored in the storage unit into analog signals and supply the analog signals to the plurality of pixels.

  In this case, a path for supplying a digital signal obtained from the A / D conversion means to the storage means and a path for supplying an external digital signal to the storage means may be provided.

  According to such a drive circuit for an electro-optical device, it can be applied to both a use for handling an analog image signal and a use for handling a digital image signal, and therefore, a plurality of types of electronic devices that require the electro-optical device are manufactured. In this case, it is possible to reduce the manufacturing cost by sharing the electro-optical device as the component.

  In each of the electro-optical device driving circuits described above, the D / A conversion unit converts the analog signal corresponding to the digital signal stored in the storage unit to a non-linear conversion such as γ correction. You may comprise by the D / A converter produced | generated from a signal.

  By doing so, it is not necessary to separately provide an analog circuit for γ correction or the like, and the apparatus can be simplified.

  The present invention is particularly suitable for a TFT active matrix type liquid crystal panel configured by forming a thin film transistor on a substrate.

  The electro-optical device having the drive circuit for the electro-optical device according to the present invention is manufactured and sold alone, and is used as a display device for various electronic devices such as a projector and a computer.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

A. First Embodiment FIG. 1 is a block diagram showing a configuration of an active matrix liquid crystal panel 1A which is a first embodiment of an electro-optical device according to the present invention. In this figure, portions corresponding to those in FIG. 10 described above are denoted by the same reference numerals, and description thereof is omitted.

  In the liquid crystal panel 1A, corresponding to the data lines 12-j (j = 1 to N), sampling switches SS-j (j = 1 to N), capacitors Cj (j = 1 to N), A / D converter 16-j (j = 1 to N), first latch 17-j (j = 1 to N), second latch 18-j (j = 1 to N), D / A converter 19-j (j = 1 to N) is provided.

  Elements constituting these circuits are formed on an element substrate together with a pixel electrode of a pixel, a switching transistor, and the like.

  The A / D converter 16-j (j = 1 to N) is, for example, a successive approximation A / D converter. Each analog input terminal of these A / D converters 16-j (j = 1 to N) is connected to an input signal line of an analog image signal via a sampling switch SS-j (j = 1 to N). Has been. Each analog signal input terminal of the A / D converter 16-j (j = 1 to N) is connected to one electrode of a capacitor Cj (j = 1 to N), and the other of these capacitors is connected to the other electrode. The electrode is grounded.

  The A / D converter 16-j (j = 1 to N) converts the analog signal held in the capacitor Cj (j = 1 to N) into a digital signal and outputs the digital signal. Here, in each A / D conversion by the A / D converter 16-j (j = 1 to N), the sampling switch SS-j (j = 1 to N) corresponding thereto is turned on, and the capacitance C After the analog image signal is written to −j (j = 1 to N), the signal is started within a time shorter than one horizontal scanning period.

  Each latch 17-j (j = 1 to N) is connected to each A / D converter 16 immediately after the A / D conversion by the corresponding A / D converter 16-j (j = 1 to N) is completed. Each digital signal output from -j (j = 1 to N) is held.

  Various timing control circuits for controlling the operation timing of the A / D converter 16-j (j = 1 to N) and the first latch 17-j (j = 1 to N) can be considered. It can be configured as shown in FIG.

  The timing control circuit illustrated in FIG. 2 includes a clock generation circuit 20 and N A / D conversion timing control circuits 21-j (j = 1 to N). Here, as illustrated in FIG. 3, the clock generation circuit 20 outputs a clock CLK having a constant frequency. Further, as illustrated in FIG. 3, each A / D conversion timing control circuit 21-j outputs a predetermined number of clocks CLK after the sampling pulse SPj is output, and then the A / D converter 16-j. Outputs a series of timing control signals necessary for A / D conversion and outputting one digital signal in synchronization with the clock CLK, and then the digital signal output from the A / D converter 16-j A latch pulse for writing a signal to the latch 17-j is output.

  As described above, in the present embodiment, the analog image signal sampled by the sampling pulse SPj and held in the capacitor Cj is then converted into a digital signal within a time shorter than one horizontal scanning period, and the latch 17-j Retained. Therefore, the capacitance value of the capacitor Cj (j = 1 to N) is made smaller than the capacitors CA-j (j = 1 to N) and CB-j (j = 1 to N) in the conventional liquid crystal panel 1. Can do.

  The second latch 18-j (j = 1 to N) is means for holding the output data of the first latch 17-j (j = 1 to N). In the configuration shown in FIG. 1, a latch pulse Lat is given from the timing signal generation circuit 2 to these latches 18-j (j = 1 to N) every horizontal scanning period. As a result, the digital signals for N pixels held in the first latch 17-j (j = 1 to N) are transferred to the second latch 18-j (j = 1 to N).

  The D / A converter 19-j (j = 1 to N) performs D / A conversion of each digital signal held in the second latch 18-j (j = 1 to N). Here, the D / A converter 19-j (j = 1 to N) does not simply convert the digital signal into an analog signal corresponding to this, but performs γ correction at the time of D / A conversion, and performs γ correction. The analog signals made are output to the data lines 12-j (j = 1 to N), respectively.

  As this D / A converter 19-j (j = 1 to N), for example, a switched capacitor type D / A converter can be used.

  Generally, this type of switched capacitor type D / A converter has a plurality of capacitors corresponding to each bit of a digital signal to be converted, and a switching circuit for charging and discharging each capacitor. ing. Here, each capacity has a capacity value corresponding to the weight of each bit of the digital signal. Then, by the switching operation of the switching circuit, the reference voltage from the reference power supply is applied only to the capacitor corresponding to the bit whose value is “1” among the bits to be converted, and then the charge held in each capacitor Are added, and an analog voltage corresponding to the charge after the addition is output. Since this switched capacitor type D / A converter can be composed of only a capacitor and a switching TFT without using an operational amplifier, it can perform D / A conversion without causing an offset. .

  The D / A converter 19-j (j = 1 to N) in this embodiment is obtained by adding a γ correction function to the switched capacitor type D / A converter. For the sake of simplicity, the outline of the D / A converter in the present embodiment will be described as follows by taking the case of D / A conversion of 3-bit digital data D0 to D2 as an example.

First, the D / A converter has three capacitors corresponding to the 3-bit digital data D0 to D2. These three capacitors have capacitance values Cdac, 2Cdac, and 4Cdac corresponding to the weights of bits D0 to D2, respectively.
Further, a switch is inserted between the three capacitors and the output terminal of the D / A converter. Here, a parasitic capacitance having a capacitance value Csln is present at the output terminal of the D / A converter. Further, this D / A converter has a DC power supply for applying a predetermined voltage Vdac to three capacitors and applying a predetermined voltage Vsln to the output terminal of the D / A converter.

  In such a configuration, with the switch opened, the voltage Vdac is applied from the DC power source to the capacitor corresponding to the bit “1” among the three capacitors, and the voltage is applied to the output terminal of the D / A converter. Vsln is applied. Thereafter, the switch is turned on. As a result, charge is transferred between the three capacitors and the parasitic capacitor on the output terminal side, and a voltage V given by the following equation is output from the output terminal of the D / A converter.

V = (N.Cdac.Vdac + Csln.Vsln) / (N.Cdac + Csln)
In the above formula, N is a numerical value corresponding to the lower 3 bits. By appropriately selecting each capacitance value and each voltage value described above, the output voltage V of the D / A converter is increased in an S-shape according to a numerical value N corresponding to 3-bit digital data, and N is supported. An analog voltage obtained by subjecting the analog voltage to γ correction can be obtained.

  If the number of bits of the digital data is large, the voltages Vdac and Vsln may be switched according to the value of the upper bits so as to obtain a wide range of analog voltages.

  The above is the configuration of the present embodiment.

  FIG. 4 is a time chart showing the operation of the liquid crystal panel 1A described above. The operation of this embodiment will be described below with reference to this time chart.

  As shown in FIG. 4, in each horizontal scanning period, the sampling pulse SPj (j = 1 to N) is sequentially output from the data line driving circuit 14, and the sampling switches SS-j (j = 1 to N) are sequentially turned on. It is said. Then, the analog image signal SigA input to the liquid crystal panel 1A from the outside is applied to the capacitor Cj through the sampling switch SS-j that is in a conductive state, and the sampling switch SS-j is in a non-conductive state. By returning, it is held in the capacitor C-j. As a result of such a sampling operation being sequentially performed by each sampling switch SS-j (j = 1 to N), N samples SigAj (j = 1 to N) of the analog image signal have a capacity Cj (j = 1). To N) sequentially.

  In each A / D converter 16-j (j = 1 to N), a sample of an analog image signal (hereinafter referred to as an analog sample) SigAj is held in a capacitor Cj corresponding to each A / D converter 16-j (from one horizontal scanning period). The analog sample SigAj is started within a short predetermined time. Then, digital signals Dj (j = 1 to N) corresponding to N analog samples SigAj (j = 1 to N) are sequentially output from each A / D converter 16-j (j = 1 to N). . Each digital signal Dj (j = 1 to N) is held in the first latch 17-j (j = 1 to N) immediately after being output from the A / D converter.

When the latch pulse Lat is output from the timing signal generation circuit 2, the digital signal Dj (j = 1 to N) held in the first latch 17-j (j = 1 to N) Are simultaneously written to the latches 18-j (j = 1 to N).
Immediately thereafter, D of the digital signal Dj (j = 1 to N) held in the second latch 18-j (j = 1 to N) by the D / A converter 18-j (j = 1 to N). / A conversion is started. When this D / A conversion is completed, the γ-corrected analog signal is output from the D / A converter 18-j (j = 1 to N), and is sent to the data lines 12-j (j = 1 to N), respectively. Supplied.

  Each analog signal on the data line 12-j (j = 1 to N) is supplied to the pixel Qij (j) via the switching transistor Tij (j = 1 to N) while the high-level selection voltage Gi is output. j = 1 to N) is applied to each pixel electrode.

  In the subsequent horizontal scanning periods, the same operation is repeated, whereby each analog signal corresponding to all pixels for one screen is converted into pixels Qij (i = 1 to M, j = 1 to N in the liquid crystal panel 1). ) Is applied to each pixel electrode, and an image is displayed.

  As described above, according to the present embodiment, the analog sample SigAj held in the capacitor Cj by the sampling pulse SPj is converted into the digital signal Dj within a short time after the holding, and the digital signal Dj Is held in the latch 17-j until D / A conversion by the D / A converter 18-j is started. For this reason, even if the analog sample SigAj held in the capacitor C-j is attenuated by leakage, the voltage applied to the pixel has almost no influence. Therefore, according to the present embodiment, it is possible to display an image with high quality. Further, according to the present embodiment, the capacity Cj (j = 1 to N) is higher than the capacity CA-j (j = 1 to N) and CB-j (j = 1 to N) in the conventional liquid crystal panel 1. Can be reduced, high-speed sampling of analog image signals can be performed, and power consumption can be reduced.

  In the above embodiment, the control signal for controlling the operation timing of the A / D converter 16-j and the latch 17-j is generated in response to the output of each sampling pulse SPj. A / D converters 16-j (j = 1 to N) and N latches 17-j (j = 1 to N) are grouped, and A / D conversion operation control and latches are performed in units of groups. Write control may be performed. FIG. 5 shows a configuration example of the timing control circuit in that case. In this example, the A / D converters 16-j (j = 1 to N) and the latches 17-j (j = 1 to N) are grouped into k pieces. For example, in the first group, by outputting the sampling pulse SPk + 1, the A / D converter 16-j (j = 1 to k) and the latch 17- by the A / D conversion timing control circuit 21- (k + 1) are output. Control of the operation timing of j (j = 1 to k) is started. In the next group, by outputting the sampling pulse SP2k + 1, the A / D converter 16-j (j = k + 1 to 2k) and the latch 17-j by the A / D conversion timing control circuit 21- (2k + 1) are output. Control of the operation timing (j = k + 1 to 2k) is started. The same applies to each group thereafter.

B. Second Embodiment FIG. 6 is a block diagram showing a configuration of a liquid crystal panel 1B according to a second embodiment of the present invention. In this figure, portions corresponding to those in FIG. 1 described above are denoted by the same reference numerals, and description thereof is omitted. The liquid crystal panel 1B includes a sampling switch SS-j (j = 1 to N), a capacitor Cj (j = 1 to N), and an A / D converter 16-j (j = 1 to N). Instead, the liquid crystal panel 1B has an A / D converter 22. An analog image signal is input to the A / D converter 22 from the outside of the liquid crystal panel 1B. The A / D converter 22 repeats the A / D conversion of the analog image signal N times during one scanning period. During one scanning period, the data line driving circuit 14 sequentially outputs sampling pulses SPj (j = 1 to N). The A / D conversion by the A / D converter 22 is performed before each sampling pulse SPj is output. When the sampling pulse SPj is output, the digital signal obtained by the A / D conversion is latched by 17-j ( j = 1 to N).

  A sampling pulse SPj (j = 1 to N) from the data line driving circuit 14 is supplied as a latch pulse to the latch 17-j (j = 1 to N). Each of the latches 17-j holds the digital signal output from the A / D converter 22 at that time point when the corresponding sampling pulse SPj is given.

  In the present embodiment, in addition to the image signal input path in the analog format, an image signal input path in the digital format is provided, and any one of the input paths can be selected. When the input path of the image signal in the digital format is selected, the external digital image signal SigD is input to the liquid crystal panel 1B in synchronization with the generation timing of the sampling pulse SPj (j = 1 to N) for each pixel. The Then, the data is sequentially written into the latch 17-j (j = 1 to N) by the sampling pulse SPj (j = 1 to N).

  Other configurations are the same as those of the first embodiment.

  FIG. 7 is a time chart showing the operation of this embodiment.

  As shown in this time chart, in this embodiment, every time each sampling pulse SPj is output, the A / D converter 22 outputs a digital signal SigDj corresponding to the analog sample SigAj, which is latched as the digital signal Dj. 17-j.

  Other operations are the same as those in the first embodiment.

  According to the present embodiment, the analog image signal supplied to the liquid crystal panel 1B is immediately converted into a digital signal, and latched as a digital signal 17-j (j = 1 to 1) until it is time to apply to the data line. N) and the latch 18-j (j = 1 to N) and returned to the analog signal when applied to the data line. Accordingly, there is little deterioration of the analog image signal in the process from being input to the liquid crystal panel 1B until being applied to the data line, and high-quality image display can be performed.

  According to this embodiment, according to the electro-optical device, in addition to the image signal input path in the analog format, the image signal input path in the digital format is provided. The present invention can be applied to both a use of handling a path analog image signal and a use of handling a digital image signal. Accordingly, when a plurality of types of electronic devices that require a liquid crystal panel are manufactured, it is possible to share the liquid crystal panel, which is a component, and to reduce the manufacturing cost.

C. Third Embodiment Next, an example in which the above-described liquid crystal panel 1A or 1B is used in an electronic device will be described.

<Part 1: Projector>
First, a projector using this liquid crystal panel as a light valve will be described. FIG. 8 is a plan view showing a configuration example of the projector.

  As shown in the figure, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The liquid crystal panels 1110R, 1110B, and 1110G have the same configuration as the liquid crystal panel 1A or 1B described above, and R, G, and B primary color signals supplied from an image signal processing circuit (not shown) are the analog image signal SigA described above. As given. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter on the counter substrate.

<Part 2: Mobile computer>
Next, an example in which the liquid crystal panel is applied to a mobile computer will be described. FIG. 9 is a front view showing the configuration of the computer. In the figure, a computer 1200 includes a main body 1204 provided with a keyboard 1202 and a liquid crystal display 1206. The liquid crystal display 1206 is configured by adding a backlight to the back surface of the liquid crystal panel 1A or 1B described above.

  In addition to the electronic devices described with reference to FIGS. 8 and 9, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a work Stations, mobile phones, videophones, POS terminals, devices equipped with touch panels, and the like. Needless to say, the present invention is applicable to these various electronic devices.

  Further, the present invention has been described by taking an example of a TFT using an active matrix type liquid crystal panel as an example. However, the present invention is not limited to this, and one using a TFD (Thin Film Diode) as a switching element or an STN liquid crystal. The present invention can also be applied to a passive liquid crystal device or the like using a sapphire, and can also be applied to a case where a switching element is formed on a silicon substrate. Furthermore, the present invention is not limited to a liquid crystal display device, and can be applied to a display device that performs display using various electro-optic effects such as an electroluminescence element.

  As described above, according to the electro-optical device or the electronic apparatus according to the invention, the input analog image signal is converted into a digital signal and stored as a digital signal until the supply timing to the pixel. Therefore, it is possible to supply an analog image signal to the pixel and display an image with high quality without being deteriorated due to the influence of switching noise or leakage in the apparatus. Further, according to the present invention, it is not necessary to increase the capacity for holding the sampled analog image signal, so that high-speed sampling is possible and power consumption can be reduced.

It is a block diagram which shows the structure of the liquid crystal panel which concerns on 1st Embodiment of this invention. 3 is a block diagram showing a configuration of a timing control circuit in the same embodiment. FIG. It is a time chart which shows operation | movement of the same timing control circuit. It is a time chart which shows operation | movement of the embodiment. It is a block diagram which shows the other structural example of a timing control circuit. It is a block diagram which shows the structure of the liquid crystal panel which concerns on 2nd Embodiment of this invention. It is a time chart which shows operation | movement of the embodiment. It is a figure which shows the structure of the projector which is an example of the electronic device which concerns on the 3rd Embodiment of this invention. It is a figure which shows the mobile computer which is another example of the same electronic device. It is a block diagram which shows the structure of the conventional active matrix type liquid crystal panel. It is a time chart which shows operation | movement of the liquid crystal panel.

Explanation of symbols

  1A, 1B: liquid crystal panel, Qij (i = 1 to M, j = 1 to N), pixel, Tij (i = 1 to M, j = 1 to N), switching transistor, 11-i (i = 1 to 1) M) Scan line, 12-j (j = 1 to N) Data line, 13 Scan line drive circuit, 14 Data line drive circuit, SS-j (j = 1 to N) Sampling switch, C- j (j = 1 to N)... capacity, 16-j (j = 1 to N)... A / D converter, 17-j (j = 1 to N)... first latch, 18-j (j = 1 to N) ... second latch, 19-j (j = 1 to N) ... D / A converter, 22 ... A / D converter.

Claims (8)

In an electro-optical device drive circuit that displays an image by driving a plurality of pixels formed in a matrix on a substrate based on an analog image signal,
A plurality of circuit units corresponding to each of the plurality of data lines;
A clock generation circuit for generating a clock;
Comprising
Each of the plurality of circuit units is
A sampling switch for sampling in accordance with prior Symbol analog image signals that will be input in one horizontal scanning period the sampling signal,
A capacity for holding a signal sampled by the sampling switch;
Wherein said clock from the sampled signal to the sampling switch is output even after that is a predetermined number output from the sampled signal is held within a predetermined short time than one horizontal scanning period to the capacitance, the timing control signal A timing control circuit that outputs in synchronization with the clock ;
Depending on the timing control signal, an A / D converter for converting each of the signal held prior Kiyo amount into a digital signal,
Storage means for memorize the digital signal,
A D / A converter that converts the digital signal stored in the storage means into an analog signal and supplies the analog signal to the plurality of pixels;
The driving circuit of the electro-optical device according to claim <br/> to have. The timing control circuit outputs the timing control signal to an A / D converter corresponding to the capacitor during a period from when the capacitor holds the sampled signal until the capacitor holds the next sampled signal. The drive circuit of the electro-optical device according to claim 1, wherein the drive circuit is supplied. The storage means
A first stage latch for holding a digital signal output from the A / D converter in response to a first latch pulse;
A second-stage latch that simultaneously holds the digital signals held in the first-stage latch in response to a second latch pulse given in each horizontal scanning period in the plurality of circuit units ;
With
3. The drive circuit for an electro-optical device according to claim 1, wherein the timing control circuit supplies the first latch pulse to the first stage latch after outputting the timing control signal. 4.   The time until the timing control circuit outputs the timing control signal and the first latch pulse after the sampled signal is held in the capacitor is within the one horizontal scanning period. Item 4. The drive circuit for the electro-optical device according to Item 3.   The D / A converter is configured by a D / A converter that generates from the digital signal an analog signal obtained by performing nonlinear conversion on the analog signal corresponding to the digital signal held in the second stage latch. The drive circuit of the electro-optical device according to claim 1. Driving circuit for an electro-optical device according to claim 1 to 5, characterized by being configured by forming a thin film transistor on the substrate. Electro-optical apparatus comprising the driving circuit of the electro-optical device according to claims 1 to 6. An electronic apparatus using the electro-optical device according to claim 7 for a display device.

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