JP4957050B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a power semiconductor device used for a power conversion device or the like. More specifically, the present invention relates to a lateral power diode in which a main current flows parallel to the main surface of a semiconductor substrate.

As shown in the cross-sectional view (a) of the main part of the conventional semiconductor device (chip) in FIG. 2, the power diode has a current 103 indicated by an arrow, which has a main surface (101, 102) of the semiconductor substrate 100 and electrodes (105, 106) a vertical structure device that flows in a direction perpendicular to the surface, and a current 103 flows in parallel to both main surfaces (101, 102) of the semiconductor substrate 100 as shown in a cross-sectional perspective view of the main part shown in FIG. There is a lateral structure device. In the conventional lateral device (FIG. 2B), the current 103 has a higher current density in the vicinity of the surface, which is the shortest path between the p ⁺ layer 107 and the n ⁺ layer 108, and the current density is lower as it goes inside the bulk. That is, substantially only the vicinity of the device surface contributes to the current. In the vertical device (FIG. 2A), the current 103 flows almost uniformly in the entire bulk between the electrodes. Therefore, as shown in FIG. The density is averaged between the electrodes. For this reason, when the same current is supplied to devices having the same chip area, the vertical device generally has less bias in the current flowing in the substrate than the horizontal device, and the voltage drop is reduced. This tendency is particularly strong in power devices with a high breakdown voltage and a large current rating, and actual devices used in this field are also exclusively vertical devices.

In the conventional lateral device, the flowing current is concentrated near the surface because the electrodes (105, 106) are on one surface. As shown in the cross-sectional perspective view of the main part in FIG. 3A, the current flows through the path with the lowest resistance between the anode electrode 105 and the cathode electrode 106, that is, the shortest path, so that the current flows between the surface electrodes (105, 106). It flows exclusively on the outermost surface, which is the shortest distance to connect. Therefore, substantially only the vicinity of the outermost surface of the device contributes to the current, and the on-voltage becomes high. As a result, lateral devices are disadvantageous for high current applications. In FIG. 3-1, the magnitude of the current density is visually shown by the thickness of the arrow. Further, in FIGS. 2 and 3-1, a one-dot chain line and a double arrow connecting between them indicate an electrode interval. The chain line in FIGS. 2 and 3-1 indicates a p ⁺ n or n ⁻ n ⁺ junction (the junction is similarly represented in the subsequent drawings).

  When a high breakdown voltage is required, in a lateral device, a depletion layer formed with a reverse bias extends in the lateral direction with a length corresponding to the breakdown voltage, and thus it is necessary to provide a longer drift layer. This means that the chip area is increased, but it is difficult to reduce the thickness because of process limitations (substrate cracking problem). With respect to the same problem, in the vertical device, it is only necessary to lengthen the drift layer vertically, that is, to increase the thickness of the substrate, and it is not necessary to increase the area of the active portion. For this reason, it can be said that the vertical device is advantageous in terms of cost even at a high breakdown voltage. Therefore, the conventional lateral device is not suitable for high withstand voltage and large current applications.

  On the other hand, in the vertical power device, it is necessary to change the drift layer thickness in accordance with the breakdown voltage as described above. Higher voltage devices require thicker drift layers. In power devices, the drift layer thickness is almost the same as the thickness of the silicon substrate, such as NPT-IGBT (Non Punch Through IGBT), FS-IGBT (Field Stop IGBT), and diodes using FZ-n type silicon. The thickness of the silicon substrate is much thicker than the drift layer thickness, such as an epi-type IGBT or epi-type diode in which an epitaxial layer serving as a functional region is deposited on a support substrate having the same structure (the former) and high impurity concentration. There is a structure (the latter).

  In the case of a diode, in the former structure, a silicon substrate thickness of about 70 μm for a 600V withstand voltage product and about 110 μm for a 1200V withstand voltage product is a necessary thickness from the viewpoint of withstand voltage. However, such a thin silicon substrate is very easy to crack, and the cracking defect increases as it goes through a long manufacturing process. For this reason, when manufacturing a power device using, for example, a 6-inch silicon substrate, a silicon substrate having a thickness of about 500 μm is usually started regardless of the breakdown voltage class, and the process is started. By grinding and making the silicon substrate as thin as possible under the conditions that satisfy the semiconductor characteristics, we have devised to harmonize the problem of thin silicon substrate and silicon substrate cracking problem. This is because if a silicon substrate having a high specific resistance and a thickness of 500 μm is completed as a device, it becomes a device having a very high on-voltage for its withstand voltage class). On the other hand, in the latter structure, although there is a thick substrate layer under the drift layer, since this substrate layer is a low resistance layer, the entire silicon substrate is thick, but the on-voltage is kept low. Further, since the silicon substrate is thick, there is no concern about cracking during the process, but in such a structure, it is necessary to form an epi layer serving as a functional region on the thick substrate, so that there is a problem that the cost of the silicon substrate is high.

  For power devices with a breakdown voltage class of 3300 V or less (including most models), the required drift layer thickness is 500 μm or less, so in order to prevent crack defects during the process, Regardless of the structure (the former and the latter, that is, the structure where the back surface is ground in the final process, the episilicon substrate structure) in the model, the process flows as a thick silicon substrate of about 500 μm. As a result, in the former structure, most of the expensive silicon substrate purchased from the wafer manufacturer is thrown away in the final process by back grinding, and in the latter structure, a substrate layer that is not originally necessary for device characteristics is simply purchased as a support substrate. Will be. As described above, in the 600V diode, the thickness necessary for device operation is 70 μm, and the remaining thick substrate layer is a portion that is not necessarily required from the viewpoint of semiconductor characteristics.

To solve the above problems in the prior art, grooves are formed from both the front and back surfaces by shifting a predetermined distance in a direction parallel to the surface of the n-type substrate, and p ⁺ layers and n ⁺ layers are respectively formed on the inner surfaces of the grooves. It is a lateral device in which the current 103 flows in parallel to the main surface as shown in FIG. However, there is a document describing a diode that allows a current 103 to flow uniformly between electrodes without flowing near the surface (Patent Document 1 to FIG. 21, abstract).

  A plurality of parallelogram-shaped through-holes having a predetermined inner angle embedded in a vertical wall made of a (111) equivalent plane perpendicular to the main surface is formed in a single crystal silicon substrate having a plane orientation (110) surface as a main surface. A method of creating a hole according to a manufacturing method of a micromachine is disclosed (Patent Documents 2 and 3). A method is known in which an ink discharge chamber is formed by anisotropic etching in a single-crystal silicon substrate having a plane orientation (110) plane as a principal plane and is surrounded by a vertical wall composed of a (111) equivalent plane perpendicular to the principal plane. (Patent Documents 4 and 5).

A semiconductor in which an n-type silicon substrate having a (110) plane as a main surface is formed by anisotropic etching to form a groove having a {111} plane perpendicular to the main surface as a side wall, and a p-type silicon layer is embedded to form a pn junction. There is a description of the apparatus (Patent Document 6).
JP-A-6-53525 JP 2003-19700 A JP 2003-72088 A JP 2000-85121 A JP 2000-272137 A JP 2001-168327 A

  However, the invention described in Patent Document 1 relates to a device for a special application, and it is difficult to manufacture a large-area, large-current element. When an n substrate is used, the groove tip on the anode electrode side is used. It seems that the electric field concentrates on the part, the withstand voltage is greatly impaired, and the high withstand voltage element is also difficult. In the inventions described in Patent Documents 2 to 6, all of the n-type silicon substrate having the (110) plane as the main surface are anisotropically etched to form a groove having a {111} plane perpendicular to the main surface as a side wall. Although the description of the method of forming is recognized, the technical field is different from that of the semiconductor device in terms of the function of providing a groove having a {111} plane perpendicular to the formed main surface as a side wall, or Even a related document relates to a vertical semiconductor device having a current path in a direction between main surfaces of a semiconductor substrate, and a technical field of a horizontal semiconductor device having a current path in a direction parallel to the main surface of the semiconductor substrate. Is different.

  The present invention has been made in view of the above problems, and in a conventional lateral power device, when trying to obtain a high withstand voltage and high current device, the on-voltage and chip area are higher than those of a vertical device. Solved the problem of extremely disadvantageous and the problem that in the case of vertical power devices, most of the thickness of the semiconductor substrate to be input cannot be effectively utilized from the viewpoint of semiconductor characteristics due to problems in the manufacturing process. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can effectively use most of the thickness of the semiconductor substrate to be introduced into the manufacturing process for improving semiconductor characteristics.

  According to the first aspect of the present invention, the semiconductor substrate is composed of a laminated substrate in contact with the first and second conductivity type layers having a low impurity concentration, and one main layer on the first conductivity type layer side is formed. The surface has a first groove composed of a selective and periodic planar strip pattern and a depth perpendicular to the main surface and reaching the layer of the second conductivity type. A first electrode structure that is filled with an electrode layer and connected to the first electrode layer that is coated on the active region of the one main surface, and a semiconductor substrate that is positioned on the outer periphery of the first electrode structure A peripheral voltage-resistant structure portion to be formed, and the other main surface on the second conductivity type layer side is located between the first grooves, and a selective periodic periodic strip pattern and main surface A second groove composed of a depth perpendicular to the first conductivity type layer and surrounding the second groove and from the other main surface to the first conductivity type A pressure-resistant structure groove reaching the layer, and the second groove and the pressure-resistant structure groove are filled with the second electrode layer and connected to the second electrode layer covered on the other main surface. A semiconductor substrate having a second conductivity type high impurity concentration layer formed at least on a semiconductor substrate surface in contact with the first groove, and in contact with the second groove and the breakdown voltage structure groove The above object is achieved by providing a semiconductor device having a high impurity concentration layer of the first conductivity type formed at least on the surface and the other main surface.

According to the second aspect of the present invention, the high conductivity concentration layer of the second conductivity type is formed on one main surface in the active region. A semiconductor device is more preferable.
According to the present invention as set forth in claim 3, the first semiconductor substrate is deposited and grown on the second conductivity type semiconductor substrate. The semiconductor device according to claim 1 or 2 is preferably made of a conductive type epitaxial layer.

According to the present invention as set forth in claim 4, the semiconductor substrate made of a stacked body in contact with the first and second conductivity type layers is a second conductivity type semiconductor substrate and a first conductivity type semiconductor substrate. The semiconductor device according to claim 1 or 2 may be formed by bonding together.
According to the present invention as set forth in claim 5, the electrode layer is epitaxial polysilicon or metal conductor having a high impurity concentration, according to any one of claims 1 to 4. A semiconductor device is preferable.

According to the present invention as set forth in claim 6, the peripheral withstand voltage structure portion includes a structure for relaxing the electric field strength at the time of reverse bias, according to any one of claims 1 to 5. It is desirable to use a semiconductor device.
According to the present invention as set forth in claim 7, the semiconductor device according to claim 1, wherein a principal plane orientation of the semiconductor substrate is a (110) plane. Is preferable.

According to the present invention as set forth in claim 8, the angle formed by two adjacent sides of the semiconductor substrate is a parallelogram whose angle is 70 degrees to 71 degrees, or 109 degrees to 110 degrees. The semiconductor device according to claim 7 is more preferable.
According to the present invention as set forth in claim 9, when the semiconductor device according to any one of claims 1 to 8 is manufactured, the first and second grooves are made of an alkaline etching solution. The object of the present invention is achieved by a method for manufacturing a semiconductor device formed by anisotropic etching.

According to a tenth aspect of the present invention, a silicon oxide film or a silicon nitride film is used as an etching mask when the first and second grooves are formed by the anisotropic etching. Preferably, the method of manufacturing a semiconductor device according to claim 9 is included.
According to the present invention of claim 11, the etching is performed to form the first or second groove on both main surfaces of the semiconductor substrate whose main surface orientation is (110). The shape of the opening of the mask is a parallel strip shape in which the angle formed by two adjacent sides is 70 degrees to 71 degrees, or 109 degrees to 110 degrees, or a parallel strip of small pieces arranged in parallel, and Each parallelogram is arranged in a planar strip shape that is perpendicular to each side of the quadrilateral and whose direction along the main surface of the semiconductor substrate is <111> or an orientation of a mirror index equivalent to this direction. It is desirable to provide a method for manufacturing a semiconductor device according to claim 10, which has a groove forming step for etching.

According to the twelfth aspect of the present invention, the shape of the opening is a parallel four sides of small pieces arranged at an interval smaller than the diffusion depth of the first or second conductivity type high impurity concentration layer. Preferably, the method for manufacturing a semiconductor device according to claim 11 is a planar strip shape having a shape.
According to the present invention of claim 13, the semiconductor substrate surface in contact with the first groove by introducing the first or second conductivity type impurity into the first or second groove and the active region A second impurity type high impurity concentration layer formed on one main surface, a semiconductor substrate surface in contact with the second groove and the breakdown voltage structure groove, and a second main surface formed on the other main surface, respectively. More preferably, the method of manufacturing a semiconductor device according to claim 12 forms a high impurity concentration layer of one conductivity type.

According to the present invention, there are provided a semiconductor device and a method of manufacturing the same that can solve the above-described problems in the prior art and can effectively use most of the thickness of the semiconductor substrate to be input to the manufacturing process for improving the semiconductor characteristics. In other words, according to the present invention, a lateral power device having an effective active area larger than that of a vertical power device having the same chip area can be manufactured, and the characteristics per chip area of the power device are larger than those of the vertical device. Can be improved. By using a thick silicon substrate that does not have to worry about cracking, it is possible to obtain performance that surpasses that of a conventional thin silicon substrate vertical device. Of course, the characteristics per chip area are greatly improved as compared with the conventional lateral device. Moreover, since the breakdown voltage of the peripheral breakdown voltage structure can be designed larger than the breakdown voltage of the active region, a high breakdown voltage and a high avalanche resistance can be realized.

  1A and 1B are an enlarged cross-sectional view and a perspective view of a main part of a semiconductor device (chip) according to the present invention, and FIG. 1A is an enlarged cross-sectional view of a main part of the semiconductor device (chip) cut along line AA. FIG. 4 is a perspective view of a semiconductor device (chip) as viewed from the first electrode (anode) side, FIG. 4 is an enlarged cross-sectional view of a main part showing equipotential lines at the time of reverse bias of a diode according to the present invention, and FIG. FIG. 2 is a perspective view of a principal part of the semiconductor device according to the embodiment, and a perspective view, wherein (a) is a principal part enlarged cross section as seen from the second electrode (cathode) side of the semiconductor device (chip) cut along line AA. FIG. 6B is a perspective view of the semiconductor device (chip) as viewed from the second electrode (cathode) side, and FIG. 6 is a top view of the semiconductor device according to the present invention as viewed from the first electrode (anode) side. FIGS. 7A and 7B are main part sectional views for explaining the semiconductor device according to the present invention, 8 on the current density and the ON voltage relationship diagram for the diode of the prior art and the present invention, FIG. 9 is a main part sectional view on the arrangement of the electrode groove. FIG. 10 is a plan view showing a line intersecting the plane orientation (111) and its equivalent plane on the semiconductor substrate of the plane orientation (110) according to the present invention, and FIG. 11 is the cathode side of the semiconductor substrate according to the present invention. FIG. 12 is a plan view showing different alkali etching opening shapes on the cathode surface side of the semiconductor substrate according to the present invention, and FIG. 13 is a parallelogram according to the present invention. FIG. 14A, FIG. 14B, and FIG. 14C are cross-sectional views of relevant parts for explaining the semiconductor device according to the present invention.

(Expansion of effective active area in semiconductor device of the present invention)
A semiconductor device (chip) according to the present invention will be described in detail with reference to a diode having an electrode groove structure (7, 8) having a striped planar pattern shown in FIGS. FIG. 1A is an enlarged cross-sectional view of a main part showing a part of the semiconductor chip of the present invention cut along line AA in FIG. The semiconductor chip is a laminated substrate in which an n ⁻ layer 5 is formed by epitaxial growth on a semiconductor substrate made of a p ⁻ layer 6 and has a p ⁻ n ⁻ junction inside. p ^- layer 6 and the n ^- narrow groove from each of the surface toward the interior of the layer 5 (7,8) are both the p ^- n ^- is formed to a depth greater than the bonding. The pattern on each surface of the narrow grooves (7, 8) is a stripe shape as shown in FIG. Although the surface shown in FIG. 1B is the anode side, the cathode 8 stripe 8 pattern on the opposite side is the anode side stripe 7 so that the cathode side stripe 8 pattern is located between the anode side stripe 7 patterns. It is arranged with a little deviation. After the formation of the stripe grooves (7, 8) on both sides, a high impurity concentration p ⁺ layer 9 and a guard ring p ⁺ of the peripheral breakdown voltage structure region 13 are formed on the inner surface of the anode side stripe groove 7 and the surface of the n ⁻ layer 5 side. A layer (described later) is formed, and an n + layer 10 having a high impurity concentration and a peripheral breakdown voltage structure region (described later) are formed on the inner surface of the cathode-side stripe groove 8 on the opposite side and the surface on the p ⁻ layer 6 side. In FIG. 1B, the long side of the active region 4 where the anode electrode layer 2 is formed is indicated by a and the short side is indicated by b on the substrate surface. In FIG. 1, the anode electrode layer 2 and the cathode electrode layer 3 are respectively formed on both main surfaces of the silicon substrate, and at the same time, the electrode layers are filled in the grooves (7, 8) on both surfaces. Connected to layer 3 and integrated. However, in FIG. 1B, the anode electrode layer is omitted or made transparent in order to clearly show the pattern of the groove below the anode electrode.

  In the semiconductor device of the present invention, as described above, the area of the effective active region through which the current actually flows is increased as compared with the conventional horizontal device and vertical device, and thereby the characteristics per chip area of the power device are increased. Since it is characterized in that it can be greatly improved as compared with the vertical device, this will be described in detail below. As shown in FIG. 1A, a single stripe-shaped groove is used as a unit cell, and the cell pitch is Wc, the depth of the grooves (7, 8) is tt, the silicon substrate thickness is tw, and the groove (7 8) is Wt, and the length of each side of the active region 4 on the substrate surface of the chip is a and b. The drift layer thickness determined by the breakdown voltage class is td (that the drift layer thickness td changes corresponding to the breakdown voltage). The current path area (that is, the area of the active region 4) Av of the conventional vertical device is Av = a × b. On the other hand, the current path area Al (effective active region area Al) of the lateral device according to the present invention can be calculated as follows. The current path area per unit cell is b × (Wt / 2 + td + tt + Wt / 2) (the sum of the groove side surface and the silicon substrate surface). The number of unit cells in one chip is a / Wc, and Wc = Wt / 2 + td + Wt / 2. Since the effective active region area Al is the sum of the current path areas of all the cells, the effective active region area Al is Al = a × b × (Wt + td + tt) / (Wt + td). The ratio of the effective active area area Al of the lateral device according to the present invention to the active area Av of the conventional vertical device, ie, Al / Av, is expressed as (Wt + td + tt) / (Wt + td) or (Wt + tw) / (Wt + td) (the latter) Where td = tw−tt). In other words, it can be seen that the effect of the present invention increases as the ratio of the silicon substrate thickness tw to the drift layer thickness td increases in the conventional vertical diode. In other words, the lower the breakdown voltage product such as 600V, the smaller the drift layer thickness, and the greater the effect.

For example, in the case of a 1200V withstand voltage diode having a silicon substrate thickness of 500 μm, if td is 110 μm, tt is 390 μm, and Wt is 40 μm, Al / Av is 3.6, and an effective active area that is three times or more can be obtained.
In this way, by effectively utilizing the bulk part, which has hardly contributed to current in the conventional lateral device, as a current path, a device having a very large effective active region area compared to the conventional vertical device can be obtained. can do. This is because the semiconductor substrate area that was thrown away in the conventional vertical device can be effectively used without being thrown away. Further, the conventional backside grinding process required for making the on-voltage a practical value as a thin silicon substrate is unnecessary, and further, there is no fear of a silicon substrate cracking defect during the process.

(Electric resistance of contact electrode)
In the present invention, the grooves formed in the silicon substrate are filled with a low-resistance material serving as an electrode, whereby the current flowing in the lateral direction in the silicon substrate is taken out and collected in the vertical electrode grooves. Therefore, it is very important that the electrode material has good electrical conductivity. The electrical resistivity ρ of various materials at room temperature is shown below. The number after the electrode material indicates the specific resistance value.

Al (aluminum): 2.8 × 10 ⁻⁶ Ωcm
Cu (copper): 1.7 × 10 ⁻⁶ Ωcm
N ⁺ silicon (1 × 10 ¹⁹ cm ⁻³ doped): 6.3 × 10 ⁻³ Ωcm
N + silicon (1 × 10 ¹⁸ cm ⁻³ doped): 2.0 × 10 ⁻² Ωcm
The resistance of the buried electrode per groove is ρ × tt / (Wt × b). ρ is a resistivity (specific resistance). Since the current handled by one embedded electrode is 2 × J × b × (Wt + td + tt), the voltage drop Vcontact in the embedded electrode is J × ρ × (Wt + td + tt) × tt / Wt. In the above example (a 1200 V withstand voltage diode with a silicon substrate thickness of 500 μm, td is 110 μm, tt is 390 μm, Wt is 40 μm), J = 200 A / cm 2 and Vcontact is 0.29 mV in the case of an aluminum electrode. The on-voltage of the diode is about 1.5V, and the voltage drop of the buried electrode can be ignored. On the other hand, when the buried electrode is formed of n ⁺ single crystal silicon having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ , V contact is 0.66 V, which is a voltage drop that cannot be ignored. Therefore, the buried electrode is optimally made of metal. In the case of embedding doped silicon, it is desirable to increase the groove width.

(Cell pressure resistance)
The conventional lateral device structure having electrode grooves perpendicular to the substrate surface and parallel to each other has a problem that the electric field tends to concentrate at the tip of the electrode groove when the device is turned off, that is, when reverse voltage blocking is performed. For this reason, an avalanche breakdown occurs at the end of the groove, and there is a possibility that a sufficient breakdown voltage cannot be obtained. In the case of a diode having a stacked structure of p ⁺ layer / n ⁻ layer / n ⁺ layer, breakdown occurs at the tip curvature portion of the anode electrode groove, and a certain amount of electric field relaxation can be achieved by increasing the diffusion length of the anode p ⁺ layer. It is possible but not an essential solution. For example, when the junction depth of the anode p ⁺ layer is 3 μm, the breakdown voltage is about half that of the one-dimensional planar junction. That is, even if the flat junction has a withstand voltage of 1400V, the anode groove tip breaks down at 700V.

Therefore, in the present invention, as shown in FIGS. 1, 4 and 5, a laminated substrate of p ⁻ layer and n ⁻ layer is used as the semiconductor substrate, and the anode electrode groove is pn from the n ⁻ layer surface of the laminated substrate. By reaching the inside of the p ⁻ layer beyond the junction and forming the p ⁺ layer on the surface of the semiconductor substrate of the anode electrode groove, the electric field of the anode curvature portion can be relaxed, and as a result, a high breakdown voltage can be obtained. It was made to be able to. Since the depletion layer extends from the pn junction, the depletion layer does not begin to extend from the tip of the anode, and the electric field is relaxed. Furthermore, the electric field can be further relaxed by setting the distance between the anode tip and the silicon substrate cathode surface to be larger than the drift layer width td required for the design withstand voltage.

(About the peripheral pressure-resistant structure)
In the semiconductor device according to the present invention, as shown in FIGS. 4, 5, and 6, the anode side periphery located on the outer periphery of the anode electrode layer 2 (shown in FIGS. 4 and 5A) or the active region 4. As the breakdown voltage structure region 13, a conventional breakdown voltage structure including the guard ring 11 can be used. However, in the structure in which the cell breakdown voltage is improved by using a thick p ⁻ layer, an annular electrode groove having the same depth as the cathode electrode groove 8 is formed at a position corresponding to the outer periphery surrounding the active region 4 as shown in FIG. By forming the cathode side peripheral pressure resistant groove structure 12, it is necessary to electrically isolate the p ⁻ layer of the inner peripheral portion 19 and the outer peripheral portion 20 of the cathode side peripheral pressure resistant groove structure 12. Otherwise, the depletion layer extends from the pn junction exposed on the cut side surface 18 of the device (chip), and a large leakage current is generated on the side surface that is not subjected to appropriate surface treatment. FIG. 4 shows an equipotential line 14 when a reverse voltage is applied when such a guard ring 11 / field plate structure including an oxide film 21 is applied as the cathode side peripheral withstand voltage groove structure 12 and the anode side peripheral withstand voltage structure region 13. It is a principal part expanded sectional view described for convenience. In FIG. 5, an oxide film necessary for protecting the substrate surface in the peripheral voltage withstanding structure region 13 is omitted. Further, the cathode electrode 3 shown in FIGS. 5 (a) and 5 (b) is illustrated in a perspective manner so that the lower substrate surface pattern can be clearly shown. Since the main junction 15 indicated by the thick broken line is in the vertical direction (perpendicular to the main surface of the semiconductor substrate), the curvature of the equipotential line 14 in the anode-side peripheral breakdown voltage structure region 13 is unlikely to be convex, and the electric field is relaxed. It has become easier. In the peripheral withstand voltage structure region of the conventional planar type power device, the curvature of the equipotential line is always convex in the direction in which the depletion layer extends, and a breakdown voltage higher than that of the planar junction cannot be obtained. However, in the power device according to the present invention, in the peripheral withstand voltage structure region 13, the curvature of the equipotential line in the region where the electric field is strongest can be made concave toward the direction in which the depletion layer extends, and a breakdown voltage higher than that of the planar junction can be obtained. Is possible. For this reason, the entire device can be broken down at the main junction 15 of the active region 4, and a high breakdown voltage and a high avalanche resistance can be ensured. Note that the p ⁺ p ⁻ and n ⁺ n ⁻ junctions are indicated by thin broken lines 16 and 17, respectively, and reference numeral 18 denotes a cut surface when chipped.

  FIGS. 7-1 and 7-2 are examples in which the present invention is applied to a diode having a withstand voltage of 1200V. Specific resistance is 50 Ωcm, principal plane orientation (110) plane, OF (orientation flat) orientation <111> direction, 500 μm thick CZ-n type silicon substrate and specific resistance is 50 Ωcm and principal plane orientation (110) A 1 mm-thick laminated silicon substrate 1 bonded to a CZ-p type silicon substrate having a surface and OF orientation <111> direction and having a thickness of 500 μm is used as a material (FIG. 7-1 (a)). The bonding method follows a known method. Alternatively, a laminated silicon substrate in which a p-type silicon epilayer of 150 μm / 50 Ωcm is stacked on a CZ-n silicon substrate having the thickness of 850 μm and other specifications that are the same as the CZ-n type silicon substrate 1 may be used as a material. Unlike the conventional diode, the n layer side is the anode surface 1-1 and the p layer side is the cathode surface 1-2.

First, a thermal oxide film 1-3 having a thickness of 2.4 μm is grown on both surfaces of the silicon substrate 1. A part of the oxide film 1-3 on the cathode surface 1-2 is removed into a striped planar pattern by patterning and etching by a photolithography technique, and the silicon substrate 1 is deepened by alkali such as TMAH (tetramethylammonium hydroxide). An etching groove 8 of 800 μm is formed (FIG. 7-1 (b)). Since the crystal orientation of the main surface of the silicon substrate is the (110) plane, the (111) plane that is difficult to be etched remains as a side wall, and as a result, a vertical groove is formed. The groove width is 80 μm and the groove interval is 280 μm. Since the etching selectivity of the silicon substrate / oxide film is 500 or more and the reduction amount of the oxide film thickness is 1.6 μm, an oxide film of 0.8 μm remains. A mask alignment marker (not shown) is also formed by etching the silicon groove simultaneously with the etching of the silicon groove. Next, the entire oxide film 1-3 on the cathode surface 1-2 is removed by dry etching. By vapor phase diffusion of phosphorus, an n ⁺ layer 8-1 having a surface concentration of 1 × 10 ¹⁸ cm ⁻³ and a depth of 5 μm is formed inside the cathode electrode groove and on the flat portion of the cathode surface 1-2 (FIG. 7-1). (C)).

A resist is patterned on the peripheral pressure-resistant structure region 13 on the anode surface 1-1 using a double-side aligner, and a part of the oxide film 1-3 is etched. Similarly, a marker (not shown) is formed on the anode surface 1-1. Boron having a dose of 1 × 10 ¹⁴ cm ⁻² is ion-implanted to form the guard ring 11 (FIG. 7-1 (d)). When the double-sided aligner is not used, the silicon in the marker portion may be etched by 1000 μm prior to the silicon etching of the cathode surface, and the through hole may reach the anode surface, and this may be used as the anode surface marker.

An oxide film 1-4 having a thickness of 2.4 μm is grown again. Next, a part of the oxide film 1-4 on the anode surface 1-1 is removed by patterning and dry etching. Anode electrode grooves 7 having a depth of 800 μm and a width of 80 μm are formed at intervals of 280 μm by alkali etching. An anode groove 7 is formed between the two cathode grooves (8) (FIG. 7-2 (e)). The distance between the cathode groove 8 / the anode groove 7 is 100 μm. An oxide film having a thickness of 0.8 μm remains on the flat portion of the anode surface 1-1 between the anode grooves 7. Boron is doped by vapor phase diffusion to form a p ⁺ layer 7-1 having a surface concentration of 1 × 10 ¹⁷ cm ⁻³ and a depth of 3 μm. The p ⁺ layer 7-1 is not formed below the oxide film. The oxide films on both sides are completely removed with HF. An oxide film is formed on the anode surface by CVD. It is preferable that the oxide film is not formed on the trench sidewall as much as possible. The sidewall oxide film is removed with dilute HF. The oxide film on the anode side remains.

Aluminum is sputtered or vapor-deposited on the cathode electrode groove 8 and the anode electrode groove 7, and the groove is filled with metal. Alternatively, the groove may be embedded by plating. In order to fill a groove having a width of 80 μm, a filling amount of at least 40 μm is required. The aluminum layer on the cathode surface 1-2 is polished to leave an aluminum layer of about 5 μm. The aluminum layer on the anode surface 1-1 is polished by CMP (Chemical Mechanical Polishing Device) and planarized using the oxide film 1-4 as a stopper (FIG. 7-2 (f)). Then, 5 μm of aluminum is sputtered. A part of the aluminum layer on the anode surface 1-1 is removed by patterning / etching, and the floating electrode 11-1 is formed on the guard ring 11 to form the peripheral breakdown voltage structure region 13 (FIG. 7-2 (g)). In the embodiment of the lateral power diode according to the present invention using FIGS. 7-1 and 7-2, unlike the above-described FIGS. 1, 4, and 5, a P ⁺ layer is formed on the surface (flat portion) of the silicon substrate. Instead, an anode electrode was formed through the oxide film. Such a configuration can also be adopted.

The carrier lifetime is controlled by performing electron beam irradiation and annealing at 350 ° C. for 1 hour. Ti / Ni / Au is vapor-deposited or sputtered on the aluminum electrode on the back surface (FIG. 7-2 (h)), and finally the chip is diced to complete the manufacturing process.
In this embodiment, the formation of the deep electrode groove depends on anisotropic etching with alkali. It is also possible to form grooves by dry etching. In the case of dry etching, the etching selectivity of the silicon substrate / oxide film is about 50 at most, so a very thick oxide film or thick film resist is required to form a deep groove.

  FIG. 8 is a comparison diagram of output characteristics of a conventional diode and a diode according to the present invention. When compared at the same forward voltage of 1.5 V, the diode according to the present invention can pass four times as much current as the conventional diode. In the conventional diode, the breakdown voltage of the planar junction of the active region 4 is 1374 V, and the breakdown voltage of the peripheral breakdown voltage structure region 13 is lower than this. In the diode according to the present embodiment, as shown in FIG. 4, the electric field strength is relaxed in the vicinity of the surface of the peripheral breakdown voltage structure region 13 as compared with the active region, so that breakdown occurs in the active region. This is because the breakdown voltage of the peripheral breakdown voltage structure portion is larger than that of the active portion. For example, with four guard rings (200 μm peripheral breakdown voltage structure width), a breakdown voltage of 1200 V or more can be secured.

  In this embodiment, the anode groove 7 and the cathode groove 8 are etched from both main surfaces of the silicon substrate. Although it is not impossible to form the anode groove 7 and the cathode groove 8 from the same surface, this case has the following problems. First, there are two types of metal electrodes, an anode electrode and a cathode electrode, on the same surface, which are arranged at intervals of about 100 μm to 200 μm, making it difficult to pull out the wire by wire bonding. Also, the etching rate ratio due to the direction of anisotropic etching is finite, the taper angle becomes 90 ° or less when trying to form a vertical trench, and the interval between the anode groove and the cathode groove depends on the position in the depth direction of the silicon substrate. Different. At td1 and td2 in FIG. 9A, td1 <td2. Since the drift layer width varies depending on the depth position of the silicon substrate, it is necessary to secure a predetermined groove interval on the outermost surface where the drift layer width is minimum in order to obtain a required breakdown voltage. Therefore, the drift layer width becomes thicker than necessary at a deep position of the silicon substrate, and the electric resistance increases. The current is biased near the surface of the silicon substrate having a small electric resistance, and the on-voltage increases when viewed as the whole device. Furthermore, when the groove is dug from the same surface, it is necessary to further increase the distance between the anode groove 7 and the cathode groove 8 on the surface of the silicon substrate, in addition to the above reason. When a reverse bias is applied, parallel equipotential lines such as the bulk region of the silicon substrate cannot be formed on the silicon substrate surface, and the surface always has a curvature. The electric field on the surface of the silicon substrate is inevitably larger than that in the bulk region of the silicon substrate, and breakdown is likely to occur. Therefore, the anode groove / cathode groove interval must be further separated in anticipation of this. As described above, formation of anode / cathode grooves from the same surface is disadvantageous in terms of device characteristics, and groove formation from both surfaces as shown in FIG. 9B is preferable.

  As described in the first embodiment, when anisotropic etching is performed on the principal plane orientation (110) plane of the silicon substrate with an alkaline etchant, trenches that are perpendicular to the principal plane and have a large aspect ratio can be formed. This is because the etching rate of the (110) plane is several hundred times greater than that of the (111) plane. However, when the layout of the etching mask is not appropriate, etching may proceed to the lower part of the mask (this is called side etching or under etching). In this case, various problems arise from the standpoint of process conditions such as the case where it cannot be compensated in advance by the mask pattern design and the difficulty of removing the residue in the trench.

In order to form a trench having a side wall of a {111} plane perpendicular to the main surface in the main surface orientation (110) plane of the silicon substrate, as shown in FIG. The mask pattern may be arranged on the (110) plane so as to be 53 degrees or 109.47 degrees.
In view of this, in the second embodiment, including a countermeasure for such a problem, a case where the present invention is applied to a diode having a withstand voltage of 600 V will be described. FIG. 11 shows a trench etching mask pattern on the cathode 200 side of the diode formed with the (110) plane as the main surface according to the second embodiment of the present invention. A solid line indicates the mask pattern 30 on the cathode side, and at the same time, a mask pattern 40 on the anode side that is not originally visible is intentionally indicated by a chain line. The mask opening (same as the etching mask pattern) is a trench pattern including a set in which parallelograms each having an angle a, b formed by two adjacent sides of 70.53 degrees or 109.47 degrees are connected to each other. It is configured. The anode side trench in the active portion has a shape in which parallelogram stripes are arranged in parallel. The opening width is 50 μm. The interval between the anode side opening and the cathode side opening in the active part was 100 μm in the sectional view of FIG. 7-2 (f), but in Example 2, it was 80 μm. Note that the number of trenches in the active portion shown in FIG. 11 is actually larger, but is omitted from several.

FIG. 12 shows a trench etching mask pattern 50 on the cathode 300 side of a different diode, which is formed with the (110) plane as the main surface according to the third embodiment. FIG. 12 is a plan view in which a cathode side trench pattern 50 is configured as a plurality of parallelograms separated from mask openings, unlike FIG. By diffusing n ⁺ impurities (phosphorus) from within each parallelogram trench surrounding the chip periphery, the formed diffusion layers are connected to each other so that the periphery of the active portion is surrounded by a continuous n ⁺ layer. The active portion inside the annular n ⁺ layer is formed in a pseudo stripe shape with a plurality of parallelograms. FIG. 12 also shows only two pseudo stripes as in FIG. 11, but there are actually many more. The n ⁺ layers formed by diffusion from the inner surface of the trench are not necessarily connected to each other. In addition, since the parallelogram-shaped trenches shown in FIG. 12 are all formed in the same shape in principle, after the diffusion from the trenches described above, in the electrode metal filling process, the in-plane variation of the silicon substrate during vapor deposition or sputtering can be ignored. For example, all trenches can be filled at the same time.

  FIG. 13 shows an example in which the mask side is formed by a parallelogram having a similar shape on the cathode side. The trench in the active portion is similar to the trench in the outer periphery of the chip. In order to reduce the ineffective area of the chip as an active area, the silicon substrate itself corresponding to the chip is formed into a parallelogram similar to the mask opening. Accordingly, the dicing lines for cutting the wafer into diode chips are not orthogonal but intersect at an angle of 70.53.

  In the above Examples 2, 3, and 4, when trench etching is performed using an etching mask pattern made of a silicon oxide film, a trench having a shape according to the designed oxide film mask pattern without side etching (under etching) can be formed. .

  FIGS. 14-1, 14-2 and 14-3 are examples in which the present invention is applied to a diode having a withstand voltage of 600V. The specific resistance is 20 Ωcm, the principal plane orientation (110) plane, the OF orientation <1-1-1>, <1-11>, <-11-1> or <-111>, and the thickness A laminated silicon substrate in which a p-type silicon epitaxial layer 402 having a specific resistance of 60 Ωcm and a thickness of 100 μm is stacked on a 495 μm 6-inch CZ-n type silicon substrate 401 is used. This laminated silicon substrate requires a double-sided mirror finish. Each thickness is a numerical value after finishing a double-sided mirror. First, a thermal oxide film (initial oxide film) 403 having a thickness of about 4500 to 9000 mm is grown on both surfaces of the laminated silicon substrate. Since pinholes in the thermal oxide film 403 become a problem during subsequent silicon etching, it is necessary to form a high-quality oxide film having no pinholes (FIG. 14-1 (a)).

The silicon substrate 401 serving as the anode side, a p ⁺ guard ring region 404 serving as a pressure-resistant structure, the part of the oxide film 403 on the anode surface is removed in an annular by patterning and etching by photolithography, ion implantation of boron To form. Although not shown, alignment markers are simultaneously formed on the anode surface during patterning and etching by this photolithography technique (FIG. 14-1 (b)).

At the same time that the p ⁺ guard ring region 404 is formed by activation and diffusion in an oxygen atmosphere, an oxide film is grown by 3000 mm to form a 12000 mm oxide film 403.
Next, the oxide film 403 is patterned on the basis of the alignment marker described above by double-sided alignment of the front and back surfaces of the silicon substrate (FIG. 14-1 (c)).
Next, the silicon substrate is anisotropically etched with a 5% -TMAH (tetramethylammonium hydroxide) aqueous solution at 80 ° C. to form grooves. The groove width is 50 μm and the groove depth is 520 μm. Since the crystal orientation of the main surface of the silicon substrate is the (110) plane, the (111) plane that is difficult to be etched remains as a side wall, and as a result, a vertical groove is formed. The groove width is 50 μm and the groove interval is 75 μm (FIG. 14-1 (d)).

The distance between the groove formed from the anode surface and the groove formed from the cathode surface determines the width of the drift layer. Since the misalignment in the double-sided alignment results in variations in the drift layer width, the alignment accuracy at the 2 to 3 μm level is desirable. Since the selectivity between the oxide film and the (110) plane in the anisotropic etching exceeds 1: 1000, a 1 mm silicon groove can be dug with a 1 μm oxide film mask. After etching, the annular substrate end region in the periphery of the chip (p ⁺ outside of the guard ring region 404) supports the active region that has a bellows shape by grooves from both sides. Since the annular substrate end region has a continuous annular shape and has a sufficient thickness, the strength can be ensured. The etching pattern on the front and back surfaces is almost the same as the pointed object when viewed from the center of the substrate, and there is an oxide film with the same film thickness on the front and back surfaces, so the stress caused by the oxide film is offset and the silicon substrate Does not substantially warp.

  As described with reference to FIG. 10, when the (110) plane of the silicon substrate surface is viewed from above, there are two (111) planes perpendicular to the wafer plane. The angle a formed by the two (111) planes is 70.53 degrees and the angle b is 109.47 degrees. If the opening of the oxide film mask for etching is completely along the (111) plane, the groove shape as the mask can be obtained. However, if the shape deviates from the (111) plane, side etching under the mask occurs, and the corner undercut occurs instead of the shape according to the mask. If the groove width is widened by side etching, a problem of insufficient filling occurs in the subsequent metal filling step. If the mask is composed only of parallelograms with appropriate internal angles, there is no need for correction, and a groove shape according to the mask can be obtained (FIG. 11).

  In silicon etching, etching proceeds slightly in the (111) plane direction. It is about 1/180 of the etching rate of the (110) plane. Accordingly, when the (110) plane is etched by 520 μm, side etching of slightly less than 3 μm occurs also in the (111) plane. In the subsequent ion implantation process, a part of the groove side wall is shielded by the eaves, and the dopant is not implanted. In order to prevent this, it is necessary to remove the eaves of the oxide film.

If the etching selectivity of silicon and oxide film is 1000: 1, the oxide film thickness after etching is about 6600 mm. When the 3500 Å oxide film is removed with a dilute HF aqueous solution, the eaves portion is etched and removed completely from both sides, while the other portions are etched from one side, so that a 3100 Å oxide film remains. The remaining oxide film becomes a mask for ion implantation. If ions are implanted into the entire anode surface, the p ⁺ guard ring region 404 at the periphery of the chip is buried in a p ⁺ layer to be formed later, and does not function. Therefore, an ion implantation mask on the anode surface must be provided. Ions are implanted into the sidewall of the groove inside the electrode groove to form an anode layer and a cathode layer (FIG. 14-2 (e)).

  Since ions are implanted into the sidewalls of the high aspect ratio trenches, it is necessary to implant ions at an angle slightly below the normal to the silicon substrate surface (the optimum angle is determined by the aspect ratio). It is desirable to use a device with a high ion beam parallelism so that ions are not self-shielded by the position in the silicon substrate surface. In order to obtain a breakdown voltage, a dopant is also required at the bottom of the groove. For this purpose, ions may be implanted again vertically, but even with the oblique ion implantation for the side walls, the ions reach the bottom due to reflection on the side walls. Since ions are implanted at a shallow angle with respect to the groove sidewall surface, the sidewall surface effective dose amount is smaller than the dose amount with respect to the wafer surface.

Assuming that the beam dose is d-beam and the angle (injection angle) of the beam with respect to the vertical line of the silicon substrate is θ, the effective dose d-sidewall to the side wall is as follows. d-sidewall = d-beam sin θ and the maximum allowable value of θ is tan θmax = Wt / t _t . Above this angle, the dopant is not implanted into the side wall near the bottom due to the self-shielding effect of the groove.

For example, when t _t = 520 μm and Wt = 50 μm, the maximum implantation angle is 5.5 degrees, and the effective side wall dose at this time is 9.6% of the beam dose. If an effective dose of 7 × 10 ¹³ cm ⁻² is required, a beam dose of 7.3 × 10 ¹⁴ cm ⁻² is required. In order to suppress the dose variation due to the non-parallelism of the ion beam to ± 5%, a beam parallelism of 5% of 5.5 degrees, that is, ± 0.25 degrees is required.

An n ⁺ diffusion layer 405 and a p ⁺ diffusion layer 406 are formed by activation and diffusion at 1150 ° C. for 90 minutes. In order to ensure soft characteristics during reverse recovery, it is important to make the cathode groove dose larger than the anode groove dose. As a result, the bipolar carrier concentration at the time of conduction can be biased to the cathode, and the reverse recovery peak current can be suppressed. Furthermore, local lifetime control is effective to increase soft characteristics.

  Conventional vertical diodes perform platinum diffusion and effectively reduce the lifetime on the anode side by utilizing platinum accumulation on the device surface. Since platinum foil is used for introducing platinum, it is not suitable for introducing a lifetime killer into the groove of the diode as in this embodiment. In order to introduce platinum in the diode of this embodiment, platinum ion implantation into the anode groove is suitable. Thereafter, platinum is diffused at 800 to 900 ° C. to obtain a local lifetime effect.

In addition, in order to obtain the same effect as the two-stage drift layer in the conventional diode, it is possible to form a high doping concentration region by ion-implanting selenium into the cathode groove and diffusing by heat treatment at about 800 to 1000 ° C. . Thereby, the width of the drift layer can be further reduced.
In order to ensure good ohmic contact between silicon and metal, a 0.1 μm film of Al is formed in the groove. Further, in order to prevent diffusion of the buried metal to the silicon interface, a film of Ti is formed to a thickness of about 0.1 μm (FIG. 14-2 (f)).

A metal CVD apparatus for filling high aspect grooves is used. Next, the groove is filled with metal 407 (FIG. 14-2 (g)).
In the case of melting and embedding a metal, an In-based alloy having a melting point of about 400 ° C. is preferable. It is also possible to fill the groove with metal by applying a plating method or a metal CVD method. In order to fill a groove having a width of 50 μm, a metal film having a thickness of 25 μm may be grown. In metal embedding of high aspect grooves, voids are formed in the grooves if the embedding property is poor. However, from the viewpoint of device characteristics, it is sufficient if the metal film grown on the trench side wall is 5 μm, and it does not affect the on-voltage. However, it is necessary to completely close the opening of the groove. This is because if a resist or the like enters the groove in a patterning and etching process by a later photolithography technique, it causes contamination. Excess metal film on the anode surface is removed by CMP polishing (FIG. 14-3 (h)).

  If the initial oxide film 403 becomes a polishing stopper, the controllability is improved. If an embedded metal having an appropriate melting point is selected, the metal can be reflowed by a heat treatment at about 400 ° C. to improve the flatness before polishing, and the CMP polishing process becomes easy. Further, since extreme flatness is not required, it is possible to remove excess metal by etch back instead of CMP polishing. A 5 μm film of Al408 is formed on the anode surface. In order to form the anode surface breakdown voltage structure, Al is patterned and etched to form the field plate 409 (FIG. 14-3 (i)). Next, polyimide 410 is applied to the anode surface, and after pre-baking, patterning is performed to open the pad portion 411 (FIG. 14-3 (j)).

In any patterning, since the marker formed on the anode surface in advance can be used as an alignment marker, it can be formed without any problem by single-sided alignment. Next, a cathode electrode 412 is formed on the cathode surface by three-layer deposition of Ti / Ni / Au to complete the wafer (FIG. 14-3 (k)).
Simultaneously with the Al film formation on the anode surface, Al may be formed on the cathode surface, and a Ti / Ni / Au three-layered cathode electrode may be formed thereon. After auto-checking, dicing is performed to complete the chip.

Referring to the configuration diagram of the semiconductor device (chip) according to the present invention, (a) is an enlarged cross-sectional view of the main part of the semiconductor device (chip) cut along the line AA, and (b) is a perspective view of the semiconductor device (chip). , The principal part expanded sectional view of the conventional power device, The principal part expanded sectional view of the conventional power device, The principal part expanded sectional view of the conventional horizontal type device, The principal part expanded sectional view which shows the equipotential line at the time of reverse bias of the diode concerning this invention, 1 is a configuration diagram of the present invention, (a) is an enlarged cross-sectional perspective view of a main part of a semiconductor device (chip) cut along line AA, (b) is a perspective view of the semiconductor device (chip), The top view of the semiconductor device concerning the present invention, The principal part sectional view for explaining the principal part expanded sectional view of the semiconductor device concerning the present invention, The principal part sectional view for explaining the principal part expanded sectional view of the semiconductor device concerning the present invention, On-current density and on-voltage relationship diagram for conventional and inventive diodes, Cross-sectional view of relevant parts regarding the arrangement of electrode grooves The top view which shows the relationship between the trench side wall surface orientation and mask pattern of the semiconductor device concerning this invention, The top view which shows the mask pattern of the semiconductor device concerning Example 2 of this invention, FIG. 6 is a plan view showing a mask pattern of a semiconductor device according to Example 3 of the invention; FIG. 6 is a plan view showing a mask pattern of a semiconductor device according to Example 4 of the present invention; The principal part sectional view for explaining the principal part expanded sectional view of the semiconductor device concerning the present invention, The principal part sectional view for explaining the principal part expanded sectional view of the semiconductor device concerning the present invention, It is principal part sectional drawing for demonstrating the principal part expanded sectional view of the semiconductor device concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1-1 Anode surface 1-2 Cathode surface 1-3 Oxide film 1-4 Oxide film 2 1st electrode layer (anode electrode)
3 Second electrode layer (cathode electrode)
4 Active region on substrate surface 5 n ^- layer 6 p ^- layer 7 First groove (anode side groove)
8 Second groove (Cathode side groove)
9 p ⁺ layer 10 n ⁺ layer 11 Guard ring 12 Peripheral breakdown voltage groove structure 13 Peripheral breakdown voltage structure region 14 Equipotential line 15 p ⁺ n ⁻ Junction 16 n ⁺ n ⁻ Junction 17 p ⁺ p ⁻ Junction 18 Cut surface 19 Inner circumference 20 outer periphery.

Claims (13)

The semiconductor substrate is a laminated substrate in contact with the first and second conductivity type layers having a low impurity concentration, and a selective periodic periodic strip pattern and main surface on one main surface on the first conductivity type layer side. And a first groove constituted by a depth reaching the layer of the second conductivity type, the first groove being filled with the first electrode layer and the active region of the one main surface A first electrode structure connected to the layer of the first electrode layer coated thereon, and a peripheral withstand voltage structure portion formed on a semiconductor substrate located on the outer periphery of the first electrode structure;
The other main surface on the second conductivity type layer side is located between the first grooves, and is a selective periodic periodic strip pattern and perpendicular to the main surface, the first conductivity type layer. A second groove configured to reach the first groove, and a pressure-resistant structure groove surrounding the second groove and reaching the first conductivity type layer from the other main surface, the second groove and the pressure-resistant structure And a second electrode structure connected to a layer of the second electrode layer that is filled with the second electrode layer and covered on the other main surface,
Having a second impurity type high impurity concentration layer formed at least on the semiconductor substrate surface in contact with the first groove;
A semiconductor device comprising: a first conductivity type high impurity concentration layer formed at least on a semiconductor substrate surface in contact with a second groove and the breakdown voltage structure groove. 2. The semiconductor device according to claim 1, wherein the second conductivity type high impurity concentration layer is formed on one main surface in the active region. 2. The semiconductor substrate made of a laminate in contact with the first and second conductivity type layers is made of a first conductivity type epitaxial layer deposited and grown on the second conductivity type semiconductor substrate. 2. The semiconductor device according to 2. The semiconductor substrate made of a stacked body in contact with the first and second conductivity type layers is formed by bonding the second conductivity type semiconductor substrate and the first conductivity type semiconductor substrate. 3. The semiconductor device according to 1 or 2. 5. The semiconductor device according to claim 1, wherein the electrode layer is epitaxial polysilicon having a high impurity concentration or a metal conductor. 6. The semiconductor device according to claim 1, wherein the peripheral withstand voltage structure portion includes a structure for relaxing electric field strength at the time of reverse bias. The semiconductor device according to claim 1, wherein a main surface orientation of the semiconductor substrate is (110). 8. The semiconductor device according to claim 7, wherein an angle formed by two adjacent sides of the semiconductor substrate is a parallelogram of 70 degrees to 71 degrees, or 109 degrees to 110 degrees. 9. The semiconductor device according to claim 1, wherein the first and second grooves are formed by anisotropic etching with an alkaline etchant. Production method. 10. The method of manufacturing a semiconductor device according to claim 9, wherein a silicon oxide film or a silicon nitride film is used as an etching mask when forming the first and second grooves by the anisotropic etching. In order to form the first or second groove on both main surfaces of the semiconductor substrate whose main surface orientation is (110), the angle between two adjacent sides of the opening shape of the etching mask is 70. It is a flat strip shape in which parallelograms or small parallelograms of degrees to 71 degrees or 109 degrees to 110 degrees are arranged, and each parallelogram is perpendicular to each side of the quadrilateral. 11. A groove forming step of etching in a planar strip shape in which the direction along the main surface of the semiconductor substrate is <111> or the orientation of the mirror index equivalent to this direction. The manufacturing method of the semiconductor device of description. The opening shape is a planar strip shape composed of parallelograms of small pieces arranged at intervals smaller than the diffusion depth of the first or second conductivity type high impurity concentration layer. 11. A method for manufacturing a semiconductor device according to 11. Second conductivity type formed respectively on the semiconductor substrate surface in contact with the first groove and one main surface in the active region by introducing the first or second conductivity type impurity into the first or second groove And a high impurity concentration layer of a first conductivity type formed respectively on the semiconductor substrate surface and the other main surface in contact with the second groove and the breakdown voltage structure groove. A method of manufacturing a semiconductor device according to claim 12.

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