JP5332376B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for achieving a p-type collector layer, an n-type buffer layer, and an n<SP>-</SP>-type drift layer with optimum design values without limitation in a wafer process, reducing an on-voltage in a low current region, obtaining an excellent on-voltage and a good turn-off loss characteristic, and providing excellent productivity, and also to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device includes: a low-concentration and thin p-type collector layer 1 and a comparatively low-concentration n-type buffer layer 2 arranged on the surface of a high-resistance p-type support substrate 101; and a second trench 11 reaching the p-type collector layer 1 from the backside of the support substrate 101 and a third trench 12 reaching the n-type buffer layer 2. The bottoms and side surfaces of the second and third trenches and the backside of the support substrate are continuously covered with a collector electrode 13. First and second insulating films 105, 106 are respectively and selectively formed on the surfaces of the support substrate 101 and the p-type collector layer 1. The formation places of the insulating films are set only in the neighborhood of a cut line positioned in the periphery of each semiconductor device chip and in the nearest circumference of the wafer. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device for high power and high power and a method for manufacturing the same. In particular, the present invention relates to a MOS type semiconductor device such as an IGBT having a control electrode formed on the surface of a semiconductor layer via an insulating film, and a method for manufacturing the same.

  In response to the recent demand for miniaturization and high performance of power supply equipment in the field of power electronics, power semiconductor devices have high breakdown voltage and large current, as well as low loss, high destruction resistance, and high speed performance. Focus is on improvement. In the 600V to 6500V class, in the high withstand voltage region, insulated gate bipolar transistors (IGBTs) occupy the mainstream of power semiconductor devices. In order to meet the above characteristics requirements, the improvement of characteristics particularly in the 600V to 1700V class There is something remarkable.

One of the major technologies that support the improvement of IGBT characteristics is the thin wafer technology. Hereinafter, the term “wafer” is sometimes used as a generic term for a semiconductor substrate before being put into a process or after being subjected to various processes. In this thin wafer technology, an FZ-n type silicon substrate having a thickness of about 500 μm is used, and first, an element structure including a MOS gate is formed on one main surface side of the wafer. After that, in the final stage of device fabrication, the device is thinned from the back surface of the wafer to an optimum thickness that can ensure device breakdown voltage and obtain sufficiently low loss characteristics. Impurities such as phosphorus and boron are ion-implanted from the back surface after wafer polishing to form an n ⁺ -type layer (FS layer or buffer layer) and a p-type layer (collector layer). When the collector electrode is formed on the surface of the p-type layer (collector layer), the main process of FS-IGBT using the thin wafer technique is completed. According to this FS-IGBT, excellent on-voltage-turn-off loss characteristics can be obtained (Patent Document 1).

The wafer process of the so-called punch-through IGBT before the thin wafer technology was born was an n ⁺ type designed in advance to an optimum thickness and impurity concentration on a low-resistance p-type silicon support substrate having a thickness of 300 μm to 500 μm. A thick wafer obtained by epitaxially growing a low resistance layer (hereinafter also referred to as an n-type buffer layer), a high resistance n ⁻ type layer (hereinafter also referred to as an n ⁻ type drift layer), etc. is maintained until the final process with the same thickness. An IGBT wafer was formed. In this punch-through type wafer process, as described above, the concentration and thickness of the n-type buffer layer and the high resistance n ⁻ type drift layer are optimally designed in advance, and the entire wafer thickness is also low resistance p ⁺ type silicon support Since the substrate is sufficiently thick, it hardly breaks during the wafer process and has excellent productivity. However, since the impurity concentration of the low resistance p ⁺ type silicon support substrate (hereinafter referred to as p ⁺ type substrate) is high and too thick, the efficiency of minority carrier injection during IGBT operation becomes extremely high. As a result, compared to the IGBT made by the wafer process using the thin wafer technology described above, the on-voltage-turn-off loss characteristics, etc., are very poor even if the electrical characteristics are adjusted by the lifetime control technology. It is known to have surface limitations.

In order to remove such a limitation on electrical characteristics, the p ⁺ type substrate is shaved from the back surface in the final stage of the punch-through type wafer process, and the remainder of the p ⁺ type substrate is about 1 μm, which is an extremely thin p type collector. A manufacturing method has also been proposed in which the on-voltage-turn-off loss characteristic is improved by reducing the minority carrier injection efficiency by leaving it as a layer. However, since the accuracy of wafer polishing is usually about ± 5 μm, the above-described manufacturing method in which backside polishing is added to the punch-through process, the p-type collector layer is completely polished after the wafer polishing due to the problem of polishing accuracy. The on-voltage may increase rapidly. On the other hand, the p-type collector layer remains thicker than the design value, and as a result, the turn-off loss increases, resulting in a very large variation in the generated loss characteristics. Furthermore, in this manufacturing method, since the wafer thickness is polished to a thickness of 60 to 70 μm in the final process, as in the thin wafer technique, after the p ⁺ substrate polishing, the wafer is broken when the back electrode is formed. There is no practical use.

That is, when the former thin wafer technology is applied, the concentration and thickness of the p-type collector layer, the n-type buffer layer (FS layer), and the high-resistance n ⁻ -type drift layer can realize optimum design values, but productivity is improved. In the case of the punch-through process using the latter epitaxial method, the productivity is excellent, but there is a feature that the electric characteristics of the device are limited and it is difficult to further improve the electric characteristics.

In addition, looking at the current-voltage characteristics of the IGBT, it is known that there is a region where no current flows when the collector-emitter voltage is in the range of 0V to 0.7V. This is because there is a built-in voltage between the low-resistance p-type collector layer, the low-resistance n-type buffer layer (FS layer), and the high-resistance n ⁻ -type drift layer, which sufficiently reduces the on-voltage in the low current region. It is a big cause that can not.

FIG. 39 is a cross-sectional view of a main part of a device called RC (Reverse Conducting) -IGBT using the FS-IGBT thin wafer technology. The RC-IGBT has a trench MOS gate structure including a p-type channel region 204, an n ⁺ -type emitter region 205, a gate insulating film (not shown) formed in the trench 208, a gate electrode 206, and the like on the surface side. . A part of the p-type collector layer 201 on the back surface side becomes the n-type buffer layer 202, and the n-type buffer layer (FS layer) 202 and the p-type collector layer 201 are short-circuited on the back surface side. In terms of an equivalent circuit, it can be said that a MOSFET is built in a part of the IGBT. This RC-IGBT is characterized in that a current can flow through the built-in MOSFET even in a region where the collector-emitter voltage is 0.7 V or less and the normal IGBT does not operate (Patent Document 2).

Further, the RC-IGBT has a structure in which the n-type buffer layer (FS layer) 202 and the p-type collector layer 201 are short-circuited on the back surface side, and the n ⁻ -type drift layer 203 is further connected to the main substrate of the semiconductor substrate. An IGBT is described that combines a superjunction structure in which an n layer and a p layer perpendicular to the surface have a stripe-like planar pattern and are alternately arranged adjacent to each other in a direction parallel to the main surface. The literature is open to the public. According to this patent document, a low on-voltage and high-speed switching can be achieved even in an IGBT having a medium to low breakdown voltage (Patent Document 3).
Japanese Patent No. 3885598 US2007 / 0231973 (FIG1) JP 2003-303965 A

  However, for the FS-IGBT described in Patent Document 1, in order to ensure device breakdown voltage and achieve low loss characteristics, the thickness after polishing the wafer is a device with a breakdown voltage of 600 V, approximately 60 μm to 70 μm, An element with a withstand voltage of 1200 V must be in a very thin state of 100 μm + α. In this situation, for example, if the wafer handling is performed with an 8-inch wafer and the process of ion implantation from the back surface and the electrode formation are advanced, there is a very high possibility that the wafer will break during the process. There is a problem that productivity is not improved easily.

In the case of the RC-IGBT described in Patent Document 2, for example, in the case of an IGBT with a withstand voltage of 600 V, the on-resistance of the MOSFET built in due to the collector short circuit structure has the characteristics of the MOSFET of 600 V with the 600 V withstand voltage element. If no action (or conductivity modulation) occurs, it becomes very high. Further, the FS-IGBT requires a low resistance FS layer (n ⁺ type layer) in order to achieve a thin wafer technology. However, when this FS layer is introduced, the RC-IGBT is less likely to cause an IGBT operation. A so-called “jump” phenomenon appears in the current-voltage characteristics in the direction, and the on-voltage cannot be sufficiently reduced.

  On the other hand, a superjunction structure described in Patent Document 3 is well known as a structure for reducing the on-resistance of a high voltage MOSFET. However, super-junction structure type MOSFETs (hereinafter abbreviated as SJ-MOSFETs) are usually formed from epitaxial wafers or wafers to which an epitaxial method is applied, so that epitaxial wafers or epitaxial methods are applied like thin wafer technology utilizing FZ wafers. It is extremely difficult to incorporate it in an IGBT that is manufactured without using it. For example, in the manufacturing method, the wafer process is extremely difficult, such as the creation of a substrate using trench etching and epitaxial growth, the design of a superjunction structure formed on the substrate, and the problem of alignment accuracy with the substrate. In particular, the IGBT described in Patent Document 3 has a shape in which the width of each pn layer of the superjunction layer is kept constant up to the p-type collector layer below the n-type buffer layer. There seems to be an increasing concern.

An object of the present invention is to optimize the concentration and thickness of a p-type collector layer, an n-type buffer layer (or FS layer), and an n ⁻ -type drift layer that affect the characteristics of a semiconductor device without restriction of the wafer process of the device. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can be realized by reducing the on-voltage in a low current region, have good on-voltage-turnoff loss characteristics, and have excellent productivity.

According to the first aspect of the present invention, in order to achieve the object of the present invention, a high-resistance p-type or n-type silicon support substrate and a silicon support substrate formed on the silicon support substrate are formed at a relatively low concentration. However, for example, a p-type collector layer having a higher concentration and thickness than that of the high-resistance p-type silicon support substrate and an n-type buffer layer having a higher concentration and a relatively small thickness are formed thereon. . Furthermore, a superjunction in which an n-type drift layer and a p-type partition layer formed in a stripe-like plane pattern in a direction perpendicular to the main surface of the substrate are alternately and repeatedly in parallel in a direction parallel to the main surface. A layer is formed. A p-type channel region selectively formed on the superjunction layer surface in a direction perpendicular to the stripe-like planar pattern; and an n ⁺ -type emitter region selectively formed on the surface of the p-type channel region. A first trench formed in a direction perpendicular to the stripe pattern of the superjunction layer at a depth penetrating the p-type channel region from the surface of the n ⁺ -type emitter region, and a gate on the inner surface of the first trench A gate electrode provided through an insulating film; and an emitter electrode in common contact with the surface of the p-type channel region and the surface of the n ⁺ -type emitter region. The other main surface side of the high-resistance silicon support substrate has a second trench and a third trench each having a depth reaching the p-type collector layer and the n-type buffer layer, respectively. The bottom of each of said second trenches and said third trench and the collector electrode to contact the side surface and the other main surface of the high resistance silicon support substrate, said first insulating film and said second insulating film is a high-resistance It is assumed that the semiconductor device is provided in a cutting region which is located at the outermost periphery of the semiconductor chips provided in a lattice shape on the silicon support substrate and is a region to be cut for semiconductor chip formation .

According to the invention of claim 2, wherein in the claims, at a depth where the first-conductivity-type partition layer reaches the second conductivity type semiconductor buffer layer from the surface of the second conductive type drift layer, a stripe-shaped The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by growing an epitaxial semiconductor layer in a trench having a planar pattern.
According to a third aspect of the present invention, the first conductivity type partition layer is in the second conductivity type drift layer and has a depth reaching the vicinity of the second conductivity type semiconductor buffer layer. The method of manufacturing a semiconductor device according to claim 1, wherein the epitaxial semiconductor layer is formed by growing an epitaxial semiconductor layer in a trench having a stripe-like planar pattern.

According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the n-type buffer layer is a layer having a lower resistance than the n-type drift layer.
According to a fifth aspect of the present invention, the ratio of the bottom area of the second trench to the third trench is 5: 1.

According to a sixth aspect of the present invention, the semiconductor device according to the first aspect of the present invention is such that the n-type buffer layer is a layer having a higher resistance than the n-type drift layer.
According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, the trench bottom area ratio of the second trench to the third trench is 36: 1.

According to the invention described in claim 8, the short side widths of the stripe-like planar patterns of the p-type partition layer and the n-type drift layer each having the stripe-like planar pattern are different. It shall be the semiconductor device according to claim 1, wherein.

According to the invention of claim 9, wherein the range of patent claims, wherein the first insulating film and the second insulating film by using as an endpoint detector insulating film of trench etching, the third trench and the second trench A method of manufacturing a semiconductor device according to claim 1, which is formed in each of the claims.

According to the invention of claim 10 , the first insulating film having a predetermined shape and laminated on one main surface of the high-resistance silicon support substrate, and more than the high-resistance silicon support substrate, respectively. A low-resistance p-type collector layer. The first insulating film is a second insulating film having a predetermined shape provided at a position that does not overlap when viewed from above the main surface, the n-type buffer layer, and a direction perpendicular to the main surface, A p-type partition layer having a striped planar pattern at a virtual cut surface parallel to the main surface and a superjunction layer composed of an n-type drift layer are provided in this order. Selectively formed on the surface layer of the superjunction layer, p-type channel region formed in a direction perpendicular to the striped planar pattern of the superjunction layer, and selectively formed on the surface layer of the p-type channel region. N ⁺ -type emitter region. Gate insulation in a direction orthogonal to the stripe-like planar pattern of the super junction layer on the surface of the p type channel region sandwiched between the surface of the n ⁺ type emitter region and the surface of the n type drift layer of the super junction layer A gate electrode provided through a film; and an emitter electrode commonly in contact with the surface of the p-type channel region and the surface of the n ⁺ -type emitter region. The other main surface of the high-resistance silicon support substrate has a second trench and a third trench each having a depth reaching the p-type collector layer and the n-type buffer layer, respectively. E Bei said second trenches and each of the bottom and side surfaces and the collector electrode in contact with the other main surface of the high resistance silicon support substrate of the third trench, and the said second insulating film and the first insulating film, the semiconductor By providing a semiconductor device provided in a cutting region, which is located in the outermost periphery in each semiconductor device provided in a lattice shape in the support substrate and is a region for cutting each semiconductor device , the present invention The purpose of is achieved.

According to the invention of claim 11 wherein the appended claims, a depth where the first-conductivity-type partition layer reaches the second conductivity type semiconductor buffer layer from the surface of the second conductive type drift layer, a stripe-shaped 11. The method for manufacturing a semiconductor device according to claim 10 , wherein the epitaxial semiconductor layer is formed by growing an epitaxial semiconductor layer in a trench having a planar pattern.
According to a twelfth aspect of the present invention, the first conductivity type partition layer is in the second conductivity type drift layer and has a depth reaching the vicinity of the second conductivity type semiconductor buffer layer. The semiconductor device according to claim 10 , which is formed by growing an epitaxial semiconductor layer in a trench having a stripe-like planar pattern.

According to a thirteenth aspect of the present invention, in the semiconductor device according to the tenth aspect , the n-type buffer layer is a layer having a lower resistance than the n-type drift layer.
According to the invention described in claim 14 , the ratio of the bottom area of the second trench to the third trench is 5: 1, and the semiconductor device according to claim 13 is provided.

According to a fifteenth aspect of the present invention, in the semiconductor device according to the tenth aspect , the n-type buffer layer is a layer having a higher resistance than the n-type drift layer.
According to a sixteenth aspect of the present invention, in the semiconductor device according to the fifteenth aspect, the trench bottom area ratio of the second trench to the third trench is 36: 1.

According to the invention described in claim 17 , the short side widths of the stripe-like planar patterns of the p-type partition layer and the n-type drift layer each having the stripe-like planar pattern are different. It shall be the claims 10 semiconductor device according.

According to the invention of claim 18, wherein the range of patent claims, the third trench and the second trench, using respectively the first insulating film using the second insulating film as an end point detection dielectric film trench etching The method of manufacturing a semiconductor device according to claim 10 , wherein the semiconductor device is formed.

  The p-type collector layer is designed to have a low concentration and a relatively thin thickness in order to suppress minority carrier injection efficiency. The n-type buffer layer is designed to have a relatively low concentration in order to facilitate the IGBT operation. A second trench extending from the back surface of the high-resistance p-type silicon support substrate (hereinafter abbreviated as a high-resistance p-type support substrate) to the p-type collector layer and a third trench reaching the n-type buffer layer. The surfaces from the bottom and side surfaces of these second and third trenches to the back surface of the high resistance silicon support substrate are continuously covered with a metal conductor serving as a collector electrode. At this time, in order to make the bottoms of the second and third trenches accurately reach the p-type collector layer or the n-type buffer layer, a silicon oxide film is previously formed on the high-resistance p-type support substrate and the p-type collector layer. First or second insulating films represented by the above are respectively formed. These first and second insulating films are used for detecting an etching end point as an etching stopper when forming the second or third trench. At that time, if the first or second insulating film is formed in the active region that is a region through which the main current flows, it becomes a resistance at the time of current conduction, and the place to be formed is not related to the conduction of the main current, for example, It is formed only in a region where no element is formed in the vicinity of the cutting line located around each semiconductor device chip or in the outermost periphery of the wafer. The semiconductor device chip thus formed has a low injection characteristic with a small total amount of SJ-MOSFET and p collector layer in the chip, and a thin IGBT with a thin n-type buffer layer is integrated in the same element. . As for the electrical characteristics, the low on-resistance characteristics of the SJ-MOSFET are obtained in the low current region, and the low on-voltage characteristics are obtained by the favorable conductivity modulation of the IGBT optimally designed from the p-type collector layer to the n-type drift layer in the high current region. Further, since the high-resistance p-type silicon which is a thick support substrate is present in the entire wafer process, it is not broken during the process, and the productivity is excellent.

According to the present invention, the optimum design values of the concentration and thickness of the p-type collector layer, n-type buffer layer (or FS layer), and n ⁻ -type drift layer that affect the characteristics of the semiconductor device are not restricted by the wafer process of the device. Thus, it is possible to provide a semiconductor device that can reduce the on-voltage in a low current region, has good on-voltage-turnoff loss characteristics, and has excellent productivity, and a method for manufacturing the same.

Hereinafter, a trench gate type and a planar gate type insulated gate bipolar transistor of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
1A and 1B are plan views of a wafer showing a lattice arrangement of IGBTs including first and second dioxide films formed on the surface of the high-resistance p-type support substrate and the surface of the p-type collector layer of Examples 1 and 4 (a ) And an enlarged plan view (b) of the broken-line circle part of the plan view (a). 2, 3, 21, and 22 show the IGBT peripheral breakdown voltage structure and the active region in Examples 1 and 4 indicating that the second trench is in contact with the p-type collector layer and the third trench is in contact with the n buffer layer. FIG. 4 and 23 are cross-sectional views of the active region when FIGS. 3 and 22 are cut along the AA line or the DD line, respectively. FIGS. 5 to 7A and FIGS. 24 to 26 are cross-sectional views showing processes up to the formation of a superjunction layer in the IGBTs of Examples 1 and 4. FIGS. 7B and 7C are plan views after the formation of the super junction layer of the IGBTs of Examples 1 and 4. FIG. 8, FIG. 9, FIG. 27, and FIG. 28 are cross-sectional views of the peripheral breakdown voltage structure portion and active region of the IGBT after the formation of the IGBT superjunction layer according to the first and fourth embodiments. 10, FIG. 11, FIG. 29, and FIG. 30 are cross-sectional views of the device peripheral breakdown voltage structure and the active region after the trench forming oxide film mask is formed on the back surface of the IGBT high resistance p-type support substrate of the first and fourth embodiments. 12, 13, 31, and 32 are cross-sectional views of the peripheral breakdown voltage structure portion and the active region after the second trench and the collector electrode are formed on the back surface of the high resistance p-type support substrate of the IGBT according to the first and fourth embodiments. 14, FIG. 17, FIG. 35, and FIG. 37 are diagrams comparing the IV characteristics of the IGBTs produced in Examples 1, 2 and Examples 4, 5, the conventional thin wafer technology, and the conventional SJ-MOSFET. 15, FIG. 18, FIG. 36, and FIG. 38 are comparison diagrams of on-voltage-turn-off loss trade-off characteristics between the IGBTs produced in Examples 1, 2, and 4, 5 and the IGBTs produced using the conventional thin wafer technology. . FIGS. 16 and 33 are cross-sectional views of main parts showing active regions of the IGBTs of Examples 2 and 5. FIGS. 19 and 34 are cross-sectional views of the active region showing that the IGBTs of Examples 1 and 4 according to the present invention incorporate a diode connected in the reverse direction. FIG. 20 is a three-phase inverter circuit diagram to which the IGBT of the present invention is applied.

Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS. 1A to 15. In the first embodiment, a trench gate IGBT having a breakdown voltage of 600 V will be described.
1A is a plan view of an 8-inch diameter high-resistance p-type support substrate 101 used for forming the trench gate IGBT of Example 1 and a silicon oxide film 102 pattern formed on the high-resistance p-type support substrate 101. FIG. is there. Since the chip size is 6.8 mm square as shown in FIG. 1A (b), which is an enlarged view of the broken-line circle in FIG. 1A (a), the pattern of the lattice-like silicon oxide film 102 shown in FIG. 1A (a). The pitch is 6.8 mm. The element region 103 of the trench gate IGBT is formed in a 6.6 mm square surrounded by the pattern of the lattice-like silicon oxide film 102 having a width of 200 μm. A center line of the lattice-like silicon oxide film 102 having a width of 200 μm becomes a dicing line 104 when the wafer is separated into IGBT chips by dicing.

2, 3, and 4 are schematic cross-sectional views of the trench gate IGBT according to the first embodiment. 2 is a cross-sectional view of the periphery of the trench gate IGBT, and FIG. 3 is a cross-sectional view of the active region of the trench gate IGBT. 4 shows a cross-sectional view taken along the line AA shown in FIG. As shown in FIGS. 2, 3, and 4, the trench gate IGBT according to the first embodiment is partially formed on the surface of the high resistance p-type support substrate 101 with the silicon oxide film 105 (FIG. 2A) and its silicon. A p-type collector layer 1 having a thickness of 3.0 μm and an impurity concentration of 3.0 × 10 ¹⁷ cm ⁻³ is provided on the oxide film 105. A silicon oxide film 106 (FIG. 2B) is further partially formed on the p-type collector layer 1 and an n-type buffer layer having a thickness of 2.0 μm and an impurity concentration of 2.0 × 10 ¹⁶ cm ⁻³ thereon. 2 At this time, the silicon oxide film 105 formed on the surface of the high resistance p-type support substrate 101 and the silicon oxide film 106 formed on the p-type collector layer are viewed from above the main surface of the high resistance p-type support substrate 101. Positions that do not overlap each other.

The n-type buffer layer 2 has a lower impurity concentration than the conventional n ⁺ -type buffer layer (FS layer) and a higher impurity concentration than the n ⁻ -type drift layer 3.
The n ⁻ type drift layer 3 has a thickness of 55 μm and contains phosphorus with an impurity concentration of about 4.0 × 10 ¹⁵ cm ⁻³ (FIG. 2). The n ⁻ type drift layer 3 is formed in a direction in which the p type partition layer 4 and the n ⁻ type drift layer 3 formed in a direction perpendicular to the main surface of the high resistance p type support substrate 101 are parallel to the main surface. The wafer has a super-junction layer composed of repeated stripe-like planar patterns that are alternately in contact with each other (FIG. 4). In FIGS. 2 and 3, the super junction layer is formed, but the p-type partition layer 4 does not appear due to the position of the cut surface.

A first trench 6 for forming a trench gate structure is formed on the surface layer of the super junction layer so as to be orthogonal to the super junction layers 3 and 4 (FIG. 3). A trench gate is formed by burying the inside of the first trench 6 with a gate electrode 5 through a gate insulating film (not shown). Formation of p-type channel region 7 and n ⁺ -type emitter region 8, interlayer insulating film (not shown) by BPSG for insulating gate electrode 5 and emitter electrode 9, and p-type channel region 7 and n ⁺ -type emitter region An emitter electrode 9 is formed in common contact with each surface of 8 (FIG. 3).

  On the back surface of the high resistance p-type support substrate 101, there are a second trench 11 and a third trench 12 that respectively reach the p-type collector layer 1 and the n-type buffer layer 2 from the front surface, and these second trenches 11. The collector electrode 13 is provided in contact with each inner surface of the third trench 12 and each bottom. The high resistance support substrate 101 may be a p-type substrate or an n-type substrate. At this time, in order to obtain the optimum element characteristics corresponding to the operating frequency such as the carrier frequency of the inverter to which the trench gate IGBT of the present invention is applied, for example, assuming that the carrier frequency of the motor driving inverter is 10 kHz, the p The area ratio of the collector electrode 13 in contact with the type collector layer 1 and the area of the collector electrode 13 in contact with the n-type buffer layer 2 is preferably set to 5: 1.

  In particular, in the case of the trench gate IGBT as in the first embodiment, the second trench 11 and the third trench 12 accurately reach the thin p-type collector layer 1 and the n-type buffer layer 2, respectively. is important. If the second trench 11 does not reach the p-type collector layer 1 accurately, the on-voltage deteriorates rapidly, and if the third trench 12 does not reach the n-type buffer layer 2 correctly, the SJ-MOSFET does not operate. This is because such a trouble occurs.

  Hereinafter, the manufacturing method of the trench gate IGBT according to the present invention will be described in detail with reference to FIGS. As shown in FIG. 5, first, a high resistance p-type support substrate 101 having a thickness of 500 μm and a diameter of 8 inches is prepared, and a silicon oxide film is formed thereon to a thickness of 0.2 μm. Thereafter, the silicon oxide film 105 is formed by patterning so as to leave an oxide film in a lattice pattern with a pitch corresponding to the chip size to be formed as shown in FIG. 1A (a). As shown in FIG. 1A (b), the oxide film width in the vicinity of the cutting line by dicing of two sides out of the four sides according to the chip size in Example 1 was set to 100 μm.

On this, as shown in FIG. 6, a p-type collector layer 1 having a thickness of 3.0 μm and an impurity concentration of 3.0 × 10 ¹⁷ cm ⁻³ is deposited using an epitaxial method which is a well-known technique. When the collector layer 1 is formed as thin as possible, the hole injection efficiency can be reduced. This is preferable, but the thickness is set to 3.0 μm in consideration of variations in the concentration and thickness in the wafer surface. At this time, boron was used as an acceptor impurity. Thereafter, similarly to the silicon oxide film 105 formed on the high resistance p-type support substrate 101, a silicon oxide film 106 having a width of 100 μm is formed in the vicinity of the cutting line by dicing. At this time, it is formed on the other two sides so as not to overlap the two sides on which the oxide film 105 is formed. An n-type buffer layer 2 having a thickness of 2.0 μm and an impurity concentration of 2.0 × 10 ¹⁶ cm ⁻³ is formed thereon by epitaxial growth.

Different methods for forming the oxide films 105 and 106 at positions that do not overlap each other when viewed from above the substrate 101 will be described below. For example, as shown in FIG. 1B, the silicon oxide film 105A having a size of about 1 cm ² is formed on the surface of the high-resistance p-type support substrate 101 in the wafer peripheral region in the left half of the wafer where no element is formed, Similarly, a silicon oxide film 106A may be formed on the surface of the p-type collector layer 1 in the wafer peripheral region on the right half of the wafer where no element is formed. Thereafter, an n ⁻ type drift layer 3 containing about 4.0 × 10 ¹⁵ cm ^{−3 of} phosphorus is epitaxially grown to a thickness of about 55 μm (FIG. 6).

Next, an oxide film (not shown) having a thickness of 1.6 μm is grown on the surface of the n ⁻ -type drift layer 3, and an oxide film mask having a 4 μm width stripe pattern is formed at a pitch of 4 μm by photolithography and etching. To do. Using this oxide film mask, a trench reaching the n-type buffer layer 2 from the surface is formed by anisotropic etching. Thereafter, p-type silicon containing boron at a concentration similar to that of the n ⁻ -type drift layer 3 is buried in the trench by epitaxial growth, and further grown to be thicker than the oxide film mask.

Thereafter, CMP (Chemical Mechanical Polishing) and the by oxide etch n ^- when exposing the surface layer of the type drift layer 3 again, n ^- -type drift layer 3, p-type p-type silicon is buried in the trench The partition layer 4 becomes a super-junction layer formed by repeating stripe-like planar patterns that are alternately in contact with each other in a direction parallel to the main surface (FIG. 7A).

  Thereafter, first trenches 6 for trench gates are formed from the surface of the super junction layer to a depth of 4.5 μm at equal intervals with a width of 1.2 μm and a pitch of 5 μm. By sufficiently carefully forming the trench 6, the radius of curvature of the bottom of the trench 6 is 0.6 μm. As described above, in Example 1, as shown in the plan view of FIG. 7B, the first trench 6 and the superjunction layer are arranged in a plane pattern orthogonal to each other. Thereafter, as shown in FIG. 9, after a gate oxide film (not shown) having a thickness of 100 nm is grown in the first trench 6, polysilicon is deposited to form a buried gate electrode 5 in the first trench 6. To do.

Next, a p-type channel region 7 having a depth of about 2.5 μm is formed by ion implantation and thermal diffusion. Note that boron was used as the impurity at this time, the dose was 8.0 × 10 ¹³ cm ⁻² , the thermal diffusion temperature and time were 1150 ° C. for 2 hours. After that, arsenic is ion-implanted to a depth of 0.4 μm in order to form the n ⁺ -type emitter region 8 with a dose of about 5.0 × 10 ¹⁵ cm ⁻² . Thereafter, BPSG (Boro Phospho Silicate Glass) is deposited as an interlayer insulating film (not shown) to a thickness of 1.0 μm and patterned, followed by heat treatment (1000 ° C.). An Al-1% Si alloy to be the emitter electrode 9 is formed to a thickness of 5 μm by a sputtering method, followed by heat treatment after patterning (400 ° C.). After forming 10 μm-thick polyimide as a surface protective film (not shown) on the element surface, patterning is performed so as to open the emitter electrode 9 and the gate electrode pad portion (not shown), and heat treatment (300 ° C.) is performed. Form (FIGS. 8 and 9). The p-type partition layer 4 of the superjunction layer is not shown in the cross-sectional views of the active region in FIGS. 8 and 9 because the trench gate and the superjunction structure are formed orthogonally. This is because, in order to explain the trench gate structure, the figure is cut parallel to the super-junction layer.

  Next, an oxide film 10 having a thickness of 1.6 μm is grown on the back surface of the wafer, that is, the back surface of the high-resistance p-type support substrate 101, and an oxide film mask 10a for forming a trench is formed by photolithography and etching (FIG. 10, FIG. 11). This oxide film mask is 5 μm in the region where the oxide film 105 is formed on the high resistance p-type support substrate 101 of the peripheral voltage withstanding structure portion corresponding to two of the four sides of the chip shown in FIG. 1A (b). Although the width is evenly formed at intervals of 5 μm (FIG. 10A), the oxide film 106 is formed in the region where the oxide film 106 is formed on the p-type collector layer 1 corresponding to the other two sides even in the same peripheral breakdown voltage structure. The window is not opened (FIG. 10B). In the active region, an oxide film mask 10b is formed to leave a part of the oxide film mask width as wide as 100 μm (FIG. 11).

  Thereafter, trench etching is performed from the back surface of the wafer by anisotropic etching such as RIE. In Example 1, in order to shorten the trench etching time in a range in which the wafer is not broken in the subsequent wafer process, the etching is performed after polishing the back surface of the wafer having a thickness of about 500 μm to reduce the thickness to 250 μm in advance. Went. At this time, it is important to stop the etching accurately when the bottom of the second trench reaches the p-type collector layer. However, as described above, the thickness of the p-type collector layer is set to 3.0 μm to improve the electrical characteristics. Since it is set relatively thin, it is usually difficult to stop trench etching well. However, according to the present invention, the width is 100 μm between the high resistance p-type support substrate and the p-type collector layer, or the thickness is 0.2 μm in the region where no element is formed at the position of the outermost peripheral portion of the wafer. Since the silicon oxide films 105 and 106 are arranged, the silicon oxide film starts to be etched at the same time when the etching is advanced and the bottom of the second trench reaches the p-type collector layer. If the etching is stopped when oxygen is detected during the etching, the tip of the trench etching can be accurately stopped by the p-type collector layer (FIG. 12). Similarly, although not shown, a resist is applied after removing the back surface oxide film. This time, a part of the oxide region in the active region is left 100 μm wide, and a window of 5 μm wide is opened in the same manner as described above, and in the peripheral breakdown voltage structure portion, the region where the second trench is not dug is 5 μm wide. Oxide film patterns with an interval of 5 μm are formed. Thereafter, trench etching is performed by the RIE method in the same manner as described above, and this time etching is stopped when the bottom of the third trench (not shown) reaches the n-type buffer layer. Next, phosphorus is ion-implanted on the back side for the purpose of making an ohmic contact between the n-type buffer layer and the back side collector electrode. After removing the back surface oxide film, a metal laminated film of Al, Ti, Ni and Au is formed by vacuum deposition on the bottom and side surfaces of the second and third trenches and the entire back surface of the wafer. (FIG. 13). The main wafer process of the trench gate IGBT according to the present invention is completed by the manufacturing method described above. Since the silicon oxide film is formed with a width of 100 μm along the cutting line 104 by dicing, or is formed only on the outermost peripheral portion of the wafer, most of the second trench 11 and the third trench 12 are In the subsequent formation of the collector electrode 13, the p-type collector layer 1 or the n-type buffer layer 2 in the IGBT and the metal laminated film (collector electrode 13) can be reliably contacted. Therefore, the silicon oxide films 105 and 106 have no influence on current conduction. The trench gate IGBT is not applied at all with a lifetime control process for improving the switching speed, but may be subjected to a lifetime control process for optimizing device characteristics.

  100 pieces of 600V trench gate IGBT wafers with a diameter of 8 inches were created by the above-mentioned method, but it was found that there were no cracks in the wafer process until the end of the IGBT process, and the productivity was extremely excellent. did. For comparison, an 8-inch trench gate FS-IGBT was similarly formed using the above-described thin wafer technology using an FZ wafer. As a result, about 35 out of 100 wafers were cracked at a wafer thickness of 65 μm. This is because the wafer was handled after thin polishing or cracked during the impurity forming process on the back surface and the electrode forming process. In addition, the collector electrode 13 is formed by the vacuum deposition method in the above-described first embodiment. However, even if the collector electrode 13 is formed by another method, for example, a sputtering method or a plating method, 100 sheets of 8-inch wafers are used. It was confirmed that there were no cracks in the wafer.

FIG. 14 shows current-voltage characteristics of the trench gate IGBT element prepared in Example 1. For comparison, the characteristics of 600V SJ-MOFET and 600V trench gate FS-IGBT to which a thin wafer process is applied are also shown. It can be seen that the trench gate IGBT of Example 1 exhibits a sufficient current conduction capability close to that of a conventional SJ-MOSFET even when the collector-emitter voltage is between 0V and 0.6V. Further, it can be seen that in the vicinity of 300 A / cm 2 near the rated current, the low on-voltage characteristics are clearly superior to the SJ-MOSFET and comparable to the trench gate FS-IGBT. Thus, in the low current region where the current density is 50 A / cm ² or less, it is as good as SJ-MOSFET, and in the high current region where the current density is near 300 A / cm ^2, a good current equivalent to that of the trench gate FS-IGBT− It can be seen that the voltage characteristics are shown. The element of the present invention is 6.8 mm square, the element rating is 600 V / 100 A, and the rated current density is 300 A / cm ² . Furthermore, the switching characteristics of the present invention were also measured. As a result, the turn-off loss at a rated current of 100 A was measured and found to be 1.95 mJ. This is a reduction of 15% with respect to the turn-off loss 2.3 mJ of the compared trench gate FS-IGBT. Further, when the elements having different conditions were prepared and the characteristics were compared, as shown in FIG. 15, although it was slightly compared to the conventional trench gate FS-IGBT, it had a good characteristic that it had a low on-voltage and a low turn-off loss. I found out that In the trench gate IGBT of Example 1, the trade-off characteristic shown in FIG. 15 is that the concentration of the p-type collector layer is changed, that is, the impurity concentration is 4.0 × 10 ¹⁷ cm ⁻³ , 6.0 ×. This is the result of newly creating and evaluating a sample having a thickness of 10 ¹⁷ cm. Accordingly, the three-phase inverter circuit shown in FIG. 20 is configured using the trench gate IGBT of the first embodiment, and the generated loss is compared with the conventional trench gate FS-IGBT by driving the motor. The inverter operating conditions are as follows.

Vdc = 300 V, Io = 60 A (rms), carrier frequency fc = 10 kHz, output frequency fo = 50 Hz, cos θ = 0.9
As a result, the generated loss of the inverter using the trench gate IGBT of Example 1 was 47 W, which was about 25% lower than the generated loss 62 W of the inverter using the conventional trench gate FS-IGBT. Although this has a slight improvement in the trade-off characteristics shown in FIG. 15, the current conduction capability in the low current region is significantly improved as compared with the conventional trench gate FS-IGBT as shown in FIG. This is because the on-voltage in the region can be sufficiently reduced.

  In addition, the device breakdown voltage of the trench gate IGBT of Example 1 was 730 V, and it was confirmed that sufficient characteristics as a 600 V device were obtained, similar to the trench gate FS-IGBT (element breakdown voltage 726 V) in the conventional thin wafer process. Furthermore, when the maximum turn-off current and the load short-circuit withstand capability were also measured, it was confirmed that the characteristics were almost the same as those of the conventional trench gate FS-IGBT (the trench gate IGBT of Example 1: maximum turn-off current: 425 A, load short-circuit tolerance 18 μsec, conventional trench gate FS-IGBT: maximum turn-off current: 416 A, load short-circuit tolerance 16 μsec). The temperature at the time of measurement is 125 ° C.

  From this, it can be seen that the trench gate IGBT according to Example 1 has high productivity, and the trench gate IGBT formed thereby exhibits extremely good electrical characteristics.

  The second embodiment is formed under the same conditions as the first embodiment except that the MOS gate structure is a planar gate structure with respect to the trench gate structure of the first embodiment. Therefore, the wafer process of the planar gate IGBT of the second embodiment is almost the same as that described in the first embodiment, and the details are omitted. FIG. 16 is a cross-sectional view of the main part of the active region of the 600V breakdown voltage planar gate IGBT according to the second embodiment (the cross-sectional view of the peripheral breakdown voltage structure is the same as that of FIG. 2 and FIG. 3 of the first embodiment except for the MOS gate structure. So I will omit it). In Example 2, a p-type substrate was used as the high-resistance support substrate, but an n-type substrate may be used. As a result, 100 IGBT wafers with a diameter of 8 inches and 600V withstand voltage having a planar gate structure were produced. However, there was no breakage in the wafer process until the wafer process was completed. Turned out to be very good.

FIG. 17 shows current-voltage characteristics of the planar gate IGBT element prepared in the second embodiment. For comparison, the characteristics of the same 600V SJ-MOFET as used in Example 1 and the trench gate FS-IGBT using the thin wafer process are also shown. Compared with FIG. 14 of the first embodiment, the characteristics are slightly deteriorated by changing the trench gate structure to the planar gate structure. However, in the planar gate IGBT of the second embodiment, the voltage between the collector and the emitter is 0 V to 0. It can be seen that a sufficient current conduction capability close to that of the conventional SJ-MOSFET is exhibited even at 6V. Further, it can be seen that a low on-voltage characteristic comparable to that of the trench gate FS-IGBT is shown near 300 A / cm ² near the rated current. Thus, even in the planar gate structure, the current density is equal to that of the SJ-MOSFET in the low current region where the current density is 50 A / cm ² or less, and the same as the trench gate FS-IGBT in the high current region where the current density is near 300 A / cm ² . It can be seen that good current-voltage characteristics are exhibited. The planar gate IGBT of Example 2 is 6.8 mm square, the element rating is 600 V / 100 A, and the rated current density is 300 A / cm ² . Further, the switching characteristics of the planar gate IGBT of Example 2 were also measured. As a result, the turn-off loss at a rated current of 100 A was measured and found to be 1.72 mJ. This is a reduction of 28% with respect to the turn-off loss of 2.0 mJ of the compared trench gate FS-IGBT. Further, when the elements having different conditions were prepared and the characteristics were compared, as shown in FIG. 18, although it was slightly compared to the conventional trench gate FS-IGBT, it had a good characteristic that it had a low on-voltage and a low turn-off loss. I found out that In the planar gate IGBT according to the second embodiment, the trade-off characteristics shown in FIG. 18 are elements in which the concentration of the p-type collector layer 1 is changed, that is, the impurity concentration is 4.0 × 10 ¹⁷ cm, 6.0 × 10. ^This is the result of newly creating and evaluating a sample with ¹⁷ cm.

Therefore, similarly to the first embodiment, the planar gate IGBT of the second embodiment is used to construct the three-phase inverter circuit shown in FIG. 20 and drive the motor to compare the generated loss with the conventional trench gate FS-IGBT. The inverter operating conditions are as follows.
Vdc = 300 V, Io = 60 A (rms), carrier frequency fc = 10 kHz, output frequency fo = 50 Hz, cos θ = 0.9
As a result, the loss generated by the inverter using the planar gate IGBT of Example 2 was 55 W, which was about 12% lower than the loss generated by the inverter using the conventional trench gate FS-IGBT, 62 W. Although this has a slight improvement in the trade-off characteristics shown in FIG. 18, the current conduction capability in the low current region is significantly improved as compared with the conventional trench gate FS-IGBT as shown in FIG. This is because the on-voltage in the region can be sufficiently reduced.

  Further, the device breakdown voltage of the planar gate IGBT of Example 2 was 730 V, and it was confirmed that sufficient characteristics were obtained as a 600 V device, similar to the trench gate FS-IGBT (element breakdown voltage 726 V) in the conventional thin wafer process. Furthermore, when the maximum turn-off current and the load short-circuit withstand capability were also measured, it was confirmed that the characteristics were almost the same as those of the conventional trench gate IGBT (planar gate IGBT of Example 2: maximum turn-off current: 430A, Load short-circuit tolerance 20 μsec, conventional trench gate FS-IGBT: maximum turn-off current: 416 A, load short-circuit tolerance 16 μsec). The temperature at the time of measurement is 125 ° C.

  In the third embodiment, the trench gate IGBT described in the first embodiment is partially subjected to lifetime control. As a lifetime killer, helium was irradiated from the rear surface of the wafer to a position having a depth of 60 μm from the front surface side of the IGBT substrate. Since the wafer process conditions of the IGBT other than the lifetime killer irradiation are the same as those described in the first embodiment, a description thereof will be omitted. First, the on-voltage-turn-off loss trade-off characteristic is as high as an on-voltage of 2.2 V when helium is irradiated, but the turn-off loss is reduced to 1.8 mJ. Almost unchanged. Further, when the reverse recovery characteristic of the diode was measured, the reverse recovery time trr = 80 nsec, and the trr = 350 nsec when the lifetime killer was not included, became significantly faster. It can be seen that the reverse recovery characteristic of the diode is greatly improved by performing the lifetime control locally. This makes it possible to simultaneously improve the performance of the element configuration indicated by the broken-line circle in the three-phase inverter circuit of FIG.

  In Example 4, a trench gate IGBT having a breakdown voltage of 600 V will be described. 1A and 1B are plan views of an 8-inch diameter high resistance p-type support substrate 101 used for forming the trench gate IGBT of Example 4 and a patterned silicon oxide film formed thereon. Since the chip size is 6.8 mm square, the silicon oxide film is formed in a lattice shape with the dimensions shown in the figure. Since the description about FIG. 1A and FIG. 1B is the same as Example 1 mentioned above, the description beyond this is abbreviate | omitted.

21, 22, and 23 are schematic cross-sectional views of the trench gate IGBT according to the fourth embodiment. FIG. 21 is a sectional view of the peripheral breakdown voltage structure portion of the trench gate IGBT, and FIG. 22 is a sectional view of the active region of the trench gate IGBT. FIG. 23 is a cross-sectional view of the cross-sectional view of FIG. 22 taken along the line DD.
As shown in FIGS. 21, 22, and 23, the structure of the trench gate IGBT according to the fourth embodiment is such that the silicon oxide film 105 (FIG. 21A) is partially formed on the surface of the high resistance p-type support substrate 101. A p-type collector layer 21 having a thickness of 3.0 μm and an impurity concentration of 1.0 × 10 ¹⁷ cm ⁻³ is provided on the silicon oxide film 105. A part of the silicon oxide film 106 (FIG. 21B) is further partially formed on the p-type collector layer 21 and a low impurity such as a thickness of 3.0 μm and an impurity concentration of 2.0 × 10 ¹³ cm ^−3. The n ⁻ type buffer layer 22 has a concentration. In the fourth embodiment, the impurity concentration of the n ⁻ type buffer layer 22 is different from that in the first embodiment, and the impurity concentration is lower than that of the n ⁻ type drift layer 23 formed thereon. At this time, the silicon oxide film 105 formed on the surface of the high-resistance p-type support substrate 101 and the silicon oxide film 106 formed on the p-type collector layer 21 are viewed from above the main surface of the high-resistance p-type support substrate 101. So that they do not overlap each other. The method may be the same as the method shown in FIG. 2 described in the first embodiment. Further, different methods for forming the oxide films 105 and 106 at positions where they do not overlap each other when viewed from above the substrate 101 will be described below. For example, as shown in FIG. 1B, the silicon oxide film 105 having a size of about 1 cm ² is formed on the surface of the high-resistance p-type support substrate 101 in the wafer peripheral region in the left half of the wafer where no element is formed, Similarly, a silicon oxide film 106 may be formed on the surface of the p-type collector layer 1 in the wafer peripheral region in the right half of the wafer where no element is formed.

The n ⁻ type drift layer 23 contains phosphorus at an impurity concentration of about 6.0 × 10 ¹⁴ cm ^{−3 and} has a thickness of about 65 μm (FIGS. 21 and 22). The n ⁻ type drift layer 23 is a striped planar pattern in which a p type partition layer 24 formed in a direction perpendicular to the main surface of the substrate and an n ⁻ type drift layer 23 are alternately in contact with each other in a direction parallel to the main surface. (FIG. 23). The fourth embodiment is not a relatively high concentration n ⁺ -type buffer layer (FS layer) such as the trench gate FS-IGBT or RC-IGBT according to the conventional thin wafer technology. Unlike the n-type buffer layer in the IGBT, a high-resistance n ⁻ -type buffer layer 22 is formed. This does not cause the transition from the MOSFET operation to the IGBT operation due to the short-circuit structure on the back surface side of the p-type collector layer 21 and the n ⁻ -type buffer layer 22, for example, the above-mentioned “jump” of the IV characteristic. This is because the on-voltage is sufficiently reduced by performing the process smoothly. Further, since there is no n ⁺ type buffer layer (FS layer) like the above-described conventional trench gate FS-IGBT, there is no depletion layer stopper at the time of device breakdown voltage, and as a result, the n ⁻ type drift layer 23 becomes thick and the on-voltage is increased. There is concern that it will be higher. However, since the trench gate IGBT according to the fourth embodiment includes the super junction layer, the impurity concentration of the n ⁻ type drift layer 23 can be significantly higher than that of the normal IGBT. Therefore, a sufficient breakdown voltage can be maintained without the conventional high impurity concentration n ⁺ -type buffer layer (FS layer). In addition, the n ⁻ type drift layer 23 can be thinned (FIG. 23).

On the surface of the superjunction layer, as in the first embodiment, the first trenches 26 for forming the trench gate structure are arranged in a plane pattern orthogonal to the superjunction layers 23 and 24. A trench gate is formed by filling the inside of the first trench 26 with conductive polysilicon through a gate insulating film. The width of the trench gate is 1.2 μm and a depth of 3.0 μm. A polysilicon gate electrode 25 is embedded in the first trench 26 via a gate oxide film (not shown) having a thickness of 100 nm. Furthermore, a p-type channel region 27 and an n ⁺ -type emitter region 28 are formed, and a metal film made of Al-1% Si having a thickness of 5 μm is provided on the gate electrode as an emitter electrode 29 through an interlayer insulating film made of BPSG. . Furthermore, a polyimide layer with a thickness of preferably 10 μm is provided thereon. The p-type collector layer 21, the n ⁻ -type buffer layer 22, and the collector electrode 35 are provided on the back surface of the high resistance p-type support substrate 101. In Example 4, a p-type substrate was used as the high-resistance support substrate, but an n-type substrate may be used. At this time, the trench gate IGBT according to the fourth embodiment is applied. For example, in order to obtain optimum device characteristics depending on the operating frequency (carrier frequency of the inverter, etc.), the p-type collector layer 21 and the n ⁻ -type buffer layer 22 are provided. It is important to optimize the ratio of the collector electrode area in contact.

In Example 4, assuming that the carrier frequency of the inverter for driving the motor was 10 kHz, the area in contact with the p-type collector layer 21 and the n ⁻ -type buffer layer 22 was set to 36: 1.
In particular, in the case of the trench gate IGBT having the structure as in the fourth embodiment, if the bottom of the second trench 11 is not in contact with the p-type collector layer 21 accurately, the on-voltage is rapidly deteriorated. Also, if the bottom of the third trench 12 does not contact the n ⁻ -type buffer layer 22 accurately, problems such as the SJ-MOSFET not operating will occur. However, this is a point to watch out for in this manufacturing method.

Including this point, the manufacturing method of the trench gate IGBT according to the fourth embodiment will be described in detail with reference to FIGS. First, a high resistance p-type support substrate 101 having a diameter of 8 inches is prepared, and a silicon oxide film 105 is formed thereon with a thickness of 0.2 μm. Thereafter, the silicon oxide film 105 is formed by patterning so as to leave an oxide film according to the chip size to be formed (FIG. 24). In the fourth embodiment, as in the first embodiment, the width of the oxide film in the vicinity of the dicing line 104 (FIG. 27) on two sides out of the four sides according to the chip size is set to 100 μm. On this, a p-type collector layer 21 having a thickness of 3.0 μm and an impurity concentration of 1.0 × 10 ¹⁷ cm ⁻³ is formed by using an epitaxial method which is a well-known technique. This layer 21 is preferably formed as thin as possible to reduce the hole injection efficiency. Actually, the thickness was set to 3.0 μm in consideration of variations in concentration and thickness in the wafer surface. At this time, boron is used as an impurity. Thereafter, a silicon oxide film 106 having a width of 100 μm is formed in the vicinity of the dicing line 104 in the same manner as formed on the high resistance p-type support substrate 101. At this time, it is formed on the other two sides that do not overlap the two sides on which the oxide film 105 is formed. An n ⁻ type buffer layer 22 having a thickness of 3.0 μm and an impurity concentration of 2.0 × 10 ¹³ cm ⁻³ is formed thereon by an epitaxial method. As a method different from that of the fourth embodiment, as shown in FIG. 1B, the oxide film 105A and the oxide film 106A each having a size of about 1 cm ² are partially left in the wafer surface. ^The -type buffer layer 22 may be formed. Thereafter, as described above, the n ⁻ -type drift layer 23 containing about 6.0 × 10 ¹⁴ cm ^{−3 of} phosphorus is epitaxially grown to a thickness of about 65 μm (FIG. 25).

Next, an oxide film (not shown) having a thickness of 1.6 μm is grown on the surface layer of the n ⁻ -type drift layer 23, and an oxide film mask having a width of 4 μm is formed every 24 μm by photolithography and etching. A trench reaching the vicinity of the boundary with the n ⁻ type buffer layer 22 from the surface of the n ⁻ type drift layer 23 is formed by reactive etching. The depth of the trench was 50 μm. Thereafter, boron is doped as an impurity, and p-type silicon containing about five times the concentration of the n ⁻ -type drift layer 23 is epitaxially grown to be thicker than the oxide film mask to fill the trench. Then, by CMP (Chemical Mechanical Polishing) and oxide film etching, the n ^- when exposing the surface layer of the type drift layer 23 again, n ^- -type drift layer 23, p-type silicon is buried in the trench p A superjunction type semiconductor substrate having a superjunction layer composed of repeated stripe-like plane patterns alternately contacting with the mold partition layer 24 in the direction parallel to the main surface can be obtained (FIG. 26). In the case of a normal super-junction MOSFET, it is known that the p-type partition layer 24 and the n ⁻ -type drift layer 23 are formed at equal intervals. In this Example 4, in order to sufficiently reduce the on-voltage. The non-uniform spacing was as described above. The reason for this is that in the superjunction IGBT, when holes injected from the back surface p-type collector layer 21 pass through the p-type partition layer 24 to the emitter electrode, the p-type partition layer 24 is, for example, If designed at an equal interval of 4 μm, holes injected from the collector will immediately escape to the emitter, and sufficient conductivity modulation will not occur. As a result, the on-voltage cannot be sufficiently reduced. However, it is expected that a sufficient device breakdown voltage cannot be obtained unless the p-type partition layer 24 and the n ⁻ -type drift layer 23 are formed at equal intervals. However, by optimizing the impurity concentration of the n-type drift layer 23. It is designed to obtain a breakdown voltage of 600V or higher. After that, the trench gate was 1.2 μm wide and 3.0 μm deep, and was arranged in a planar pattern such that the first trench gate trench and the superjunction layer were orthogonal to each other as shown in FIG. 7C. In the fourth embodiment, the trench gate structure with unequal intervals as shown in FIG. 7C is used, but a normal trench gate structure with regular intervals as shown in FIG. 7B may be used. Further, by sufficiently carefully forming the first trench, the curvature of the bottom of the first trench can be formed with 0.6 μm. Thereafter, after the growth of a gate oxide film having a thickness of 100 nm on the inner surface of the first trench, a polysilicon gate electrode is embedded.

Next, a p-type channel region 27 having a depth of about 2.5 μm is formed using an ion implantation method and a thermal diffusion method. Boron is used as an impurity at this time, the dose is 8.0 × 10 ¹³ cm ⁻² , and the thermal diffusion temperature and time are 1150 ° C. and 2 hours. Thereafter, arsenic is ion-implanted at a dose of 5.0 × 10 ¹⁵ cm ⁻² to form an n ⁺ -type emitter region 28 to form a 0.4 μm deep layer. Thereafter, BPSG is deposited to a thickness of 1.0 μm as an interlayer insulating film (not shown), heat treatment after patterning (1000 ° C.), and Al-1% Si to be the emitter electrode 29 is formed to a thickness of 5 μm by sputtering. Similarly, post-patterning heat treatment (400 ° C.) is performed to form each. After forming polyimide (not shown) having a thickness of 10 μm as a surface protection film on the element surface, patterning is performed so as to open the emitter electrode 29 and the gate electrode pad portion (not shown), and heat treatment (300 ° C.) is performed. Form (FIG. 28). Further, although the superjunction layer is not shown in the sectional view of the active region of the trench gate IGBT of the fourth embodiment shown in FIG. 28, the trench gate and the superjunction layer are orthogonal to each other as in the first embodiment. This is because it is formed.

Next, an oxide film 31 having a thickness of 1.6 μm is grown on the back surface of the wafer, that is, the surface where the high-resistance p-type support substrate 101 is exposed, and an oxide film mask 31a for forming a trench is formed by photolithography and etching. (FIGS. 29 and 30). The oxide film mask 31a is equivalent to two of the four sides of the chip. In the region where the oxide film 105 is formed on the high resistance p-type support substrate 101 of the peripheral breakdown voltage structure portion, the oxide film mask 31a is evenly spaced at 5 μm width and 5 μm intervals. In the region where the oxide film 105 is formed on the p-type collector layer 21 corresponding to the other two sides even in the same peripheral breakdown voltage structure portion, no window is formed in the oxide film (FIG. 29B). ). In the active region, an oxide film region 31b is formed to leave a part of the oxide film width as wide as 100 μm (FIG. 30). Thereafter, trench etching is performed from the back surface of the wafer by anisotropic etching such as RIE. In Example 4, in order to shorten the trench etching time in a range where the wafer is not broken in the subsequent wafer process, the etching was performed after the back surface of the wafer was polished in advance to a thickness of 250 μm. At this time, it is important to stop the trench etching accurately when it reaches the p-type collector layer 21. However, as described above, the thickness of the p-type collector layer 21 is relatively as small as 3.0 μm in order to improve electrical characteristics. Since it is set thin, it is difficult to stop the trench etching well. However, according to the fourth embodiment, the IGBT chips are formed between the high-resistance p-type support substrate 101 and the p-type collector layer 21 at an interval of 100 μm in width or at the outermost peripheral portion of the wafer. Since the silicon oxide film mask 105A having a thickness of 0.2 μm is disposed in the non-existing region, the silicon oxide film 105 starts to be etched at the same time when the trench etching is advanced and the tip of the etching reaches the p-type collector layer 21. . If the etching is stopped when oxygen is detected during etching, it is possible to accurately stop the tip of the trench etching with the p-type collector layer 21 (FIGS. 31 and 32). After removing the back oxide film, a resist is applied. Next, an oxide film having a width of 5 μm is opened in the active region where a part of the oxide film width is left as wide as 100 μm, and a width is formed in a region where the third trench 12 is not dug in the peripheral breakdown voltage structure portion. Oxide film patterns are formed at 5 μm intervals of 5 μm. Thereafter, trench etching is performed by the RIE method in the same manner as described above, and this time etching is stopped when the n ⁻ type buffer layer 22 is reached. Here, phosphorus is ion-implanted for the purpose of making an ohmic contact between the n ⁻ -type buffer layer 22 and the back electrode. After removing the back surface oxide film, a metal laminated film of Al, Ti, Ni and Au is formed by vacuum deposition on the bottom and side surfaces of the third trench and the entire back surface of the wafer to form the collector electrode 35 (FIG. 31, FIG. 32). Thereby, the wafer process of the trench gate IGBT according to the fourth embodiment is completed. Since the silicon oxide film is formed with a width of 100 μm along the dicing line 104 or only on the peripheral portion of the wafer, most of the trenches are surely formed in the p in the device by forming the collector electrode 35 thereafter. The collector electrode 35 can be in contact with the surface of the type collector layer 21 and the surface of the n ⁻ type buffer layer 22. Therefore, the silicon oxide film has no influence on current conduction. Note that a lifetime control process for improving the switching speed is not applied to the trench gate IGBT, but a lifetime control process may be performed to optimize the device characteristics.

  By the method described above, 100 600V trench gate IGBT wafers having a diameter of 8 inches were prepared. However, no cracks were found in the wafer process until the IGBT was completed, and it was found that the productivity was excellent. did. For comparison, an 8-inch IGBT wafer was similarly produced using the above-described thin wafer technology using an FZ wafer. When the wafer thickness was 65 μm, about 35 out of 100 wafers were broken. This is because the wafer was broken during the wafer handling or in the middle of the impurity forming process on the back surface and the electrode forming process after thin polishing. In the above embodiment, the collector electrode 35 is formed by a vacuum deposition method. However, even if another method, for example, a sputtering method or a plating method is used, the wafer is cracked by 100 8-inch IGBT wafers. Confirmed that there was no.

FIG. 35 shows the current-voltage characteristics of the trench gate type IGBT prepared in Example 4. For comparison, the characteristics of a 600V SJ-MOFET and a 600V trench gate FS-IGBT using a thin wafer process are also shown. It can be seen that the trench gate IGBT of Example 4 exhibits a sufficient current conduction capability close to that of a conventional SJ-MOSFET even when the collector-emitter voltage is between 0V and 0.7V. It can also be seen that in the vicinity of 300 A / cm ² near the rated current, the low on-voltage characteristics are clearly superior to the SJ-MOSFET and comparable to the trench gate FS-IGBT. Thus, a good current-voltage equivalent to that of the SJ-MOSFET in the low current region where the current density is 50 A / cm ² or less and equivalent to the trench gate FS-IGBT in the high current region where the current density is near 300 A / cm ^2. It can be seen that the characteristics are shown. The trench gate IGBT of Example 4 is 6.8 mm square, the element rating is 600 V / 100 A, and the rated current density is 300 A / cm ² . Furthermore, the switching characteristics of the trench gate IGBT of Example 4 were also measured. As a result, the turn-off loss at a rated current of 100 A was measured and found to be 2.15 mJ. This means that a 6% reduction can be achieved with respect to the turn-off loss 2.29 mJ of the compared trench gate FS-IGBT. Furthermore, when an element with different IGBT process conditions was prepared and the characteristics were compared, as shown in FIG. 36, the device had a low on-state voltage and a low turn-off loss, although slightly compared to the conventional trench gate FS-IGBT. It turns out that it is a favorable characteristic. In the trench gate IGBT of Example 4, the trade-off characteristics shown in FIG. 36 are elements in which the impurity concentration of the p-type collector layer 21 is changed, that is, the impurity concentration is 2.0 × 10 ¹⁷ cm ⁻³ . It is the result of newly creating and evaluating what is set to 0 × 10 ¹⁷ cm ⁻³ . The three-phase inverter circuit shown in FIG. 20 was configured using the trench gate IGBT of Example 4, and the generated loss was compared with the conventional trench gate FS-IGBT by driving the motor. The inverter operating conditions are as follows. Vdc = 300 V, Io = 60 A (rms), carrier frequency fc = 10 kHz, output frequency fo = 50 Hz, cos θ = 0.9
As a result, the generated loss of the inverter using the trench gate IGBT of Example 4 was 46 W, and it was possible to reduce the generated loss 62 W of the inverter using the conventional trench gate IGBT by about 26%. As a result, there is a slight improvement in the trade-off characteristics shown in FIG. 36. However, as shown in FIG. 35, the current conduction ability in the low current region is remarkably improved compared to the conventional trench gate FS-IGBT. This is because the on-voltage in this region can be sufficiently reduced. Further, the trench gate IGBT element withstand voltage of Example 4 was 730 V, and it was confirmed that sufficient characteristics as a 600 V element were obtained, similar to the trench gate FS-IGBT (element withstand voltage 726 V) in the conventional thin wafer process. Furthermore, when the maximum turn-off current and the load short-circuit withstand capability were also measured, it was confirmed that the characteristics were almost the same as those of the conventional trench gate IGBT (the trench gate IGBT of Example 4: maximum turn-off current: 425A, Load short-circuit tolerance 18 μsec, conventional trench gate FS-IGBT: maximum turn-off current: 416 A, load short-circuit tolerance 16 μsec). The temperature at the time of measurement is 125 ° C. From this, it can be seen that the trench gate IGBT manufacturing method according to Example 4 has high productivity, and the trench gate IGBT formed thereby exhibits extremely good electrical characteristics.

Example 5 was created under the same conditions as Example 4 except that the gate structure was a planar gate. Therefore, since the wafer process is almost the same as that described in the first embodiment, details are omitted. FIG. 33 is a schematic cross-sectional view of the active region of the 600V breakdown voltage and planar gate IGBT according to the fifth embodiment (the cross-sectional view of the peripheral breakdown voltage structure is the same as that of the fourth embodiment, and is omitted). In Example 5, a p-type high-resistance support substrate was used, but an n-type high-resistance support substrate may be used. As a result, 100 600V IGBT wafers having a diameter of 8 inches were produced by the method described above, but there were no cracks in the wafer process until the main wafer process of the IGBT was completed. Similarly, it was found that the productivity was very excellent. FIG. 37 shows current-voltage characteristics of the planar gate IGBT produced in the fifth embodiment. For comparison, the characteristics of the same 600V SJ-MOFET as used in Example 1 and the trench gate FS-IGBT using the thin wafer process are also shown. Compared with the trench gate FS-IGBT of the fourth embodiment, the characteristics of the fifth embodiment are slightly deteriorated by the difference in the planar gate structure. However, the voltage between the collector and the emitter of the planar gate IGBT of the fifth embodiment is still 0V. It can be seen that a sufficient current conduction capability close to that of the conventional SJ-MOSFET is shown even between 0.7V and 0.7V. Further, it can be seen that a low on-voltage characteristic comparable to that of the trench gate FS-IGBT is shown near 300 A / cm ² near the rated current. As described above, even in the planar gate structure, the current density is as good as the SJ-MOSFET in the low current region where the current density is 50 A / cm ² or less, and the same as the trench gate FS-IGBT in the high current region where the current density is near 300 A / cm ^2. It can be seen that the current-voltage characteristics are excellent. The planar gate IGBT of Example 5 is 6.8 mm square, the element rating is 600 V / 100 A, and the rated current density is 300 A / cm ² . Furthermore, the switching characteristics were also measured in Example 5. As a result, as shown in FIG. 38, the turn-off loss at a rated current of 100 A was measured and found to be 2.00 mJ. Furthermore, when a planar gate IGBT with different conditions was created and the characteristics were compared, it had good characteristics of having a low on-voltage and low turn-off loss as compared with the conventional trench gate FS-IGBT as shown in FIG. I understood. In the planar gate IGBT of the fifth embodiment, the trade-off characteristics shown in FIG. 38 indicate that the concentration of the p-type collector layer is changed, that is, the impurity concentration is 2.0 × 10 ¹⁷ cm ⁻³ , 4.0 × 10. ^This is the result of newly creating and evaluating a ^sample with ¹⁷ cm ⁻³ .

Therefore, similarly to the fourth embodiment, the planar gate IGBT of the fifth embodiment is used to construct the three-phase inverter circuit shown in FIG. 20 and drive the motor to compare the generated loss with the conventional trench gate FS-IGBT. The inverter operating conditions are as follows.
Vdc = 300 V, Io = 60 A (rms), carrier frequency fc = 10 kHz, output frequency fo = 50 Hz, cos θ = 0.9
As a result, the generated loss of the inverter using the planar gate IGBT of the fifth embodiment is 53 W, which can be reduced by about 15% with respect to the generated loss 62 W of the inverter using the conventional trench gate FS-IGBT. This is because the trade-off characteristic shown in FIG. 38 is improved, but the current conduction capability in the low current region is significantly improved as compared with the conventional trench gate FS-IGBT as shown in FIG. This is due to the fact that the on-voltage at the time was sufficiently reduced. In addition, the device breakdown voltage of the planar gate IGBT of Example 5 was 730 V, and it was confirmed that sufficient characteristics were obtained as a 600 V device, similar to the trench gate FS-IGBT (element breakdown voltage 726 V) in the conventional thin wafer process. Furthermore, when the maximum turn-off current and the load short-circuit withstand capability were also measured, it was confirmed that the characteristics were almost the same as those of the conventional trench gate FS-IGBT (planar gate IGBT of Example 5: maximum turn-off current: 430A, load short-circuit tolerance 20 μsec, conventional trench gate FS-IGBT: maximum turn-off current: 416 A, load short-circuit tolerance 16 μsec). The temperature at the time of measurement is 125 ° C.

  In the sixth embodiment, the trench gate IGBT shown in the fourth embodiment is partially subjected to lifetime control. As a lifetime killer, helium was irradiated from the back surface of the wafer to a position 60 μm just from the device surface. The other IGBT creation process conditions are the same as those described in the fourth embodiment, and will be omitted. First, the on-voltage-turn-off loss trade-off characteristic is as high as an on-voltage of 2.2 V when helium is irradiated, but the turn-off loss is reduced to 1.8 mJ. As a result, the trench gate IGBT of the fourth embodiment Almost unchanged. When the reverse recovery characteristics of the diode were measured, it was possible to significantly increase the reverse recovery time trr = 80 nsec and trr = 350 nsec when the lifetime killer was not included. It can be seen that the reverse recovery characteristic of the diode is greatly improved by performing the lifetime control locally. As a result, it is possible to simultaneously improve the performance of the element configuration indicated by the circles in FIG.

  According to the first to sixth embodiments as described above, the productivity can be greatly improved while maintaining the same electrical characteristics as those of the trench gate FS-IGBT produced by the conventional thin wafer technology. Further, as shown in FIGS. 19 and 34, the IGBT according to the present invention can be considered to be a normal IGBT having a diode in the reverse direction indicated by a diode symbol. As a result, for example, in the three-phase inverter circuit shown in FIG. 20, what is conventionally configured by connecting the IGBT and the reverse diode as separate devices at the portion surrounded by the broken-line circle in the figure is the present invention. Therefore, both devices can be integrated as one device. By this integration, for example, a conventional IGBT module can be provided with the same function with half the required number of elements, so that the size of the module can be extremely reduced.

The top view (a) and broken line of a wafer which show the lattice-like arrangement | sequence of IGBT including the 1st, 2nd dioxide film formed on the high resistance p-type support substrate of Example 1, 4 concerning this invention, and a p-type collector layer It is an enlarged plan view (b) of a circle part. The top view of the wafer which shows the grid | lattice-like arrangement | sequence of IGBT containing the 1st, 2nd dioxide film formed in the different position on the high resistance p-type support substrate of Example 1, 4 concerning this invention, and a p-type collector layer (a ) And an enlarged plan view (b) of the broken-line circle part. It is sectional drawing of the periphery pressure | voltage resistant structure part of IGBT of Example 1 concerning this invention. It is sectional drawing of the active region of IGBT of Example 1 concerning this invention. It is sectional drawing cut | disconnected by the AA line of FIG. It is principal part sectional drawing (the 1) which shows the main manufacturing processes of IGBT of Example 1 concerning this invention. It is principal part sectional drawing (the 2) which shows the main manufacturing processes of IGBT of Example 1 concerning this invention. It is principal part sectional drawing (the 3) which shows the main manufacturing processes of IGBT of Example 1 concerning this invention. It is principal part sectional drawing (the 4) which shows the main manufacturing processes of IGBT of Example 1 concerning this invention. It is principal part sectional drawing which shows the main manufacturing processes of Example 4 concerning this invention. It is sectional drawing (the 5) of the periphery pressure | voltage resistant structure part which shows the main manufacturing processes of IGBT of Example 1 concerning this invention. It is sectional drawing (the 6) of the active region which shows the main manufacturing processes of IGBT of Example 1 concerning this invention. It is sectional drawing (the 6) of the periphery pressure | voltage resistant structure part which shows the main manufacturing processes of IGBT of Example 1 concerning this invention. It is sectional drawing (the 7) of the active region which shows the main manufacturing processes of IGBT of Example 1 concerning this invention. It is sectional drawing (the 7) of the periphery pressure | voltage resistant structure part which shows the main manufacturing processes of IGBT of Example 1 concerning this invention. It is sectional drawing (the 8) of the active region which shows the main manufacturing processes of IGBT of Example 1 concerning this invention. It is IV characteristic comparison figure of IGBT of 1st Example concerning this invention, FS-IGBT, and the conventional SJ-MOSFET. FIG. 6 is a characteristic comparison diagram between on-state voltage and turn-off loss of the IGBT, FS-IGBT, and conventional SJ-MOSFET of Example 1 according to the present invention. It is sectional drawing of the IGBT active region of Example 2 concerning this invention. It is a IV characteristic comparison figure of IGBT of Example 2 concerning this invention, FS-IGBT, and the conventional SJ-MOSFET. FIG. 6 is a characteristic comparison diagram between on-state voltage and turn-off loss of the IGBT, FS-IGBT, and conventional SJ-MOSFET of Example 2 according to the present invention. It is a figure which shows the reverse direction built-in diode of IGBT structure of Example 1 concerning this invention. It is the three-phase inverter circuit diagram which measured the loss by applying IGBT of Example 1 and Example 2 concerning this invention. Sectional drawing of the periphery pressure | voltage resistant structure part of IGBT of Example 4 concerning this invention. Sectional drawing of the active region of IGBT of Example 4 concerning this invention. FIG. 23 is a cross-sectional view taken along line DD in the cross-sectional view of FIG. 22. It is principal part sectional drawing (the 1) which shows the main manufacturing processes of IGBT of Example 4 concerning this invention. It is principal part sectional drawing (the 2) which shows the main manufacturing processes of IGBT of Example 4 concerning this invention. It is principal part sectional drawing (the 3) which shows the main manufacturing processes of IGBT of Example 4 concerning this invention. It is sectional drawing (the 4) of the periphery pressure | voltage resistant structure part which shows the main manufacturing processes of IGBT of Example 4 concerning this invention. It is sectional drawing (the 5) of the active region which shows the main manufacturing processes of IGBT of Example 4 concerning this invention. It is sectional drawing (the 5) of the periphery pressure | voltage resistant structure part which shows the main manufacturing processes of IGBT of Example 4 concerning this invention. It is sectional drawing (the 6) of the active region which shows the main manufacturing processes of IGBT of Example 4 concerning this invention. It is sectional drawing (the 6) of the periphery pressure | voltage resistant structure part which shows the main manufacturing processes of IGBT of Example 4 concerning this invention. It is sectional drawing (the 7) of the active region which shows the main manufacturing processes of IGBT of Example 4 concerning this invention. It is sectional drawing of the active region of IGBT of Example 5 concerning this invention. It is a figure which shows the reverse direction built-in diode of IGBT structure of Example 4 concerning this invention. It is IV characteristic comparison figure of IGBT of Example 4 concerning this invention, FS-IGBT, and the conventional SJ-MOSFET. FIG. 10 is a characteristic comparison diagram between on-state voltage and turn-off loss of the IGBT, FS-IGBT, and conventional SJ-MOSFET of Example 4 according to the present invention. It is IV characteristic comparison figure of IGBT of Example 5 concerning this invention, FS-IGBT, and the conventional SJ-MOSFET. FIG. 10 is a characteristic comparison diagram between on-state voltage and turn-off loss of the IGBT, FS-IGBT, and conventional SJ-MOSFET of Example 5 according to the present invention. The schematic sectional drawing of RC-IGBT which provided the n ⁺ type layer in a part of collector of trench FS-IGBT using the conventional thin wafer technique.

Explanation of symbols

1,21 p-type collector layer 2,22 n-type buffer layer 3,23 n ^- type drift layer 4,24 p-type partition layer 5,25 gate electrode 6,26 first trench 7,27 p-type channel region 8,28 N-type emitter region 9, 29 Emitter electrode 10, 31 Oxide film mask 11 Second trench 12 Third trench 13, 35 Collector electrode 101 High resistance p-type support substrate 102 Silicon oxide film 103 Element region 104 Dicing line 105 First insulating film 106 Second insulating film.

Claims (18)

A first insulating film having a predetermined shape, laminated on one main surface of the semiconductor support substrate, a first conductive semiconductor layer having a lower resistance than the semiconductor support substrate, and the first insulating film are the main insulating film A second insulating film having a predetermined shape provided at a position that does not overlap when viewed from above the surface, a second conductivity type semiconductor buffer layer, and a virtual cut in a direction perpendicular to the main surface and parallel to the main surface A first conductive type partition layer having a striped planar pattern on the surface and a superjunction layer comprising a second conductive type drift layer in this order, and a first conductive layer selectively formed on the surface layer of the superjunction layer -type channel region, a second conductivity type emitter region formed in a direction which selectively perpendicular to the stripe-shaped planar pattern of the previous SL superjunction layer on the surface layer of the channel region, the surface of the second conductive type emitter region Through the channel region A first trench formed in a direction perpendicular to the stripe-like planar pattern of the superjunction layer, a gate electrode provided on the inner surface of the first trench via a gate insulating film, the surface of the channel region, and An emitter electrode in common contact with the surface of the emitter region, and the other main surface of the semiconductor support substrate has a depth that reaches each of the first conductivity type semiconductor layer and the second conductivity type semiconductor buffer layer. and a two trench and the third trench, the bottom of each of said second trenches and said third trench and the collector electrode to contact the side surface and the other main surface of the semiconductor support substrate, said first insulating film The second insulating film is located at the outermost periphery in each semiconductor device provided in a plurality of lattices in the semiconductor support substrate, and is a cutting region that is a region for cutting each semiconductor device. Wherein a being eclipsed. At a depth where the first-conductivity-type partition layer reaches the second conductivity type semiconductor buffer layer from the surface of the second conductive type drift layer is formed by causing the trench stripe planar pattern growing an epitaxial semiconductor layer The method of manufacturing a semiconductor device according to claim 1. An epitaxial semiconductor layer is grown in a trench having a stripe-like planar pattern at a depth at which the first conductivity type partition layer is in the second conductivity type drift layer and reaches the vicinity of the second conductivity type semiconductor buffer layer. The method of manufacturing a semiconductor device according to claim 1, wherein the method is formed. 2. The semiconductor device according to claim 1, wherein the second conductivity type semiconductor buffer layer is a layer having a lower resistance than the second conductivity type drift layer. 5. The semiconductor device according to claim 4, wherein a trench bottom area ratio of the second trench to the third trench is 5: 1. 2. The semiconductor device according to claim 1, wherein the second conductivity type semiconductor buffer layer is a layer having a higher resistance than the second conductivity type drift layer. The semiconductor device according to claim 6, wherein a trench bottom area ratio of the second trench to the third trench is 36: 1. 2. The semiconductor device according to claim 1, wherein a short side width of each of the stripe-shaped planar patterns of the first conductivity-type partition layer and the second conductivity-type drift layer having the stripe-shaped planar pattern is different. 2. The semiconductor device according to claim 1, wherein the second trench and the third trench are formed using the first insulating film and the second insulating film as insulating films for detecting an end point of trench etching, respectively. Production method. A first insulating film having a predetermined shape, laminated on one main surface of the semiconductor support substrate, a first conductive semiconductor layer having a lower resistance than the semiconductor support substrate, and the first insulating film are the main insulating film A second insulating film having a predetermined shape provided at a position that does not overlap when viewed from above the surface, a second conductivity type semiconductor buffer layer, and a virtual cut in a direction perpendicular to the main surface and parallel to the main surface A superconducting layer composed of a first conductive type partition layer having a striped planar pattern and a second conductive type drift layer in this order, and is selectively provided on the surface layer of the superjunction layer. A first conductivity type channel region formed in a direction orthogonal to the stripe-shaped planar pattern; a second conductivity type emitter region selectively formed in a surface layer of the first conductivity type channel region; and the second conductivity type Of the surface of the emitter region and the superjunction layer A gate electrode provided through a gate insulating film in a direction perpendicular to the stripe-like planar pattern of the superjunction layer on the surface of the channel region of the first conductivity type sandwiched between the surface of the second conductive layer and the channel region; An emitter electrode that is in common contact with the surface and the emitter region surface, and the first main surface of the semiconductor support substrate has a depth that reaches the first conductivity type semiconductor layer and the second conductivity type semiconductor buffer layer, respectively. It has two trenches and third trenches, e Bei said second trench and the third trench bottom and side and the other of the collector electrode in contact with the main surface of the semiconductor support substrate, the second insulated from the first insulating film A film is located at the outermost periphery in each semiconductor device provided in a lattice form in the semiconductor support substrate, and is in a cutting region that is a region for cutting each semiconductor device. Wherein a being eclipsed. At a depth where the first-conductivity-type partition layer reaches the second conductivity type semiconductor buffer layer from the surface of the second conductive type drift layer is formed by causing the trench stripe planar pattern growing an epitaxial semiconductor layer The method of manufacturing a semiconductor device according to claim 10 . An epitaxial semiconductor layer is grown in a trench having a stripe-like planar pattern at a depth at which the first conductivity type partition layer is in the second conductivity type drift layer and reaches the vicinity of the second conductivity type semiconductor buffer layer. The method of manufacturing a semiconductor device according to claim 10 , wherein the method is formed. 11. The semiconductor device according to claim 10, wherein the second conductivity type semiconductor buffer layer is a layer having a lower resistance than the second conductivity type drift layer. 14. The semiconductor device according to claim 13, wherein a trench bottom area ratio of the second trench to the third trench is 5: 1. 11. The semiconductor device according to claim 10, wherein the second conductivity type semiconductor buffer layer is a layer having a higher resistance than the second conductivity type drift layer. 16. The semiconductor device according to claim 15, wherein a trench bottom area ratio of the second trench to the third trench is 36: 1. 11. The semiconductor device according to claim 10 , wherein the short side widths of the stripe-shaped planar patterns of the first conductivity type partition layer and the second conductivity type drift layer having the stripe-shaped planar pattern are different. 11. The semiconductor device according to claim 10 , wherein the second trench and the third trench are formed by using the first insulating film and the second insulating film as insulating films for detecting the end point of trench etching, respectively. Manufacturing method.

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