JP4955224B2 - Decision feedback equalizing input buffer - Google Patents

Description

  The present invention relates to an input buffer, and more particularly to a decision feedback equalizing input buffer, a memory having the same, and a memory system.

  In communication between integrated circuit systems, timing errors and voltage errors generated from transmission signals between chips are inevitably generated. A common cause of such errors is inter-symbol interference (ISI) caused by channel bandwidth limitations. Intersymbol interference (ISI) must be minimized for high speed communication between chips.

  Decision feedback equalizing (DFE) input buffers are used in conventional systems to reduce the detrimental effects of inter-symbol interference (ISI). However, the conventional decision feedback equalizer input buffer cannot effectively compensate for the timing error and voltage error caused by intersymbol interference (ISI) because the equalizing coefficient is fixed in the buffer.

  FIG. 1 is a waveform diagram showing the effects of timing errors and voltage errors caused by intersymbol interference. Waveforms A and B represent input signals received by the receiving circuit. Signal B represents a normal input signal received without intersymbol interference, and signal A represents an input signal containing an error affected by intersymbol interference. The error input signal A includes a timing error (TE) appearing in a timing delay form and a voltage error (VE) appearing in an input voltage decrease form. Timing errors (TE) and voltage errors (VE) appear as a result of intersymbol interference (ISI) that occurs during signal transmission between circuits.

  FIG. 2 is a block diagram of a conventional decision feedback equalizer input buffer 11. In FIG. 2, equalizer 10 amplifies the difference between an input signal (IN) containing an intersymbol interference (ISI) component and an oversampled odd (odd) output signal (OD) multiplied by an equalizing factor (α). Thus, the intersymbol interference (ISI) component is compensated. As a result, an amplified even (even) output signal (ed) is generated. That is, the amplified even output signal (ed) is ed = IN− (α × OD), and α × OD represents an intersymbol interference (ISI) component. Thus, the intersymbol interference (ISI) component is reduced with the amplified even output signal (ed).

  At the same time, the equalizer 10 multiplies an input signal (IN or INB (where “xB” indicates an inverted signal of the signal “x”)) including an intersymbol interference (ISI) component and an equalizing coefficient (α). Amplifying the difference between the resulting oversampled even output signal (EDB, or ED) to compensate for the intersymbol interference (ISI) component, and the resulting amplified odd (odd) An output signal (od) is generated, ie, the amplified odd signal (od) is od = IN− (α × ED), where α × ED represents the intersymbol interference (ISI) component. The intersymbol interference (ISI) component is reduced with the amplified odd output signal (od), and the equalizer 10 is amplified with circuitry that generates an amplified even output signal (ed or edB). A circuit for generating odd output signals (od or odB) and an equalizing circuit for generating even output signals (ed / edB) are described with reference to FIG. The equalizing circuit to be made is similar to the configuration of FIG.

  The oversampler 12 sequentially samples the even output signal (ed) amplified in response to each of the sampling clock signals (c0, c90) and sequentially generates an oversampled even output signal (ED, ED90). Let The oversampler 12 sequentially samples the odd output signal (od) amplified in response to each of the sampling clock signals (c90, c180) and oversamples the first and second odd output signals (OD90). , OD) are generated sequentially.

  The sampling clock signals (c0, c90) have a phase difference of 90 degrees. The phase detector 14 detects the phase difference between the oversampled even output signal (ED, ED90) and the oversampled odd output signal (OD, OD90), and in response to this, the up signal (up) ) And the down signal (dn) are activated. The up signal (up) and the down signal (dn) are transmitted to the counter 16 while being exchanged. The phase difference indicates the phase relationship between the data clock of the received data and the sampling clock used by the oversampler 12 to sample incoming data.

  The counter 16 increases the count output signal (cout) including a plurality of digital bits when the up signal (up) is activated, and decreases the count output signal (cout) when the down signal (dn) is activated. To do.

  The timing adjuster 18 adjusts the generation timing of the sampling clock signals (c0, c90, c180, c270) in response to the count output signal (cout). For example, when the count output signal (cout) increases at a higher value than the previous value such as 00... 01 to 00... 10, the generation timing of each of the sampling clock signals (c0, c90, c180, c270) is higher than before. Is adjusted to occur even later. However, if the count output signal (cout) decreases at a lower value, the generation timing of each of the sampling clock signals (c0, c90, c180, c270) is adjusted to occur earlier than before. In this way, the sampling clock signal is generated by the timing adjuster 18 in order to compensate for the centering error that exists between the input signal (IN) and the sampling clock signals (c0, c90, c180, c270) in the oversampler 12. The generation timing of (c0, c90, c180, c270) is adjusted.

  The clock generator 20 generates a number of reference clock signals (c1 to cn) in response to the input clock signal (CLK). Sampling clock signals (c0, c90, c180, c270) are generated from a number of reference clock signals (c1 to cn).

  FIG. 3 shows a schematic configuration of the equalizer 10 in the conventional decision feedback equalizing input buffer shown in FIG. The value of the input signal (IN) received by the equalizer 10 is amplified to compensate for voltage errors in the input signal (IN). Conventional equalizers have a fixed equalizing factor (α) having a predetermined value. In the equalizer circuit of FIG. 3, the load transistors (P1, P2) operate like load resistors and can be replaced with resistors. The differential transistors (N1, N2) receive input signals (IN, INB), respectively, and the differential transistors (N3, N4) receive output signals (OD, ODB), respectively. The current source transistors (N5, N6) flow currents (I1, I2) flowing through the first and second differential units, respectively. The value of the fixed equalizing coefficient (α) is determined as a function of the relative magnitude of the channel width of the fixed transistors (N5, N6). In the circuit of FIG. 3, the voltage (Vb) indicates a bias voltage having a constant value. Since the equalizing coefficient (α) has a fixed value, the equalizer 10 circuit operates under a certain condition regardless of the timing error (TE) or voltage error (VE) present in the input signal (IN). Therefore, conventional equalizer circuits cannot accurately compensate for timing errors or voltage errors present in input signals that fall outside the range of operating conditions.

  An object of the present invention is to provide a decision feedback equalizing input buffer capable of completely compensating for timing errors and voltage errors caused by intersymbol interference, and a memory using the same.

  The present invention can be accomplished by applying a variable equalizing factor that accommodates and compensates for timing error (TE) or voltage error (VE) ranges that can occur outside the range of operating conditions.

  One aspect of the invention is an equalizer that amplifies a voltage level difference between an input signal and an oversampled signal in response to a variable equalizing control signal to generate an amplified output signal, and is responsive to a sampling clock signal A sampling unit for generating the oversampled signal using the amplified output signal as a sample, and a timing for controlling the activation timing of the sampling clock signal in response to the phase of the oversampled signal A phase detector for generating a control signal and an equalizing controller for changing the variable equalizing control signal in response to the timing control signal are provided.

  The equalizer generates an amplified even output signal and an amplified odd output signal in response to the amplified output signal, and the sampling unit outputs the amplified even output signal to a first sampling clock and a second sampling signal. The first and second sampling clocks have a phase difference of 90 degrees with respect to the other and are oversampled in response to the first and second sampling clocks. The sampling unit generates an even signal and an oversampled second even signal, and the sampling unit samples the amplified odd output signal with a second sampling clock and a third sampling clock, and the second and third sampling signals. The clock has a phase difference of 90 degrees with respect to the counterpart and corresponds to the second and third sampling clocks. Characterized by generating a second odd signal first odd signal and the over-samples oversampled by. The phase detector determines whether or not there is a phase difference between the oversampled first even signal and the oversampled second even signal, and the oversampled first odd signal. And determining whether a phase difference exists between the over-sampled second odd signal and generating the timing control signal in response to the determination, wherein the phase detector comprises: The oversampled first in response to one of the first sampling clock, the second sampling clock, the third sampling clock, and a fourth sampling clock having a phase difference of 90 degrees from the third sampling clock. Whether there is a phase difference between the even signal and the oversampled second even signal and the oversampled Characterized in that to decide the propriety phase difference exists between the 1 odd signal and the oversampled second odd signal.

  The timing control signal includes a lock control signal, an up control signal, and a down control signal, and the lock control signal has no phase difference between the oversampled first and second even signals and is oversampled. The down control signal is activated when there is no phase difference between the first and second odd signals, and the down control signal is activated when there is no phase difference between the oversampled first and second even signals. The control signal is activated when there is no phase difference between the oversampled first and second odd signals.

  The equalizing controller adjusts a variable equalizing control signal in response to states of the up control signal, the down control signal, and the lock control signal, and the equalizing controller is configured to adjust the up control signal, the down control signal, and the down control signal. Receiving a control signal and the lock control signal, responding thereto, generating an auxiliary up control signal and an auxiliary down control signal, and when at least one of the up control signal and the down control signal is activated, An equalizing control signal generator that activates the auxiliary down control signal when the auxiliary up control signal is activated and the lock control signal is activated, and receives the auxiliary up control signal and the auxiliary down control signal In response, the variable equalizing control signal is generated and activated before being activated. In response to the auxiliary up control signal by increasing the variable equalizing control signal, in response to the auxiliary down control signal is activated, characterized in that it comprises a counter for reducing the variable equalizing control signal.

  The amplified output signal comprises an amplified even output signal and an amplified odd output signal, and the oversampled signal comprises an oversampled first even signal and an oversampled second even signal. The phase detector includes an oversampled first odd signal and an oversampled second odd signal between the oversampled first even signal and the oversampled second even signal. Responsive to this determination by determining whether a phase difference exists and determining whether a phase difference exists between the oversampled first odd signal and the oversampled second odd signal. Generating a timing control signal comprising a lock control signal, an up control signal, and a down control signal, wherein the oversampled first and The lock control signal is generated when there is no phase difference between two even signals and there is no phase difference between the oversampled first and second odd signals, and the oversampled first and second even signals The down control signal is generated when a phase difference exists between them, and the up control signal is generated when a phase difference exists between the oversampled first and second odd signals. The equalizing controller changes the variable equalizer control signal in response to the states of the up control signal, the down control signal, and the lock control signal, and the equalizing controller includes the up control signal, the A down control signal and the lock control signal are received, and in response, an auxiliary up control signal and an auxiliary down control signal are generated, and at least one of the up control signal and the down control signal is activated in the auxiliary up control signal The equalizing control signal generator is activated when the lock control signal is activated, and the auxiliary up control signal and the auxiliary down signal are activated when the lock control signal is activated. In response to receiving the control signal, the variable equalizing control signal is generated and activated. And a counter for increasing the value of the variable equalizing control signal in response to the auxiliary up control signal and decreasing the value of the variable equalizing control signal in response to the activated auxiliary down control signal. And

  The equalizing control signal includes a digital signal having a plurality of bits, the equalizer includes a transistor bank including a plurality of transistors, and the amplified output signal is responsive to an activation state of each transistor of the transistor bank. Each of the transistors is activated in response to a bit of the equalizing control signal to be variably amplified, and the equalizing control signal comprises a digital signal having a plurality of bits. The equalizer includes a first transistor having one of a source and a drain connected to a first voltage source and another one of the source and a drain connected to a first node, the first node and a second voltage source, Connected in series, and activated in response to the input signal and the first reference voltage, respectively, and in series between the first node and the second voltage source. A fourth transistor and a bank connected to each other, wherein the fourth transistor is activated in response to an inverted oversampled signal, and the transistor bank includes a plurality of fifth transistors connected in parallel with each other; The fifth transistors are connected to the first node in response to activation states of the fifth transistors in the transistor bank. The transistor bank is activated in response to a bit of the equalizing control signal so that the amplified output signal provided is variably amplified, and the transistor bank includes a plurality of sixth transistors. Each of the sixth transistors is connected in series to a corresponding fifth transistor, and each of the sixth transistors is activated in response to the first reference voltage.

  The decision feedback equalizing input buffer includes one of a source and a drain connected to the first voltage source, another one of the source and drain connected to a second node, a gate of the first transistor, and the second voltage. A seventh transistor having a gate connected to a source; an eighth transistor connected between the second node and a junction between the second transistor and the third transistor; and a second node and the second transistor. A ninth transistor connected between four transistors and a junction between the transistor banks is further provided. The amplified output signal comprises an amplified even output signal and an amplified odd output signal, and the amplified even output signal is provided from the first node to invert the amplified even output signal. The eighth transistor is activated in response to an inverted input signal and the ninth transistor is responsive to an inverted oversampled signal, wherein the signal is provided from the second node. The eighth transistor is activated in response to a second reference voltage.

  The amplified output signal is provided from the first node and the second node.

  The equalizing control signal comprises a digital signal having a plurality of bits, and the equalizer has one of a source and a drain connected to a first voltage source and another one of the source and a drain connected to a first node. The first and second transistors connected in series between the first node and the second voltage source and activated in response to the input signal and the first reference voltage, respectively, and A fourth transistor and a transistor bank connected in series between a first node and the second voltage source; and a voltage controller for generating a voltage control signal in response to the equalizing control signal. A transistor is activated in response to the oversampled signal, and the fifth transistor flows a variable current in response to the voltage control signal. And wherein the Unisuru. The input buffer is connected to one of the source and drain connected to the first voltage source, the other one of the source and drain connected to the second node, the gate of the first transistor, and the second voltage source. A sixth transistor having a gate, a seventh transistor connected between the second node and a junction between the second transistor and the third transistor, and a second node and the fourth transistor; The method further comprises an eighth transistor connected between the junction points with the fifth transistor.

  The sampling unit compares the amplified output signal with a reference voltage, generates a comparison signal, and samples the comparison signal in response to a first sampling clock signal to oversample the first signal. A second sampling register for generating an oversampled second signal by sampling the comparison signal in response to a second sampling clock signal having a phase different from that of the first sampling clock signal. The oversampled first and second output signals comprise the oversampled signal. The phase detector samples the oversampled first signal in response to a detector sampling clock signal and generates a first bit of a phase detector data signal, the detector sampling clock A second detection register that samples the oversampled second signal in response to the signal and generates a second bit of the phase detector data signal; and the first and second bits of the phase detector data signal A decoder for generating the timing control signal in response is provided.

  The amplified output signal comprises amplified even and odd output signals, and the sampling unit compares the amplified even output signal with a reference voltage to generate a first comparison signal; A first sampling register that samples the first comparison signal in response to a first sampling clock signal to generate an oversampled first even signal; a second sampling clock signal having a phase different from that of the first sampling clock signal A second sampling register that samples the first comparison signal in response to generating an oversampled second even signal, and compares the amplified odd output signal with a reference voltage to generate a second comparison signal. A second comparator, which samples the second comparison signal in response to the second sampling clock signal, A third sampling register for generating a first odd signal, and a second sampling signal oversampled in response to a third sampling clock signal having a phase different from that of the second sampling clock signal. A fourth sampling register for generating an odd signal is provided.

  The phase detector samples the oversampled first even signal in response to a detector sampling clock signal and generates a first bit of the phase detector data signal, the detector sampling A second detector register for sampling the oversampled second even signal in response to a clock signal and generating a second bit of the phase detector data signal; and in response to the detector sampling clock signal A third detection register for sampling a first odd signal oversampled to generate a third bit of the phase detector data signal; a second odd signal oversampled in response to the detector sampling clock signal; A fourth detection register that samples and generates a fourth bit of the phase detector data signal; and In response to the phase detector data signals, characterized in that it comprises a decoder for generating the timing control signal. The timing control signal includes a lock control signal, an up control signal, and a down control signal. When the values of the first and second bits are equal and the values of the third and fourth bits are equal, the lock control signal Is activated, and the down control signal is activated when the values of the first and second bits are not equal and the values of the third and fourth bits are equal, and the values of the first and second bits are A decision feedback equalizing input buffer, wherein the up control signal is activated when the third and fourth bit values are not equal.

  The input buffer may further include a sampling clock generator that generates the sampling clock signal, and the sampling clock generator may include one of a phase locked loop and a delay locked loop, and the sampling clock generator may include the sampling clock generator. A timing controller that generates a sampling clock signal, and a clock generator that receives the clock signal and generates a plurality of internal clock signals supplied to the timing controller are provided.

  The equalizer receives the variable equalizing control signal and generates an equalizing coefficient in response to the variable equalizing coefficient controller. The multiplier multiplies the oversampled output signal by the equalizing coefficient to generate a double signal. And a differential amplifier for generating the amplified output signal by subtracting the output of the multiplier from the input signal.

  The oversampled output signal comprises an oversampled even signal and an oversampled odd signal, and the equalizer receives the variable equalizing control signal and generates an equalizing coefficient in response thereto. A first multiplier that multiplies the oversampled odd signal by the equalizing coefficient to generate an odd multiple signal, and a multiplier that multiplies the oversampled even signal by the equalizing coefficient to generate an even multiple signal. A first multiplier that subtracts the odd multiple signal from the input signal to generate an even output signal; and an odd output that is amplified by subtracting the even signal from the input signal. A second differential amplifier for generating a signal is provided.

  According to another aspect of the present invention, as a memory device, the memory device receives a plurality of addressable memory cells each having a data storage element, and accesses at least one of the addressable memory cells. And a decision feedback equalizing input buffer, wherein the decision feedback equalizing input buffer is responsive to a variable equalizing control signal between the input signal and the oversampled signal. An equalizer for amplifying a voltage level difference to generate an amplified output signal; a sampling unit for sampling the amplified output signal in response to a sampling clock signal to generate the oversampled signal; and the oversample Signal phase A phase detector for generating a timing control signal for controlling the activation timing of the sampling clock signal in response; and an equalizing controller for changing the variable equalizing control signal in response to the timing control signal. Features.

  According to another aspect of the present invention, the memory system includes a memory controller that generates a command and an address signal, and a plurality of memory devices, and receives the command and the address signal, and in response to the command and the address signal, A memory module for storing data in the memory device and reading data from the memory device, each memory device receiving a plurality of addressable memory cells each having a data storage element; A decision feedback equalizing input buffer comprising: a decoder for generating a row signal and a column signal for accessing at least one of the addressable memory cells; and a decision feedback equalizing input buffer, wherein the decision feedback equalizing input buffer is responsive to a variable equalizing control signal. And oversampled signal An equalizer for amplifying the voltage level difference of the output signal to generate an amplified output signal; a sampling unit for sampling the amplified output signal in response to a sampling clock signal to generate the oversampled signal; and A phase detector for generating a timing control signal for controlling the activation timing of the sampling clock signal in response to the phase of the sampled signal; and changing the variable equalizing control signal in response to the timing control signal A decision feedback equalizing input buffer including an equalizing controller is provided.

According to another aspect of the present invention, the equalizer is a first load connected in series, a first transistor activated in response to a first input signal, and a first channel width responsive to a bias voltage. A first current path between the first voltage source and the second voltage source, the second load being connected in series, and A transistor bank having a third transistor activated in response to an input signal and a plurality of fourth transistors connected in parallel to each other, wherein each of the fourth transistors is responsive to a bit of the equalizing control signal An output that is activated to provide a variable second current in response to the variable equalizing control signal to provide a junction of the first load and the first transistor. The first voltage source and the second voltage source selectively change the effective second channel width of the transistor bank so that the signal is variably amplified in response to the variable second current And a second current path between the first and second input signals in response to a variable equalizing control signal.
The first and second loads include load transistors or load resistors.

  The first load and the first transistor are connected to a first node, the second load and the second transistor are connected to a second node, and between the second node, the first transistor, and the second transistor. Connected to the junction between the fifth transistor, which is activated in response to the inverted first input signal, the first node, the third transistor, and the transistor bank. The semiconductor device further includes a sixth transistor that is activated in response to the input signal.

  The transistor bank further includes a plurality of seventh transistors, and each of the seventh transistors is connected in series with a corresponding fourth transistor and is activated in response to the bias voltage. .

  Another aspect of the present invention is a method of equalizing an input signal received at an input buffer, the method amplifying a voltage difference between the input signal and the oversampled signal in response to a variable equalizing control signal. Generating an amplified output signal, sampling the amplified output signal in response to a sampling clock signal to generate the oversampled signal, and responding to a phase of the oversampled signal Generating a timing control signal for adjusting the activation timing of the sampling clock signal, and changing the variable equalizing control signal in response to the timing control signal.

  The amplified output signal comprises an amplified even output signal and an amplified odd output signal, and the oversampled signal comprises an oversampled first even signal and an oversampled second even signal, The phase detector comprises an oversampled first odd signal and an oversampled second odd signal, and the phase detector is positioned between the oversampled first even signal and the oversampled second even signal. Determine if a phase difference exists and determine if there is a phase difference between the oversampled first odd signal and the second oversampled second odd signal and lock in response to this determination A timing control signal comprising a control signal, an up control signal, and a down control signal is generated and the oversampled first and second even signals are generated. The lock control signal is generated when there is no phase difference with the signal and no phase difference with the oversampled first and second odd signals, and the oversampled first and second even numbers are generated. The down control signal is generated if there is a phase difference with the signal, and the up control signal is generated if there is a phase difference between the oversampled first and second odd signals. It is characterized by that.

  The step of changing the variable equalizing control signal is characterized by changing the variable equalizing control signal in response to states of the up control signal, the down control signal, and the lock control signal, and the variable equalizing control. The step of changing the signal receives the up control signal, the down control signal, and the lock control signal, and generates an auxiliary up control signal and an auxiliary down control signal in response thereto, and the auxiliary up control signal is The auxiliary down control signal is activated when at least one of the up control signal and the down control signal is activated, and the auxiliary down control signal is activated when the lock control signal is activated; and the auxiliary up control signal And receiving the auxiliary down control signal and generating the variable equalizing control signal in response to the auxiliary down control signal. A value of the variable equalizing control signal is increased in response to the activated auxiliary up control signal, and a value of the variable equalizing control signal is decreased in response to the activated auxiliary down control signal. It is characterized by providing.

  FIG. 4 is a block diagram illustrating a decision feedback equalizing input buffer according to the present invention. In the embodiment of FIG. 4, the equalizer 10 'is multiplied by an input signal (IN) containing an intersymbol interference (ISI) component and a variable equalization coefficient (β) determined in response to the received equalization coefficient control signal (eqco). The difference between the oversampled odd output signals (OD or ODB) is amplified to compensate for the intersymbol interference (ISI) component. As a result, amplified first even (even) output signals (ed, edB) are generated. At the same time, the equalizer 10 ′ amplifies the difference between the input signal (IN) containing the intersymbol interference (ISI) component and the oversampled even output signal (ED or EDB) multiplied by the variable equalizing factor (β). Compensate for intersymbol interference (ISI) components. As a result, an amplified first odd output signal (od, odB) is generated. The equalizer 10 'includes a circuit that generates an amplified even output signal (ed, edB) and a circuit that generates an amplified odd output signal (od, odB).

  The oversampler 12 sequentially samples the first even output signal (ed) amplified in response to each of the sampling clock signals (c0, c90), and oversamples the even output signal (ED, ED90). It occurs sequentially. The oversampler 12 sequentially samples the odd output signals (od, odB) amplified in response to the sampling clock signals (c90, c180) and sequentially oversamples the first and second odd output signals. (OD90, OD) are generated sequentially. The sampling clock signals (c0, c90, c180) each have a phase difference of 90 degrees. Oversampled even and odd output signals (ED, OD) are output as intersymbol interference (ISI) compensation signals. The equalizer 10 'and the oversampler 12 can be selectively configured as a single, common circuit block, or independent circuit block.

  The phase detector 14 'detects the phase difference between the oversampled even output signals (ED, ED90), detects the phase difference between the oversampled odd output signals (OD, OD90), and In response, an up control signal (up) or a down control signal (dn) is generated. The phase detector 14 ′ generates a lock control signal (lock) when there is no phase difference between the oversampled even output signal (ED, ED90) or the oversampled odd output signal (OD, OD90). .

  The equalizing adjuster 22 receives the up control signal (up), the down control signal (dn), and the lock control signal (lock) generated from the phase detector 14 ′, and in response thereto, the equalizing coefficient adjustment signal (eqco). ). In one embodiment, the equalizing coefficient adjustment signal (eqco) is a digital value composed of a plurality of digital bits. When the up signal (up) and the down signal (dn) are activated, the equalizing adjuster 22 increases the value of the equalizing coefficient adjustment signal (eqco). Activation of the up signal (up) and the down signal (dn) means that a timing error and / or a voltage error exists in the input signal (IN). However, if the lock control signal (lock) is enabled, the equalizing adjuster 22 decreases the value of the equalizing coefficient adjusting signal (eqco). Activation of the lock control signal (lock) means that there is substantially no timing error or voltage error in the input signal (IN). By such a method, the value of the equalizing coefficient adjustment signal (eqco) is variably controlled, and control signals (up, dn, lock) indicating whether or not there is a timing error or a voltage error in the input signal. Received and adjusted in response. The timing error and the voltage error included in the input signal (IN) as the value of the equalizing coefficient adjustment signal (eqco) can be compensated accurately and efficiently. Therefore, the value of the equalizing coefficient (β) is adjusted depending on whether or not there is a timing error and / or a voltage error in the input signal (IN).

  The counter 16 receives the up control signal (up) and the down control signal (dn) from the phase detector 14 ′, generates a current output signal (cout), and supplies it to the timing adjuster 18. The timing adjuster 18 receives the reference clock signals (c1, c2,..., Cn) from the clock generator 20, which may include a phase locked loop or a delay locked loop, and samples clock signals (c0, c90, c180, c270). Is generated. The sampling clock signals (c0, c90, c180, c270) each have a phase difference of 90 degrees and are activation timings controlled by the timing adjuster 18 that operates in response to the count output signal (cout). The operations of the counter 16, the timing adjuster 18 and the clock generator 20 in the system of the present invention are the same as those of the embodiment according to the prior art shown in FIG.

  FIG. 5 is a block diagram of the equalizing adjuster 22 shown in FIG. 4 according to the present invention. In the embodiment of FIG. 5, the equalizing adjuster 22 includes an equalizing adjusting signal generator 30 and a counter 32. The equalizing regulator 22 receives the up control signal (up), the down control signal (dn) and the lock control signal (lock) generated by the phase detector 14 '. When the up control signal (up) or the down control signal (dn) is activated, the equalizing adjustment signal generator 30 activates the auxiliary up control signal (up), and when the lock control signal (lock) is activated. The auxiliary down control signal (ddn) is activated.

  The counter 32 generates an increased equalizing coefficient control signal (eqco) in response to the activated auxiliary up control signal (up), and is decreased in response to the activated auxiliary down control signal (ddn). An equalizing coefficient control signal (eqco) is generated. By such a method, the value of the equalizing coefficient adjustment signal (eqco) is varied.

  FIG. 6 is a block diagram of the equalizer 10 'shown in FIG. 4 according to the present invention. The equalizer 10 ′ includes an equalizing coefficient adjuster 40, first and second multipliers 42 and 46, and first and second differential amplifiers 44 and 48. The equalizing coefficient adjuster 40 receives a binary equalizing coefficient adjusting signal (eqco) having a size of n bits, and generates an equalizing coefficient (β) in response thereto. Here, since the equalizing coefficient (β) is generated in response to the variable equalizing coefficient control signal (eqco), it has a variable value. For this reason, compared to the prior art, the embodiments of the present invention can accurately compensate for timing errors and voltage errors present in a received input signal that falls outside the range of operating conditions.

  The first multiplier 42 of the equalizer 10 'multiplies the variable equalizing coefficient (β) and the oversampled odd output signal (OD) to output an odd output signal (βOD). In the same manner, the second multiplier 46 multiplies the variable equalizing coefficient (β) and the oversampled even output signal (ED) to output an even output signal (βED). The first differential amplifier 44 amplifies the difference between the odd output signal (βOD) and the input signal (IN) to generate an amplified first even output signal (ed), and the second differential amplifier 48 generates the even output signal. The difference between (βED) and the input signal (IN) is amplified to generate an amplified first odd output signal (od).

  7A and 7B are schematic circuit diagrams showing even and odd components of the equalizer 10 'shown in FIGS. 4 and 6 according to the present invention. In FIG. 7A, the equalizer 10 ′ includes first and second PMOS transistors (P1, P2) and first to fifth NMOS transistors (N1, N2, N3, N4, and N5), and transistors N6-1 to N6- a first transistor bank (TB1) configured by n) and a second transistor bank (TB2) configured by transistors (N7-1 to N7-n). The inverted input signal (INB) and the oversampled inverted odd output signal (ODB) are input to the transistors (N2, N3). The first and second PMOS transistors (P1, P2) operate with respective load resistors, and predetermined currents (I1, I2) flow through the first and second PMOS transistors (P1, P2), respectively. The voltage level of the amplified first even output signal (ed) includes a first PMOS transistor (P1), a first NMOS transistor (N1) responding to the input signal (IN), and a fifth NMOS transistor (Nb) responding to the bias voltage (Vb). Current (I1) flowing along N5) and the second PMOS transistor (P2), a fourth NMOS transistor (N4) responsive to the oversampled odd output signal (OD), and a transistor (N6) in the first transistor bank (TB1) -1 to N6-n) and the current (I2) flowing along the selectively activated transistors (N7-1 to N7-n) of the second transistor bank (TB2). The transistors (N7-1 to N7-n) of the second transistor bank (TB2) are selectively activated in response to the bit state of the variable equalizing coefficient control signal (eqco). Each pair of transistors corresponding to the first transistor bank (TB1) and the second transistor bank (TB2) is a variable equalizing coefficient (eg, transistors N6-1 and N7-1, transistors N6-2 and N7-2, etc.). The current flows in accordance with the bit state (activated or deactivated) of the control signal (eqco). In this process, the amplified first even output signal (ed) is generated in response to the amplified values of the first current (I1) and the second current (I2). The voltage level of the amplified inverted even output signal (edB) is also determined by a similar method.

  The transistors (N6-1 to N6-n) of the first transistor bank (TB1) are responsive to the bias voltage (Vb), and the transistors (N7-1 to N7-n) of the second transistor bank (TB2) are variable equalizing coefficients. Responds to the control signal (eqco). The gates of the transistors (N7-1 to N7-n) of the second transistor bank (TB2) are connected to bits corresponding to the bits of the variable equalizing coefficient control signal (eqco). The transistors (N7-1 to N7-n) of the second transistor bank (TB2) are formed to have different channel widths, and the transistors (N6-1 to N6-) of the first transistor bank (TB1) are formed. n) is formed to have different channel widths so as to correspond to the channel widths of the respective transistors of the second transistor bank (TB2), so that the series of paired transistors (N6-1, N7-1) are respectively Make different currents flow. For example, the channel width of each transistor (N7-1 to N7-n) of the second transistor bank (TB2) is formed so as to have a current driving capability that is a multiple of 2 of the adjacent transistors, and the second current (I2) and A corresponding equalization coefficient (β) of the equalizer 10 ′ is variably adjusted to have a value directly related to the binary value of the variable equalization coefficient control signal (eqco). In this way, variable control of the equalizing coefficient (β) of the system becomes possible. In other embodiments, the transistors (N6-1 to N6-n) in the first transistor bank (TB1) may be equal to the transistors (N7-1 to N7-n) in the second transistor bank (TB2). . In such a case, the current drive capability of each transistor is equal. However, when the additional transistor is activated, the overall current drive capability is varied to obtain a variable system equalizing factor (β).

  In another embodiment, instead of the inverted input signal (INB) and the oversampled inverted odd output signal (ODB) being supplied to the respective gates of the transistors (N2, N3), the reference voltage (Vref) is supplied. You can also

  The equalizer 10 'shown in FIG. 7A is a circuit configured to generate an amplified first even output signal (ed, edB). As shown in FIG. 7B, an odd equalizer circuit 10 ″ configured similar to the circuit of FIG. 7A may be used to generate an amplified first odd output signal (od, oddB). A second transistor bank (TB1, TB2) is provided for the odd equalizer circuit 10 ". Therefore, odd output signals (od, odB) amplified in response to the variable equalization coefficient control signal (eqco) are generated.

  FIG. 8 is a circuit diagram showing another embodiment of the equalizer shown in FIG. 4 according to the present invention. In the embodiment of FIG. 8, a single transistor (N8) is connected in series between a node connecting the transistors (N3, N4) and a reference ground voltage. A voltage control signal (VCO) is connected to the gate of the transistor (N8). The voltage control signal (VCO) is variable, and the voltage of the voltage control signal (VCO) is controlled by the voltage regulator 60 in response to the variable equalizing coefficient control signal (eqco). For example, when the variable equalizing coefficient control signal (eqco) increases, the voltage regulator 60 increases the voltage level of the voltage control signal (VCO) in response thereto, and when the variable equalizing coefficient control signal (eqco) decreases, the voltage regulator. In response, 60 reduces the voltage level of the voltage control signal (VCO). The current flowing through the transistor (N8) is variably controlled based on a variable voltage control signal (VCO). Therefore, as described above, since it is a direct function of the current flowing through the transistor (N8), variable control is possible by the equalizing coefficient (β) of the equalizer 10 ″ ″.

  FIG. 9 is a block diagram of the embodiment of the oversampler 12 shown in FIG. 4 according to the present invention. The oversampler 12 includes first and second comparators 70 and 72 and first to fourth D flip-flops (DFF1, DFF2, DFF3, and DFF4). The first comparator 70 receives the amplified even output signal (ed) and the reference voltage (Vref). If the amplified even output signal (ed) is larger than the reference voltage (Vref), the first and first comparators 70, The 2D flip-flops (DFF1, DFF2) output an even comparison signal (Ded) having a “high” level. The second comparator 72 receives the amplified odd output signal (od) and the reference voltage (Vref). If the amplified odd output signal (od) is larger than the reference voltage (Vref), the second and second comparators 72 and An odd comparison signal (Dod) having a “high” level is output from the 4D flip-flops (DFF3 and DFF4).

  The first D flip-flop (DFF1) latches the even comparison signal (Ded) in response to the first sampling clock signal (c0) and outputs an oversampled first even output signal (ED). The second D flip-flop (DFF2) latches the even comparison signal (Ded) in response to the second sampling clock signal (c90) and outputs an oversampled second even output signal (ED90). Here, the oversampled first and second even output signals (ED, ED90) are compared evenly in response to the first and second sampling clocks (c0, c90) in which the oversampler 12 has a phase difference of 90 degrees. Sequentially generated by sampling the signal (Ded) twice.

  In a manner similar to that described above, the third D flip-flop (DFF3) latches the odd comparison signal (Dod) in response to the second sampling clock signal (c90) and oversamples the first odd output signal (OD90). ) Is output. The fourth D flip-flop (DFF4) latches the odd comparison signal (Dod) in response to the third sampling clock signal (c180), and outputs an oversampled second odd output signal (OD). Here, the oversampled first and second odd output signals (OD90, OD) are odd in response to the second and third sampling clocks (c90, c180) in which the oversampler 12 has a phase difference of 90 degrees. Sequentially generated by sampling the comparison signal (Dod) twice.

  FIG. 10 is a schematic block diagram of the phase detector 14 'shown in FIG. 4 according to the present invention. In the embodiment of FIG. 10, the phase detector 14 ′ includes fifth, sixth, seventh, and eighth D flip-flops (DFF 5, DFF 6, DFF 7, and DFF 8) and a decoder 80. The fifth D flip-flop (DFF5) outputs a first even output signal (ED) oversampled in response to the third sampling clock signal (c270). The sixth D flip-flop (DFF6) outputs a second even output signal (ED90) oversampled in response to the third sampling clock signal (c270). The seventh D flip-flop (DFF7) outputs an oversampled first odd output signal (OD90) in response to the third sampling clock signal (c270). The eighth D flip-flop (DFF8) outputs a second odd output signal (OD) oversampled in response to the third sampling clock signal (c270). In the embodiment of phase detector 14 'of FIG. 10, the third sampling clock signal (c270) was used to sample the oversampled even and odd output signals (ED, ED90, OD, OD90), but the other Sampling clock signals (c0, c90, c180) can also be used. A clock signal received at an external terminal can also be used.

  Output data signals (data) of the fifth, sixth, seventh, and eighth D flip-flops (DFF5, DFF6, DFF7, and DFF8) are supplied to the decoder 80, and the decoder 80 performs up-control in response thereto. Three control signals are generated: a signal (up), a down control signal (dn), and a lock control signal (lock). In one embodiment, the decoder 80 activates the up control signal (up) if the phase of the sampling clock (c0, c90, c180) is earlier than the phase of the input data signal (IN). If the phase of the sampling clock (c0, c90, c180) is later than the phase of the input data signal (IN), the decoder 80 activates the down control signal (dp). When the phase of the sampling clock (c0, c90, c180) and the phase of the input data signal (IN) coincide, the decoder 80 activates the lock control signal (lock).

  The operation of the decoder 80 shown in FIG. 10 refers to the timing diagrams of FIGS. 11A, 11B, and 11C showing the generation conditions of the up control signal (up), the down control signal (dn), and the lock control signal (lock). And describe.

  For example, if the input data signal (IN) is continuously input at “0110”, the effective value of the amplified first even output signal (ed) output by the equalizer 10 ′, 10 ″ or 10 ″ ′ is It is “0”, and the effective value of the amplified second even output signal (ed) is “1”. On the other hand, assuming that the input data is as above, the effective value of the amplified first odd output signal (od) output by the equalizer 10 ′, 10 ″, or 10 ″ ′ is “1”. The effective value of the amplified second odd output signal (od) is “0”. That is, the order of even-numbered input data (ed) is “01”, and the order of odd-numbered input data (od) is “10”. In FIG. 11A, the data signal (data) has a value of “0011” at the first rising edge of the third sampling clock signal (c270). The data signal (data) is supplied to the decoder 80, and the oversampled first even output signal (ED) and the oversampled second even output signal (ED90) have the same value (eg, “0”). Have. Since each of the oversampled first and second even output signals (ED, ED90) is a value sampled from the same even data (first even data (ed) having a value of “0”), it is oversampled. The even output signals (ED, ED90) have the same value. Further, the decoder 80 determines that the oversampled second odd output signal (OD) and the oversampled first odd output signal (OD90) have the same value (“1”). Since each of the oversampled first and second odd output signals (OD90, OD) is a value sampled with the same odd data (first odd data (od) having a value of “1”), it is oversampled. The odd output signals (OD, OD90) have the same value. Since the oversampled even output signals (ED, ED90) have the same value (“0”) and the oversampled odd output signals (OD, OD90) have the same value (“1”), the decoder 80 enables a lock control signal (lock).

  Further, the data signal (data) has a value of “1100” at the second rising edge of the third sampling clock (c270). The data signal (data) is supplied to the decoder 80, and the decoder 80 has the same value ("1") between the oversampled first even output signal (ED) and the oversampled second even output signal (ED90). Decide to have. Each of the oversampled first and second even output signals (ED, ED90) is oversampled because it is sampled with equal even data, ie, second even data (ed) having a value of “1”. The even output signals (ED, ED90) have the same value. Further, the decoder 80 determines that the oversampled second odd output signal (OD) and the oversampled first odd output signal (OD90) have the same value (“0”). Since each of the oversampled first and second odd output signals (OD90, OD) is a value sampled by the same odd data, ie, second odd data (od) having a value of “0”, The sampled odd output signals (OD, OD90) have the same value. Since the oversampled even output signals (ED, ED90) have the same value ("1") and the oversampled odd output signals (OD, OD90) have the same value ("0") The decoder 80 maintains the activated state of the lock control signal (lock). That is, the rising edge of the sampling clock signal (c0) is located at an appropriate position related to the even-numbered input data (ed), for example, the center of the even-numbered input data (ed), and the rising edge of the sampling clock signal (c180) is the odd-numbered input data. Valid data for confirming that it is located at an appropriate position related to (od), for example, the center of odd-numbered input data (od) is output.

  Unlike the input data of FIG. 11A, assuming that data “1001” is continuously input to the input data signal (IN), the amplified data output by the equalizer 10 ′, 10 ″ or 10 ″ ′ The effective value of the first even output signal (ed) is “1”, while the effective value of the amplified second even output signal (ed) is “0”. On the other hand, if the input data remains the same as above, the effective value of the amplified first odd output signal (od) output by the equalizer 10 ′, 10 ″, or 10 ″ ′ is “0” and is amplified. The effective value of the second odd output signal (od) is “1”. That is, the order of even-numbered input data (ed) is “10”, and the order of odd-numbered input data (od) is “01”. Therefore, in connection with FIG. 11B, the substantial value of the data signal (data) must be a value of “1100” at the first rising edge of the third sampling clock signal (c270), but the data signal (data) ) Has a value of “1000”. The data signal (data) is supplied to the decoder 80, and the decoder 80 has an oversampled first even output signal (ED) and an oversampled second even output signal (ED90) having different data values ("1"). So that the values of the oversampled first odd output signal (OD90) and the oversampled second odd output signal (OD) have the same value (“0”). Decide on. In response to this determination, the decoder 80 activates the down control signal (dn) to make the rising edge of the first sampling clock signal (c0) closer to the center of the even data signal (ed). As described above, when the down control signal (dn) is activated, the timing adjuster 18 activates the sampling clock signals (c0, c90, c180) earlier. In addition, at the second rising edge of the third sampling clock signal (c 270), the data signal (data) should be “0111” even though the substantial value of the data signal (data) should have the value “0011”. ”. The data signal (data) is supplied to the decoder 80, and the decoder 80 determines that the oversampled first even output signal (ED) and the oversampled second even output signal (ED90) have different values ("0" and "0"). 1 ”). Further, the decoder 80 determines that the oversampled first odd output signal (OD90) and the oversampled second odd output signal (OD) have the same value ("1"). In response to this determination, the decoder 80 keeps the activated state of the down control signal (dn) so that the rising edge of the first sampling clock signal (c0) is closer to the center of the even data signal (ed).

  In FIG. 11B, when data “1001” is continuously input to the input data signal (IN), the amplified first even output signal (ed) output by the equalizer 10 ′, 10 ″, or 10 ″ ′. The effective value is “1”, and the value of the amplified second even output signal (ed) is “0”. On the other hand, if the input data is much the same, the effective value of the amplified first odd output signal (od) output by the equalizer 10 ′, 10 ″ or 10 ″ ′ is “0”, and the amplified first data 2 The effective value of the odd output signal (od) is “1”. That is, the order of even-numbered input data (ed) is “10”, and the order of odd-numbered input data is “01”. Therefore, in connection with FIG. 11C, the value of the data signal (data) must become “1100” at the first rising edge of the third sampling clock signal (c270). It has a value of “1110”. The data signal (data) is supplied to the decoder 80 so that the oversampled first even output signal (ED) and the oversampled second even output signal (ED90) have the same data value (“1”). Thus, the oversampled first odd output signal (OD90) and the oversampled first odd output signal (OD) are determined to have different data values ("1" and "0"), respectively. In response to this determination, the decoder 80 activates the up control signal (up) so that the rising edge of the sampling clock signal (c180) is closer to the center of the odd data signal (od). As described above, when the up control signal (up) is activated, the timing controller 18 activates the sampling clock signals (c0, c90, c180) with further delay. Also, at the second rising edge of the third sampling clock (c 270), the data signal (data) has a value of “0001” even though the data value has to become “0011”. The data signal (data) is supplied to the decoder 80 so that the oversampled first even output signal (ED) and the oversampled second even output signal (ED90) have the same data value (“0”). The over-sampled first odd output signal (OD90) and the over-sampled second odd output signal (OD) are determined to have different data values ("0" and "1"), respectively. In response to this determination, the decoder 80 keeps the activation of the up control signal (up) so that the rising edge of the sampling clock signal (c180) is closer to the center of the odd data signal (od). As described above, when the up control signal (up) is activated, the timing controller 18 activates the sampling clock signals (c0, c90, c180) with further delay.

  FIG. 12 is a block diagram showing still another embodiment of a decision feedback equalizing input buffer according to the present invention. In the embodiment of FIG. 12, the equalizer 10 'is different from that of the other embodiment of the present invention in that the equalizer 10' generates the amplified even and odd output signals (ed, od). In response, an amplified single serial output signal (in) is generated. In this case, only a single equalizer circuit 10 'is required as shown in FIG. Further, the output signal (ain1), which has been over-sampled by the equalizing coefficient control signal (eqco) generated by the equalizing adjuster 22, is fed back to the equalizer 10 '. The amplified single serial output signal (in) can correspond to an even component of the signal.

  The timing adjuster 18 ′ outputs a plurality of sampling output signals (ck1, ck2, ck3, ck4) sequentially generated in response to the reference clock signals (c1, c2,..., Cn) generated by the clock generator 20. appear. As in the above-described embodiment, the generation timing of the sampling clock signal is controlled by the timing controller 18 ′ in response to the count output signal (cout) of the counter 16. In the embodiment of FIG. 12, sampling clock signals (ck1, ck2, ck3, ck4) correspond to clock signals (c0, c90, c180, c270) each having a phase difference of 90 degrees in the above-described embodiment. Further, all the sampling clock signals (ck1, ck2, ck3, ck4) including the fourth sampling clock signal (ck4) are supplied to the oversampler 12 ′, and the oversampler 12 ′ responds to this by oversampling. The generated first to fourth output signals (ain1, ain2, ain3, ain4) are generated. The oversampled first to fourth output signals (ain1, ain2, ain3, ain4) are supplied to a phase detector 14 'having a function similar to that of the above-described embodiment of FIG. That is, as described above, the lock control signal (lock) is supplied to the equalizing coefficient adjuster 22, and the up control signal (up) and the down control signal (dn) are supplied to the equalizing coefficient adjuster 22 and the counter 16.

  In the embodiment of FIG. 4 described above, a double data rate approach method is used in which data is interleaved using even and odd branches, but the input data rate compared to the processing capability of the input buffer circuit. Since time is lower, a time interleaving approach is not required. The embodiment of FIG. 12 is implemented under such an assumption. Therefore, the single input branch as in the embodiment of FIG. 12 has the merit of simplifying the hardware configuration and reducing the consumed circuit configuration and manufacturing cost.

  In the manner described above, the decision feedback equalizing input buffer provides sufficient compensation for timing and voltage errors. That is, by using the variable equalizing coefficient (β) by the equalizer, the timing error and the voltage error that are out of the range of the operating condition are compensated. This can further increase the signal reliability and the transmission rate between the internal circuits.

  The present invention can be applied to all kinds of integrated circuits including memory devices and memory systems. In an embodiment of a memory device, the memory device includes a plurality of addressable memory cells, each cell including a data storage element. The decoder receives an address from an external source and generates a row signal and a column signal to approach any one of the memory cells. A decision feedback input buffer can be used in the memory device to receive a signal transmitted from a source external to the chip.

  FIG. 13 is a block diagram of a memory system according to the present invention. The memory system includes a memory controller 100 and a memory module 300 that generate an instruction signal (COM) and an address signal (BA (bank address) and ADD). The memory module 300 includes a plurality of memory devices (300-1, 300-2,..., 300-n), receives a command signal (COM) and an address signal (BA, ADD), and responds to the memory by the memory Write data (Din) to the devices (300-1, 300-2,..., 300-n) and read data (Dout) from the memory devices (300-1, 300-2,..., 300-n). . The decision feedback equalizing input buffer according to the present invention can be used in a memory device to receive data transmitted from a source external to the chip.

  Although the foregoing has been described with reference to preferred embodiments of the invention, those skilled in the art will recognize that the invention may be practiced without departing from the spirit and scope of the invention as set forth in the appended claims. Various modifications and changes can be made to the invention.

It is a wave form diagram which shows the influence of the timing error and voltage error which generate | occur | produce by interference between symbols. It is a block diagram which shows the conventional decision feedback equalizing input buffer. FIG. 3 is a diagram showing a detailed configuration of an equalizer in the conventional decision feedback equalizing input buffer shown in FIG. 2. FIG. 6 is a block diagram illustrating a decision feedback equalizing input buffer according to the present invention. FIG. 5 is a block diagram of the equalizing regulator shown in FIG. 4 according to the present invention. FIG. 5 is a block diagram of the equalizer shown in FIG. 4 according to the present invention. FIG. 5 is a circuit diagram illustrating in detail the even and odd components of the equalizer shown in FIG. 4 in accordance with the present invention. FIG. 5 is a circuit diagram illustrating in detail the even and odd components of the equalizer shown in FIG. 4 in accordance with the present invention. FIG. 5 is a circuit diagram showing another embodiment of the equalizer shown in FIG. 4 according to the present invention. It is a block diagram which shows the structure of the oversampler shown in FIG. 4 by this invention. It is a block diagram which shows the structure of the phase detector shown in FIG. 4 by this invention. FIG. 6 is a timing diagram illustrating conditions under which a lock control signal, a down signal, and an up signal are generated according to the present invention. FIG. 6 is a timing diagram illustrating conditions under which a lock control signal, a down signal, and an up signal are generated according to the present invention. FIG. 6 is a timing diagram illustrating conditions under which a lock control signal, a down signal, and an up signal are generated according to the present invention. FIG. 7 is a block diagram illustrating still another embodiment of a decision feedback equalizing input buffer according to the present invention. 1 is a block diagram of a memory system according to the present invention.

Explanation of symbols

10, 10 ', 10 "': Equalizer 12, 12 ': Oversampler 14, 14': Phase detector 16: Counter 18, 18 ': Timing adjuster 20: Clock generator 22: Equalizing adjuster 30: Equalizing Adjustment signal generator 32: Counter 40: Equalizing coefficient adjuster 42, 46: First and second multipliers 44, 48: First and second differential amplifiers 60: Voltage regulators 70, 72: First and second Comparator 80: Decoder 100: Memory controller 300: Memory module

Claims (53)

An equalizer that amplifies the voltage level difference between the input signal and the oversampled signal in response to the variable equalizing control signal to generate an amplified output signal;
A sampling unit that samples the amplified output signal in response to a sampling clock signal to generate the oversampled signal;
A phase detector that generates a timing control signal for controlling the timing of activation of the sampling clock signal in response to the phase of the oversampled signal;
An equalizing controller for changing the variable equalizing control signal in response to the timing control signal;
A decision feedback equalizing input buffer comprising: The equalizer is
The decision feedback equalizing input buffer of claim 1, wherein the even output signal and the amplified odd output signal are generated in response to the amplified output signal. The sampling unit is
The amplified even output signal is sampled with a first sampling clock and a second sampling clock, and the first and second sampling clocks have a phase difference of 90 degrees with respect to each other, Generating an oversampled first even signal and an oversampled second even signal in response to the second sampling clock;
The sampling unit samples the amplified odd output signal with a second sampling clock and a third sampling clock, and the second and third sampling clocks have a phase difference of 90 degrees with respect to each other, and 3. The decision feedback equalizing input buffer of claim 2, wherein the decision feedback equalizing input buffer is configured to generate an oversampled first odd signal and an oversampled second odd signal in response to the second and third sampling clocks.   The phase detector determines whether or not a phase difference exists between the oversampled first even signal and the oversampled second even signal, and the oversampled first odd signal and 4. The decision feedback according to claim 3, wherein whether or not there is a phase difference with the oversampled second odd signal is determined and the timing control signal is generated in response to the determination. Equalizing input buffer.   The phase detector is responsive to one of the first sampling clock, the second sampling clock, the third sampling clock, and a fourth sampling clock having a phase difference of 90 degrees from the third sampling clock. Whether a phase difference exists between the oversampled first even signal and the oversampled second even signal, and the oversampled first odd signal and the oversampled second odd signal The decision feedback equalizing input buffer according to claim 4, wherein whether or not a phase difference exists is determined.   The timing control signal includes a lock control signal, an up control signal, and a down control signal. The lock control signal is oversampled without a phase difference between the oversampled first and second even signals. The down control signal is activated when there is no phase difference between the first and second odd signals, and the down control signal is activated when there is no phase difference between the oversampled first and second even signals. 5. The decision feedback equalizing input buffer of claim 4, wherein a control signal is activated when there is no phase difference between the oversampled first and second odd signals. The equalizing controller is
7. The decision feedback equalizing input buffer according to claim 6, wherein a variable equalizing control signal is adjusted in response to states of the up control signal, the down control signal, and the lock control signal. The equalizing controller is
Receiving the up control signal, the down control signal and the lock control signal, and generating an auxiliary up control signal and an auxiliary down control signal in response thereto;
Equalizing in which the auxiliary up control signal is activated when at least one of the up control signal and the down control signal is activated, and the auxiliary down control signal is activated when the lock control signal is activated. A control signal generator;
Receiving the auxiliary up control signal and the auxiliary down control signal, generating the variable equalizing control signal in response thereto, and increasing the variable equalizing control signal in response to the activated auxiliary up control signal; A counter that decrements the variable equalizing control signal in response to the activated auxiliary down control signal;
The decision feedback equalizing input buffer of claim 6, comprising: The decision feedback equalizing input buffer is:
The amplified output signal comprises an amplified even output signal and an amplified odd output signal, and the oversampled signal is an oversampled first even signal and an oversampled second even signal, over Comprising a sampled first odd signal and an oversampled second odd signal;
The phase detector determines if there is a phase difference between the oversampled first even signal and the oversampled second even signal, and the oversampled first odd signal and the oversampled second even signal. Determining whether there is a phase difference with the oversampled second odd signal and generating a timing control signal comprising a lock control signal, an up control signal, and a down control signal in response to the determination; The lock control signal is generated when there is no phase difference between the oversampled first and second even signals and there is no phase difference between the oversampled first and second odd signals, and the oversampled If there is a phase difference between the first and second even signals, the down control signal is generated, and the phase is between the oversampled first and second odd signals. Decision feedback equalizing the input buffer of claim 1, wherein the generating the up control signal and the difference is present. The equalizing controller is
The decision feedback equalizing input buffer according to claim 9, wherein the variable equalizer control signal is changed in response to states of the up control signal, the down control signal, and the lock control signal. The equalizing controller is
Receiving the up control signal, the down control signal, and the lock control signal, and generating an auxiliary up control signal and an auxiliary down control signal in response to the up control signal, the down control signal, and the down control signal; An equalizing control signal generator activated when at least one of the control signals is activated, and the auxiliary down control signal is activated when the lock control signal is activated;
The auxiliary up control signal and the auxiliary down control signal are received, the variable equalizing control signal is generated in response thereto, and the value of the variable equalizing control signal in response to the activated auxiliary up control signal A counter that increases and decreases in value of the variable equalizing control signal in response to the activated auxiliary down control signal;
10. The decision feedback equalizing input buffer of claim 9 comprising:   The equalizing control signal includes a digital signal having a plurality of bits, the equalizer includes a transistor bank including a plurality of transistors, and the amplified output signal is responsive to an activation state of each transistor of the transistor bank. The variable feedback equalizing input buffer of claim 1, wherein each of the transistors is activated in response to a bit of the equalizing control signal to be variably amplified. The equalizing control signal comprises a digital signal having a plurality of bits;
The equalizer is
A first transistor having one of a source and a drain connected to a first voltage source and another one of the source and drain connected to a first node;
Second and third transistors connected in series between the first node and a second voltage source and activated in response to the input signal and a first reference voltage, respectively;
A fourth transistor and a transistor bank connected in series between the first node and the second voltage source;
The fourth transistor is activated in response to an inverted oversampled signal, the transistor bank includes a plurality of fifth transistors connected in parallel to each other, and each of the fifth transistors is the first transistor of the transistor bank. In response to the activation state of each of the five transistors, the amplified output signal provided from the first node is activated in response to a bit of the equalizing control signal so as to be variably amplified. The decision feedback equalizing input buffer according to claim 1.   The transistor bank includes a plurality of sixth transistors, and each of the sixth transistors is connected in series to a corresponding fifth transistor, and each of the sixth transistors is activated in response to the first reference voltage. 14. The decision feedback equalizing input buffer of claim 13, wherein the decision feedback equalizing input buffer.   The decision feedback equalizing input buffer of claim 13, wherein the fifth transistors have different channel widths. The decision feedback equalizing input buffer is:
One of a source and a drain connected to the first voltage source, another one of the source and a drain connected to a second node, a gate of the first transistor, and a gate connected to the second voltage source. The seventh transistor,
An eighth transistor connected between junctions between the second node and the second transistor and the third transistor;
14. The decision feedback equalizing input buffer of claim 13, further comprising a ninth transistor connected between junctions between the second node, the fourth transistor, and the transistor bank.   The amplified output signal comprises an amplified even output signal and an amplified odd output signal, and the amplified even output signal is provided from the first node to invert the amplified even output signal. 17. The decision feedback equalizing input buffer of claim 16, wherein the processed signal is provided from the second node.   The method of claim 16, wherein the eighth transistor is activated in response to an inverted input signal, and the ninth transistor is activated in response to an inverted oversampled signal. Decision feedback equalizing input buffer.   17. The decision feedback equalizing input buffer of claim 16, wherein the eighth transistor is activated in response to a second reference voltage.   14. The decision feedback equalizing input buffer of claim 13, wherein the amplified output signal is provided from the first node and the second node. The equalizing control signal comprises a digital signal having a plurality of bits;
The equalizer is
A first transistor having one of a source and a drain connected to a first voltage source and another one of the source and drain connected to a first node;
Second and third transistors connected in series between the first node and a second voltage source and activated in response to the input signal and a first reference voltage, respectively;
A fourth transistor and a transistor bank connected in series between the first node and the second voltage source;
A voltage controller for generating a voltage control signal in response to the equalizing control signal,
The method of claim 1, wherein the fourth transistor is activated in response to the oversampled signal, and the fifth transistor causes a variable current to flow in response to the voltage control signal. Decision feedback equalizing input buffer. One of a source and a drain connected to the first voltage source, another one of the source and a drain connected to a second node, a gate of the first transistor, and a gate connected to the second voltage source. The sixth transistor,
A seventh transistor connected between junctions between the second node and the second transistor and the third transistor;
An eighth transistor connected between junctions between the second node, the fourth transistor, and the fifth transistor;
The decision feedback equalizing input buffer of claim 21, further comprising: The sampling unit is
A comparator that compares the amplified output signal with a reference voltage to generate a comparison signal;
A first sampling register that samples the comparison signal in response to a first sampling clock signal to generate an oversampled first signal;
A second sampling register that samples the comparison signal in response to a second sampling clock signal having a phase different from that of the first sampling clock signal to generate an oversampled second signal;
The decision feedback equalizing input buffer of claim 1, wherein the oversampled first and second output signals comprise the oversampled signal. The phase detector is
A first detection register that samples the oversampled first signal in response to a detector sampling clock signal and generates a first bit of a phase detector data signal;
A second detection register that samples the oversampled second signal in response to the detector sampling clock signal and generates a second bit of a phase detector data signal;
24. The decision feedback equalizing input buffer of claim 23, further comprising a decoder that generates the timing control signal in response to the first and second bits of the phase detector data signal. The amplified output signal comprises amplified even and odd output signals,
The sampling unit is
A first comparator for comparing the amplified even output signal with a reference voltage to generate a first comparison signal;
A first sampling register that samples the first comparison signal in response to a first sampling clock signal and generates an oversampled first even signal;
A second sampling register that samples the first comparison signal in response to a second sampling clock signal having a phase different from that of the first sampling clock signal and generates an oversampled second even signal;
A second comparator for comparing the amplified odd output signal with a reference voltage to generate a second comparison signal;
A third sampling register that samples the second comparison signal in response to the second sampling clock signal to generate an oversampled first odd signal;
A fourth sampling register for sampling the second comparison signal in response to a third sampling clock signal having a phase different from that of the second sampling clock signal and generating an oversampled second odd signal;
The decision feedback equalizing input buffer of claim 1, comprising: The phase detector is
A first detector register that samples the oversampled first even signal in response to a detector sampling clock signal to generate a first bit of the phase detector data signal;
A second detector register that samples the oversampled second even signal in response to the detector sampling clock signal and generates a second bit of the phase detector data signal;
A third detection register that samples the oversampled first odd signal in response to the detector sampling clock signal and generates a third bit of the phase detector data signal;
A fourth detection register that samples the oversampled second odd signal in response to the detector sampling clock signal and generates a fourth bit of the phase detector data signal;
A decoder for generating the timing control signal in response to the phase detector data signal;
26. The decision feedback equalizing input buffer of claim 25.   The timing control signal comprises a lock control signal, an up control signal, and a down control signal, wherein the values of the first and second bits are the same, and the values of the third and fourth bits are the same; When the lock control signal is activated and the values of the first and second bits are not the same, and the values of the third and fourth bits are in the sinus position, the down control signal is activated, 27. The decision feedback of claim 26, wherein the up control signal is activated when the values of the first and second bits are the same and the values of the third and fourth bits are not the same. Equalizing input buffer.   The decision feedback equalizing input buffer according to claim 1, further comprising a sampling clock generator for generating the sampling clock signal.   29. The decision feedback equalizing input buffer of claim 28, wherein the sampling clock generator comprises one of a phase locked loop and a delay locked loop. The sampling clock generator includes:
A timing controller for generating the sampling clock signal;
A clock generator for receiving a clock signal and generating a plurality of internal clock signals supplied to the timing controller;
29. The decision feedback equalizing input buffer of claim 28. The equalizer is
An equalizing coefficient controller that receives the variable equalizing control signal and generates an equalizing coefficient in response thereto;
A multiplier for multiplying the oversampled output signal by the equalizing factor to generate a double signal;
A differential amplifier for subtracting the output of the multiplier from the input signal to generate the amplified output signal;
The decision feedback equalizing input buffer of claim 1, comprising: The oversampled output signal comprises an oversampled even signal and an oversampled odd signal;
The equalizer is
An equalizing coefficient controller that receives the variable equalizing control signal and generates an equalizing coefficient in response thereto;
A first multiplier for multiplying the oversampled odd signal by the equalizing factor to generate an odd multiple signal;
A second multiplier for multiplying the oversampled even signal by the equalizing factor to generate an even multiple signal;
A first differential amplifier for subtracting the odd multiple signal from the input signal to generate an amplified even output signal;
A second differential amplifier for subtracting the even multiple signal from the input signal to generate an amplified odd output signal;
The decision feedback equalizing input buffer of claim 1, comprising: A plurality of addressable memory cells each comprising a data storage element;
A decoder for receiving an address from outside and generating a row signal and a column signal to access at least one of the addressable memory cells;
An equalizer that amplifies the voltage level difference between the input signal and the oversampled signal in response to the variable equalizing control signal to generate an amplified output signal;
A sampling unit that samples the amplified output signal in response to a sampling clock signal to generate the oversampled signal;
A phase detector that generates a timing control signal for controlling the timing of activation of the sampling clock signal in response to the phase of the oversampled signal;
A decision feedback equalizing input buffer comprising an equalizing controller for changing the variable equalizing control signal in response to the timing control signal;
A memory comprising: The amplified output signal comprises an amplified even output signal and an amplified odd output signal, and the oversampled signal comprises an oversampled first even signal and an oversampled second even signal, Comprising an oversampled first odd signal and an oversampled second odd signal;
The phase detector determines whether a phase difference exists between the oversampled first even signal and the oversampled second even signal, and the oversampled first odd signal and the oversampled signal. Determining whether there is a phase difference with the sampled second odd signal and generating a timing control signal comprising a lock control signal, an up control signal, and a down control signal in response to the determination; If there is no phase difference between the sampled first and second even signals and there is no phase difference between the oversampled first and second odd signals, the lock control signal is generated and the oversampled If there is a phase difference between the first and second even signals, the down control signal is generated, and a position between the oversampled first and second odd signals is generated. The memory of claim 33, wherein a difference generating said up control signal if present.   The memory of claim 34, wherein the amplified output signal comprises an amplified even output signal and an amplified odd output signal output in series by the equalizer.   The equalizer includes first and second equalizers, and the amplified output signal is in parallel with the amplified even output signal output by the first equalizer and the even output signal amplified by the second equalizer. 35. The memory of claim 34, comprising an amplified odd output signal that is output.   The memory of claim 34, wherein the equalizing controller changes the variable equalizing control signal in response to states of the up control signal, the down control signal, and the lock control signal. The equalizing controller is
The up control signal, the down control signal, and the lock control signal are received and, in response, an auxiliary up control signal and an auxiliary down control signal are generated, and the auxiliary up control signal is the up control signal and the down control. An equalizing control signal generator activated when at least one of the signals is activated, and the auxiliary down control signal is activated when the lock control signal is activated;
The auxiliary up control signal and the auxiliary down control signal are received, the variable equalizing control signal is generated in response, and the value of the variable equalizing control signal is changed in response to the activated auxiliary up control signal. A counter that increases and decreases in value of the variable equalizing control signal in response to the activated auxiliary down control signal;
35. The memory of claim 34, comprising: The equalizing control signal is:
The equalizer comprises a digital bank having a plurality of bits, the equalizer comprises a transistor bank comprising a plurality of transistors, and the amplified output signal is variably responsive to the activation state of each transistor in the transistor bank. 34. The memory of claim 33, wherein each of the transistors is activated in response to a bit of the equalizing control signal to be amplified. A memory controller for generating instruction and address signals;
Comprising a memory module comprising a plurality of memory devices, receiving the command and address signals, storing data in the memory devices in response thereto, and reading data from the memory devices;
Each memory device
A plurality of addressable memory cells each comprising a data storage element;
A decoder for receiving an address from outside and generating a row signal and a column signal to access at least one of the addressable memory cells;
An equalizer that amplifies the voltage level difference between the input signal and the oversampled signal in response to the variable equalizing control signal to generate an amplified output signal;
A sampling unit that samples the amplified output signal in response to a sampling clock signal to generate the oversampled signal;
A phase detector that generates a timing control signal for controlling the timing of activation of the sampling clock signal in response to the phase of the oversampled signal;
A decision feedback equalizing input buffer comprising an equalizing controller for changing the variable equalizing control signal in response to the timing control signal;
A memory system comprising: The amplified output signal comprises an amplified even output signal and an amplified odd output signal, and the oversampled signal is an oversampled first even signal and an oversampled second even signal, over Comprising a sampled first odd signal and an oversampled second odd signal;
The phase detector determines whether a phase difference exists between the oversampled first even signal and the oversampled second even signal, and the oversampled first odd signal and the oversampled signal. Determining whether there is a phase difference with the sampled second odd signal and generating a timing control signal comprising a lock control signal, an up control signal, and a down control signal in response to the determination; If there is no phase difference between the oversampled first and second even signals and there is no phase difference between the oversampled first and second odd signals, the lock control signal is generated and the oversampled. If there is a phase difference between the first and second even signals, the down control signal is generated, and a position between the oversampled first and second odd signals is generated. The memory system of claim 40, characterized in that for generating the up control signal and the difference is present.   42. The memory system of claim 41, wherein the equalizing controller changes the variable equalizing control signal in response to states of the up control signal, the down control signal, and the lock control signal. The equalizing controller is
The up control signal, the down control signal, and the lock control signal are received and, in response, an auxiliary up control signal and an auxiliary down control signal are generated, and the auxiliary up control signal is the up control signal and the down control. An equalizing control signal generator activated when at least one of the signals is activated, and the auxiliary down control signal is activated when the lock control signal is activated;
The auxiliary up control signal and the auxiliary down control signal are received, the variable equalizing control signal is generated in response, and the value of the variable equalizing control signal is changed in response to the activated auxiliary up control signal. A counter that increases and decreases in value of the variable equalizing control signal in response to the activated auxiliary down control signal;
42. The memory system of claim 41, comprising: The equalizing control signal is:
Comprising a digital signal having a plurality of bits, the equalizer comprising a transistor bank comprising a plurality of transistors, wherein the amplified output signal is variably responsive to the activation state of each transistor of the transistor bank; 41. The memory system of claim 40, wherein each of the transistors is activated in response to a bit of the equalizing control signal to be amplified. A first load connected in series; a first transistor activated in response to a first input signal; a second transistor having a first channel width and activated in response to a bias voltage; A first current path between a first voltage source and a second voltage source that causes the first current to flow;
A second load connected in series; a third transistor activated in response to a second input signal; a transistor bank having a plurality of fourth transistors connected in parallel and having a second channel width ; wherein is activated in response each of the fourth transistor to the corresponding bit of the variable equalizing control signal, said transistor bank specified transistor is selectively activated out of the variable equalizing control signal to thus the fourth transistor The output signal supplied to the junction of the first load and the first transistor is changed to the variable second current so that a variable second current flows as the effective channel width changes. it and a second current path between the response to be that before Symbol first voltage source to be variably amplified and said second voltage source Equalizer, characterized in that to amplify the difference in voltage level between the first and second input signal in response to the variable equalizing control signal, characterized.   46. The equalizer of claim 45, wherein the first and second loads comprise load transistors.   46. The equalizer of claim 45, wherein the first and second loads comprise load resistors. The first load and the first transistor are connected to a first node, the second load and the second transistor are connected to a second node,
A fifth transistor connected to a junction between the second node and the first transistor and the second transistor and activated in response to an inverted first input signal; the first node; and the third transistor; 46. The equalizer of claim 45, further comprising a sixth transistor connected to a junction with the transistor bank and activated in response to an inverted second input signal.   The transistor bank further comprises a plurality of seventh transistors, each of the seventh transistors being connected in series with a corresponding fourth transistor and being activated in response to the bias voltage. Item 46. The equalizer according to item 45. Amplifying the voltage difference between the input signal and the oversampled signal in response to the variable equalizing control signal to generate an amplified output signal;
Sampling the amplified output signal in response to a sampling clock signal to generate the oversampled signal;
Generating a timing control signal that adjusts an activation timing of the sampling clock signal in response to a phase of the oversampled signal;
Changing the variable equalizing control signal in response to the timing control signal, equalizing the input signal received from an input buffer. The amplified output signal comprises an amplified even output signal and an amplified odd output signal, and the oversampled signal is an oversampled first even signal and an oversampled second even signal, over Comprising a sampled first odd signal and an oversampled second odd signal;
The phase detector determines whether a phase difference exists between the oversampled first even signal and the oversampled second even signal, and the oversampled first odd signal and the oversampled signal. Determining whether there is a phase difference with the sampled second odd signal and generating a timing control signal comprising a lock control signal, an up control signal, and a down control signal in response to the determination; If there is no phase difference between the oversampled first and second even signals and there is no phase difference between the oversampled first and second odd signals, the lock control signal is generated and the oversampled. If there is a phase difference between the first and second even signals, the down control signal is generated, and a position between the oversampled first and second odd signals is generated. The method of claim 50, characterized in that for generating the up control signal and the difference is present. Changing the variable equalizing control signal comprises:
52. The method of claim 51, wherein the variable equalizing control signal is changed in response to states of the up control signal, the down control signal, and the lock control signal. Changing the variable equalizing control signal comprises:
The up control signal, the down control signal, and the lock control signal are received and, in response, an auxiliary up control signal and an auxiliary down control signal are generated, and the auxiliary up control signal is the up control signal and the down control. Activated when at least one of the signals is activated, and the auxiliary down control signal is activated when the lock control signal is activated;
The auxiliary up control signal and the auxiliary down control signal are received, the variable equalizing control signal is generated in response, and the value of the variable equalizing control signal is changed in response to the activated auxiliary up control signal. Increasing and decreasing the value of the variable equalizing control signal in response to the activated auxiliary down control signal;
52. The method of claim 51, comprising:

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