TWI265700B - Decision feedback equalization input buffer - Google Patents

Decision feedback equalization input buffer

Info

Publication number
TWI265700B
TWI265700B TW094114012A TW94114012A TWI265700B TW I265700 B TWI265700 B TW I265700B TW 094114012 A TW094114012 A TW 094114012A TW 94114012 A TW94114012 A TW 94114012A TW I265700 B TWI265700 B TW I265700B
Authority
TW
Taiwan
Prior art keywords
signal
timing
response
control signal
input buffer
Prior art date
Application number
TW094114012A
Other languages
Chinese (zh)
Other versions
TW200616392A (en
Inventor
Young-Soo Sohn
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020040037966A external-priority patent/KR100615597B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200616392A publication Critical patent/TW200616392A/en
Application granted granted Critical
Publication of TWI265700B publication Critical patent/TWI265700B/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439—Fixed structures
    • H04L2025/03445—Time domain
    • H04L2025/03471—Tapped delay lines
    • H04L2025/03484—Tapped delay lines time-recursive
    • H04L2025/0349—Tapped delay lines time-recursive as a feedback filter
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/0014—Carrier regulation
    • H04L2027/0024—Carrier regulation at the receiver end
    • H04L2027/0026—Correction of carrier offset
    • H04L2027/0038—Correction of carrier offset using an equaliser

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Memory System (AREA)

Abstract

In a decision feedback equalization (DFE) input buffer, timing and voltage errors, such as those caused by inter-symbol interference (ISI), are fully compensated. A variable equalizing coefficient is applied that accommodates, and compensates for, a range of timing errors TE or voltage errors VE that may be generated over a range of operating conditions. In this manner, accurate compensation is achieved, allowing for greater signal reliability and higher inter-circuit transfer rates. A decision feedback equalization (DFE) input buffer includes an equalizer that amplifies a difference in voltage level between an input signal and an oversampled signal in response to a variable equalizing control signal, the equalizer generating an amplified output signal. A sampling unit samples the amplified output signal in response to a sampling clock signal to generate the oversampled signal. A phase detector generates a timing control signal for controlling the timing of the activation of the sampling clock signal in response to a phase of the oversampled signal. An equalizing controller modifies the variable equalizing control signal in response to the timing control signal.
TW094114012A 2004-05-27 2005-04-29 Decision feedback equalization input buffer TWI265700B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020040037966A KR100615597B1 (en) 2004-05-27 2004-05-27 Data input circuit and method
US11/040,808 US7542507B2 (en) 2004-05-27 2005-01-21 Decision feedback equalization input buffer

Publications (2)

Publication Number Publication Date
TW200616392A TW200616392A (en) 2006-05-16
TWI265700B true TWI265700B (en) 2006-11-01

Family

ID=35433344

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094114012A TWI265700B (en) 2004-05-27 2005-04-29 Decision feedback equalization input buffer

Country Status (3)

Country Link
JP (1) JP4955224B2 (en)
DE (1) DE102005022684B4 (en)
TW (1) TWI265700B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4557948B2 (en) 2006-10-12 2010-10-06 ザインエレクトロニクス株式会社 Clock data recovery device
US7916780B2 (en) * 2007-04-09 2011-03-29 Synerchip Co. Ltd Adaptive equalizer for use with clock and data recovery circuit of serial communication link
JP2011113450A (en) 2009-11-30 2011-06-09 Toshiba Corp Memory interface circuit
JP2012244537A (en) * 2011-05-23 2012-12-10 Ricoh Co Ltd Data recovery method and data recovery device
JP6273679B2 (en) * 2013-03-04 2018-02-07 株式会社リコー Transmission / reception system, transmission / reception method, and reception apparatus
JP6079388B2 (en) * 2013-04-03 2017-02-15 富士通株式会社 Reception circuit and control method thereof
US9325489B2 (en) * 2013-12-19 2016-04-26 Xilinx, Inc. Data receivers and methods of implementing data receivers in an integrated circuit
JP6769317B2 (en) 2017-01-31 2020-10-14 富士通株式会社 Judgment feedback type equalizer and interconnect circuit
CN111726104A (en) * 2019-03-22 2020-09-29 瑞昱半导体股份有限公司 Decision feedback equalizer
KR20230000322A (en) * 2021-06-24 2023-01-02 에스케이하이닉스 주식회사 Electronic device performing for data align operation
CN115589225A (en) * 2021-07-05 2023-01-10 长鑫存储技术有限公司 Input buffer circuit and semiconductor memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0468834A (en) * 1990-07-05 1992-03-04 Fujitsu Ltd Sampling value estimating system for impulse response
DE69321427T2 (en) * 1992-08-06 1999-05-12 Koninkl Philips Electronics Nv Receiving arrangement for receiving a digital signal from a transmission medium with variable equalization means
JP2002184125A (en) * 2000-12-08 2002-06-28 Matsushita Electric Ind Co Ltd Digital signal reproducing device
JP4331641B2 (en) * 2004-04-09 2009-09-16 富士通株式会社 Receiver circuit having equalization circuit

Also Published As

Publication number Publication date
DE102005022684B4 (en) 2011-01-13
JP4955224B2 (en) 2012-06-20
TW200616392A (en) 2006-05-16
DE102005022684A1 (en) 2005-12-22
JP2005341582A (en) 2005-12-08

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