DE102005022684A1 - Decision feedback equalization input buffer for memory device, has equalizing controller that modifies variable equalizing control signal in response to timing control signal generated by phase detector - Google Patents

Abstract

A phase detector generates timing control signal for controlling the timing of activation of sampling clock signal in response to phase of the over sampled signal from a sampling unit. An equalizing controller modifies the variable equalizing control signal in response to the timing control signal. Independent claims are also included for the following: (1) method for equalizing input signal; (2) memory system; (3) memory device; and (4) equalizer.

Description

The This invention relates to a DFE input buffer, an equalizer, a memory device, a memory system and an equalization method.

communications between integrated circuits inevitably lead to Generation of timing errors and voltage errors, which in the between the chips exchanged signals occur. A common Source for such errors are Intersymbol Interference (ISI), which is bounded by limitations a channel bandwidth can be caused. To an interchip communication At high speed, the influence of ISI be minimized.

In current Systems use decision-response equalizer input buffers (Decision Feedback Equalizer Input Buffer), short DFE input buffer, used, to mitigate the adverse effects of ISI. Traditional DFE input buffers can however, the timing and voltage errors caused by ISI not compen- sating efficiently because the coefficients for equalization, i.e. for balancing, are fixed in such buffers.

1 shows a waveform diagram illustrating the effects caused by ISI with respect to timing error and voltage error. Waveforms A and B represent input signals received by a receiving circuit. The waveform B represents a normal input signal which is received without ISI error. The waveform A represents a faulty input signal with ISI. As can be seen, the erroneous input signal A experiences a timing error TE in the form of a time delay and a voltage error VE in the form of a reduced input voltage. The timing error TE and the voltage error VE are introduced during a signal transmission between circuits as a result of the ISI.

2 shows a block diagram of a conventional DFE input buffer 11 , In this conventional embodiment, an equalizing unit amplifies 10 the difference between an input signal IN with an ISI component and an odd oversampled output signal OD, which is multiplied by an equalizing coefficient α to compensate for the ISI component. As a result, a straight amplified output signal ed is generated. In other words, the just amplified output signal ed results according to ed = IN - (α · OD), where α · OD represents the ISI component, whereby the ISI component in the even amplified output signal ed is reduced.

At the same time the equalizer increases 10 the sum between the input signal IN or INB, where "xB" in the present description represents an inverted signal of a respective signal "x" which contains the ISI component and an even oversampled output signal EDB or ED multiplied by the equalizer coefficient α Compensate for ISI component. As a result, an odd amplified output signal od is generated. In other words, the odd amplified output signal od results according to od = IN - (α · ED), where α · ED represents the ISI component, whereby the ISI component in the odd amplified output signal od is reduced. Therefore, the equalizer includes 10 a circuit which generates the currently amplified output signal ed or edB, and a circuit which generates the odd amplified output signal od or odB. An equalizing circuit for generating the even output signal ed / edB will be described below with reference to FIG 3 described. An equalizing circuit for generating the odd output signal od / odB is constructed similarly to the circuit according to FIG 3 ,

An oversampling circuit 12 the currently amplified output signal ed sequentially samples in response to each sampling clock signal c0 and c90, and sequentially generates even oversampled output signals ED and ED90. In addition, the oversampling circuit samples 12 the odd amplified output signal od sequentially in response to each sampling clock signal c90 and c180 and sequentially generates first and second odd oversampled output signals OD90 and OD.

The sampling clock signals c0 and c90 have a phase difference of 90 degrees. A phase detector 14 determines the phase difference between the even oversampled output signals ED and ED90 and the phase difference between the odd oversampled output signals OD and OD90 and, in response, activates an up control signal up or a down control signal dn indicative of a counter 16 be transmitted. The phase difference is determined by the phase relationship between the data clock of the received data and that of the oversampling circuit 12 represents sample clock used to sample the incoming data.

The counter 16 increases a counter output signal cout having, for example, a plurality of digital bits when the up control signal up is active. The counter 16 The counter output signal cout decreases when the down control signal dn is active.

A timing control circuit 18 Sets activation timings or the phases of the sampling clock signals c0, c90, c180, c270 in response to the counter output signal cout. For example, if the value of the counter output signal cout has increased to a value higher than a predetermined value, for example, from 00..01 to 00..10, then the activation timing of each of the sampling clock signals c0, c90, c180, c270 is set so that that it will be activated later than before. On the other hand, when the value of the counter output signal cout has decreased to a lower value, the activation timing of each of the sampling clock signals c0, c90, c180, c270 is set to be activated earlier than before. In this way, the activation timings of the sampling clock signals c0, c90, c180, c270 by the timing control circuit 18 is set to compensate for a centering error occurring between the input signal IN and the sampling clock signals c0, c90, c180, c270 in the oversampling circuit 12 can exist.

A clock generator 20 generates a plurality of reference clock signals c1, c2, cn in response to an input clock signal CLK. The reference clock signals c1, c2, cn each have different phases from which the sampling clock signals c0, c90, c180, c270 are generated.

3 shows a schematic diagram of a component of Entzerreinheit 10 of the conventional DFE input buffer 2 , In the equalizer 10 the value of the received input signal IN is amplified to compensate for the voltage error of the input signal IN. For this purpose, the conventional Entzerreinheit 10 a fixed equalizing coefficient α of a predetermined value. In the equalizing circuit according to 3 Load transistors P1 and P2 act as load resistors and can be replaced by resistors. Differential transistors N1 and N2 receive the signal IN and INB, respectively. Differential transistors N3 and N4 receive the signal ODB and OD, respectively. Current source transistors N5 and N6 pull the respective currents I1 and I2 flowing through the first and second difference units, respectively. The value of the fixed equalizer coefficient α is determined as a function of the relative size of the channel widths of the transistors N5 and N6, which are fixed. In the circuit, a voltage value Vb represents a bias voltage having a constant value. Since the value of the equalizer coefficient α is fixed, the equalizer operates 10 in a constant state regardless of whether there is a timing error TE or a voltage error VE in the input signal IN. For this reason, the conventional Entzerreinheit 10 unable to accurately compensate for timing errors or voltage errors in the input signal over a wider range of operating conditions.

It The object of the invention is to provide a DFE input buffer, an equalizer unit, a memory device, a memory system and an equalization method indicate which are capable of being intersymbol interference (ISI) caused timing and voltage error comparatively well to compensate.

The Invention solves this task through a DFE input buffer with the features of Patent claim 1, by a memory device having the features of claim 31, by a storage system having the features of claim 33, by a Entzerreinheit with the features of claim 34 and by an equalizing method with the features of patent claim 39.

advantageous Further developments of the invention are specified in the dependent claims.

The use embodiments of the invention variable equalization coefficients, which correspond to the ranges of timing errors or voltage errors can be adjusted and in this way the same over a full range of operating conditions can be almost completely compensated. On this way, accurate compensation can be achieved, thereby a greater signal reliability and higher Data transfer rates between Circuits can be achieved.

Advantageous, Embodiments described below of the invention and the above for their better understanding explained, conventional embodiment are shown in the drawings. Show it:

1 a signal diagram illustrating the effect of a timing error and a voltage error caused by ISI,

2 a block diagram of a conventional DFE input buffer,

3 a schematic diagram of an equalizer of the conventional DFE input buffer 2 .

4 a block diagram of a DFE input buffer according to the invention,

5 a block diagram of a Entzerrsteuerschaltung invention 4 .

6 a block diagram of a Entzerreinheit invention 4 .

7A and 7B in each case a circuit diagram of a straight and an odd component of Entzerreinheit invention 4 .

8th a circuit diagram of an alternative embodiment of Entzerreinheit invention 4 .

9 a block diagram of a Überabtastschaltung invention 4 .

10 a block diagram of a phase detector according to the invention from 4 .

11A . 11B and 11C each a timing chart illustrating the conditions for generating a lock control signal, a down control signal and an up control signal,

12 a block diagram of an alternative embodiment of the DFE input buffer according to the invention and

13 a block diagram of a memory system according to the invention.

4 shows a block diagram of a DFE input buffer according to the invention. In the embodiment according to 4 strengthens an equalizer 10 ' the difference between an input signal IN with an ISI component and an odd oversampled output signal OD or ODB which is multiplied by a variable equalizer coefficient value β determined in response to a received value of an equalizer control signal eqco to compensate for the ISI component. As a result, a first even amplified output signal ed, edB is generated. At the same time the equalizer increases 10 ' the difference between the input signal IN with the ISI component and an even oversampled output signal ED or EDB which is multiplied by the variable equalizer coefficient value β to compensate for the ISI component. As a result, a first odd amplified output signal od, odB is generated. Therefore, the equalizer includes 10 ' a circuit which generates the currently amplified output signal ed / edB, and a circuit which generates the odd amplified output signal od / odB.

An oversampling circuit 12 the first just amplified output signal ed / edB sequentially samples in response to each sampling clock signal c0 and c90, and sequentially generates even oversampled output signals ED and ED90. In addition, the oversampling circuit samples 12 the first odd amplified output signal od / odB sequentially in response to each sampling clock signal c90 and c180, and sequentially generates first and second odd oversampled output signals OD90 and OD. The sampling clock signals c0, c90 and C180 each have a phase difference of 90 degrees. The even and odd oversampled output signals ED, OD are output as ISI compensation signals. The equalizer 10 ' and the oversampling circuit 12 may alternatively be implemented as a common circuit block or as independent circuit blocks.

A phase detector 14 ' Detects the phase difference between the even oversampled output signals ED and ED90 and the phase difference between the odd oversampled output signals OD and OD90, and outputs an up control signal up or a down control signal dn in response to the detected phase difference. In addition, the phase detector generates 14 ' a lock control signal lock when there is no phase difference in the even oversampled output signals ED, ED90 or in the odd oversampled output signals OD, OD90.

An equalization control circuit 22 receives the up control signal up, the down control signal dn and the lock control signal lock, which are received from the phase detector 14 ' and, in response, generates the equalizing coefficient control signal eqco. According to an embodiment, the equalization coefficient control signal eqco is a digital value having a plurality of digital bits. The equalization control circuit 22 increases the value of the equalizing coefficient control signal eqco when the up control signal up or the down control signal dn are activated. The activation of the up-control signal up or the down-control signal dn indicates the existence of a timing error, ie timing error, and / or a voltage error in the input signal IN. However, when the lock control signal lock is released, the value of the equalizer coefficient control signal eqco by the equalization control circuit becomes 22 reduced. The activation of the lock control signal lock indicates that there is substantially no voltage error or timing error in the input signal IN. In this way, the value of the equalizing coefficient control signal eqco is variably controlled and set in response to the received control signals up, dn, lock indicating whether a voltage error or timing error exists in the input signal. This enables efficient and accurate compensation of the timing errors and voltage errors in the input signal IN by adjusting the value of the equalizer control signal eqco and thereby the value of the equalizer coefficient β in response to whether timing and / or voltage errors exist in the input signal IN.

A counter 16 receives the up control signal up and the down control signal dn from the pha sendetektor 14 ' and generates a current output signal cout, which is a timing control circuit 18 is made available. In addition, the timing control circuit receives 18 Reference clock signals c1, c2, ... cn from a reference clock signal generator 20 which may comprise a phase-locked loop or a delay-locked loop, and generates sampling clock signals c0, c90, c180, c270 each having a phase shift of 90 degrees and their activation times from the timing control circuit 18 be controlled in response to the counter output signal cout. The operation of the counter 16 , the timing control circuit 18 and the clock signal generator 20 For the system according to the invention substantially correspond to the operation of the conventional embodiment, which in connection with above 2 has been described.

5 shows a block diagram of the Entzerrsteuerschaltung invention 22 out 4 , According to the illustrated embodiment, the equalization control circuit comprises 22 an equalization control signal generator 30 and a counter 32 , The equalization control circuit 22 receives the up control signal up, the down control signal dn and the lock control signal lock, which are received from the phase detector 14 ' be generated. If the up control signal up or the down control signal dn are active, then the equalization control signal generator is activated 30 an additional upstream signal uup. If the lock control signal lock is active, then the equalization control signal generator activates 30 an additional down signal ddn.

The counter 32 in the equalization control circuit 22 generates a raised equalizer coefficient control signal eqco in response to the additional upstream signal uup. In addition, the counter generates 32 a reduced equalizer coefficient control signal eqco in response to the additional downstream signal ddn. In this way, the value of the equalizing coefficient control signal eqco is variable.

6 shows a block diagram of Entzerreinheit invention 10 ' out 4 , The equalizer 10 ' includes an equalization coefficient control circuit 40 , a first and a second multiplier 42 . 46 and a first and second differential amplifier 44 . 48 , The equalizer coefficient control circuit 40 receives the binary equalizer coefficient control signal eqco, which is, for example, n-bit wide, and in response generates the value of the equalizer coefficient β. In this way, the equalizing coefficient β is variable because it is generated in response to the variable equalizing coefficient control signal eqco. For this reason, the invention can accurately compensate for the timing and voltage errors in received input signals as opposed to the conventional solutions over a range of operating conditions.

In the equalizer 10 ' becomes the variable equalizing coefficient β in the first multiplier 42 is multiplied by the odd oversampled output signal OD to produce an odd product output signal βOD. Analogously, the variable equalization coefficient β in the second multiplier 46 multiplied by the second even oversampled output signal ED to produce a straight product output signal βED. The first differential amplifier 44 provides the difference between the odd product output signal βOD and the input signal IN to produce the first just amplified output signal ed, and the second differential amplifier 48 provides the difference between the even product output signal βED and the input signal IN to generate the first odd amplified output signal od.

The 7A and 7B each show a circuit diagram of Entzerreinheit invention 10 ' according to 4 and 6 , How out 7A can be seen includes equalizer 10 ' first and second PMOS transistors P1, P2 and first to fifth NMOS transistors N1, N2, N3, N4 and N5. In addition, the Entzerreinheit includes 10 ' a first transistor bank TB1 with sixth NMOS transistors N6-1 ... N6-n and a second transistor bank TB2 with seventh NMOS transistors N7-1 ... N7-n. The inputs of the transistors N2 and N3 are respectively the inverted input signal INB and the inverted odd oversampled output signal ODB. The first and second PMOS transistors P1, P2 act as load resistors, and predetermined currents I1 and I2 flow through the transistors P1, P2, respectively. The voltage level of the first even amplified output signal ed is in accordance with the current I1, which flows through the transistor P1, the transistor N1, which is activated in response to the input signal IN, and the transistor N5, which is activated in response to a bias voltage Vb, and in accordance with the current I2 determined by the transistor P2, the transistor N4 which is activated in response to the odd oversampled output signal OD, and the transistors N6-1 ... N6-n of the first transistor bank TB1 and the selectively activated ones Transistors N7-1 ... N7-n of the second transistor bank TB2 flows. The transistors N7-1 ... N7-n of the second transistor bank TB2 are selectively activated in response to the states of the bits of the variable equalizer coefficient control signal eqco. Each corresponding transistor pair in the first transistor bank TB1 and the second transistor bank TB2, for example, the transistors N6-1 and N7-1, the transistors N6-2 and N7-2, etc., pull in response to the active or inactive state of the corresponding bit of the equalizer control signal eqco electricity. In this way, the first just amplified output signal ed in response to the Amplification of the corresponding values of the first current I1 and the second current I2 generated. The voltage level of the inverted even amplified output signal edB is determined analogously.

The transistors N6-1 ... N6-n of the first transistor bank TB1 respond to the bias voltage Vb, and the transistors N7-1 ... N7-n of the second transistor bank TB2 respond to the variable equalizer coefficient control signal eqco. Each of the transistors N7-1 ... N7-n of the second transistor bank TB2 includes a gate connected to a corresponding bit of the variable equalizer coefficient control signal eqco. By forming the individual transistors N7-1 ... N7-n of the second transistor bank TB2 with different channel widths and by forming the individual transistors N6-1 ... N6-n of the first transistor bank TB1 with different channel widths, which correspond to corresponding channel widths of the second Transistor bank TB2 correspond, pulling each corresponding series transistor pair, ie N6-1, N7-1, a corresponding other current. By forming the respective transistor channel widths of the transistors N7-1... N7-n of the second transistor bank TB2 such that, for example, a current corresponding to a binary multiple of the current drawn by the adjacent transistor is drawn, the second current I2 and thus the corresponding one Equalization coefficient β for the equalizer purity 10 ' be made variable adjustable, so that a set value has a direct reference to the binary value of the variable Entzerkkoeffizientensteuersignals eqco. In this way, the variable control of the system distortion coefficient β can be realized. In an alternative embodiment, the channel width of each of the transistors N6-1 ... N6-n of the first transistor bank TB1 and the transistors N7-1 ... N7-n of the second transistor bank TB2 may be made equal. In this case, the current drawn by each of the transistors is the same, but if additional transistors are activated, then the total drawn current can be varied to achieve a variable system sizing coefficient .beta.

In alternative embodiment may instead of the inverted input signal INB and the inverted odd oversampled output signal ODB a reference voltage Vref to the gates of the transistors N2 and N3 are created.

The equalizing circuit 10 ' according to 7A is implemented to generate the first even amplified output signals ed, edB. An analogue odd-numbered equalizer circuit 10 '' according to 7B can be used to generate the first odd amplified output signal od, odB. Analogous first and second transistor banks TB1, TB2 are used for the odd equalizer circuit 10 '' are provided so that the odd amplified output signals od, odB are generated in response to the variable equalizing coefficient control signal eqco.

8th shows a circuit diagram of an alternative embodiment of the Entzerreinheit invention 10 ''' out 4 , In this embodiment, a single transistor N8 is connected in series between the node connecting transistors N3 and N4 and a ground reference voltage level. A voltage control signal VCO is applied to a gate of the transistor N8. The voltage control signal VCO is variable and the voltage of the voltage control signal VCO is controlled by a voltage control circuit 60 controlled in response to the variable equalizing coefficient control signal eqco. For example, if the variable equalizing coefficient control signal eqco increases, the voltage control circuit responds 60 with an increase in the voltage level of the voltage control signal VCO. In addition, the voltage control circuit reacts 60 with a lowering of the voltage level of the voltage control signal VCO when the variable equalizing coefficient control signal eqco decreases. The current flow through the transistor N8 is variable and controlled based on the variable value of the voltage control signal VCO. This allows variable control of the resulting equalizing coefficient β of the equalizer 10 ''' because the equalizer coefficient value β is a direct function of the current flow through the transistor N8, as described above.

9 shows a block diagram of a Überabtastschaltung invention 12 out 4 , The oversampling circuit 12 includes a first and a second comparator 70 . 72 and first to fourth D flip-flops DFF1, DFF2, DFF3, DFF4. The first comparator 70 receives and compares the currently amplified output signal ed and a reference voltage Vref. If the level of the even amplified output signal ed is greater than the level of the reference voltage Vref, then the first comparator outputs a high level even comparison signal Ded to the first and second D flip-flops DFF1, DFF2. The second comparator 72 receives and compares the odd amplified output signal od and the reference voltage Vref. When the level of the odd amplified output signal od is greater than the level of the reference voltage Vref, the second comparator outputs an odd comparison signal Dod of a high level to the third and fourth D flip-flops DFF3, DFF4.

The first D-type flip-flop DFF1 latches the even comparison signal Ded in response to the first sampling clock signal c0, and outputs the first output signal ED that has just been oversampled. The second D flip-flop DFF2 stores the even comparison signal Ded in response to the second sample clock signal c90 between and outputs the second output signal ED90 which has just been oversampled. In this way, the first and second even oversampled output signals ED, ED90 are generated sequentially when the oversampling circuit 12 the even comparison signal Ded is sampled twice in response to the first and second sampling clock signals c0, c90 having a phase shift of 90 degrees.

In an analogous manner, the third D flip-flop DFF3 latches the odd comparison signal Dod in response to the second sampling clock signal c90 and outputs the first odd oversampled output signal OD90. The fourth D flip-flop DFF4 latches the odd comparison signal Dod in response to the third sampling clock signal c180 and outputs the second odd oversampled output signal OD. In this way, the first and second odd oversampled output signals OD90, OD are sequentially generated when the oversampling circuit 12 the odd comparison signal Dod is sampled twice in response to the second and third sampling clock signals c90, c180 having a phase shift of 90 degrees.

10 shows a block diagram of the phase detector according to the invention 14 ' out 4 , In the illustrated embodiment, the phase detector comprises 14 ' a fifth, a sixth, a seventh and an eighth D-flip-flop DFF5, DFF6, DFF7 and DFF8 and a decoder 80 , The fifth D-type flip-flop DFF5 samples the first output signal ED that has just been oversampled in response to the fourth sampling clock signal c270. The sixth D-type flip-flop DFF6 samples the second output signal ED90 which has just been oversampled in response to the fourth sampling clock signal c270. The seventh D-type flip-flop DFF7 samples the first odd oversampled output signal OD90 in response to the fourth sampling clock signal c270. The eighth D-type flip-flop DFF8 samples the second odd oversampled output signal OD in response to the fourth sampling clock signal c270. While the phase detector 14 ' In the embodiment described above, the sampling clock signal c270 is used to sample the even and odd oversampled output signals ED, ED90, OD, OD90, another sampling clock signal may be used for this purpose, for example one of the sampling signals c0, c90 or c180. Alternatively, a clock signal received at an external terminal may also be used.

The output data signals data of the fifth, sixth, seventh and eighth D flip-flops DFF5, DFF6, DFF7 and DFF8 are respectively sent to the decoder 80 in response to which the up control signal up, the down control signal dn and the lock control signal lock are generated. In one embodiment, the up control signal is up from the decoder 80 activated when the phases of the sampling clock signals c0, c90, c180 lead the phase of the input data signal IN. If the phases of the sampling clock signals c0, c90, c180 go after the phase of the input data signal IN, then the decoder activates 80 the down control signal dn. If the phases of the sampling clock signals and the input data signal IN are tuned, then the decoder activates 80 the lock control signal lock.

The operation of the decoder 80 according to 10 will now be described with reference to the timing diagrams according to 11A . 11B and 11C which respectively show conditions for generation of the lock control signal lock, the down control signal dn and the up control signal up.

Assuming, for example, that the input data signal IN is continuously inputted with a data "0110", then "0" is a valid value of the first even amplified output signal, while "1" is a valid value of the second even amplified output signal ed from the equalizer circuits 10 ' . 10 '' or 10 ''' be issued. On the other hand, in the same input data, "1" is a valid value of the first odd amplified output signal od, while "0" is a valid value for the second odd amplified output signal od as supplied by the equalizing circuits 10 ' . 10 '' or 10 ''' be issued. Therefore, the order of the even input data ed is "01" while the order of the odd input signals od is "10". Accordingly, the data signal data, as shown 11A As can be seen, at the first rising edge of the fourth sample clock signal c270, a value of "0011" is present. The data signal data is sent to the decoder 80 which determines that the first even oversampled output signal ED and the second even oversampled output signal ED90 have the same value, in the example shown the value "0." Since the first and second even oversampled output signals ED and ED90 are from the same even data from the first even data ed having a value "0", the values of the signals ED and ED90 are identical. Analog determines the decoder 80 Also, the second odd oversampled output signal OD and the first odd oversampled output signal OD90 have the same value "1." Since the first and second odd oversampled output signals OD90 and OD are sampled from the same odd data, namely, the first odd data od with a value "1", the values of the signals OD and OD90 are identical. In response to this determination, the lock control signal becomes lock from the decoder 80 enabled, since both signals ED and ED90 have the same value "0" and both signals OD and OD90 the same value "1" aufwei sen.

In addition, the data signal data has a value of "1100" on the second rising edge of the fourth sampling clock signal c270. The data signal data is sent to the decoder 80 which determines that the first just oversampled output signal ED and the second even oversampled output signal ED90 have the same value, in the example shown the value "1." Since the first and second even oversampled output signals ED and ED90 are from the same even data from the second even data ed having a value "1", the values of the signals ED and ED90 are identical. Analog determines the decoder 80 Also, the second odd oversampled output signal OD and the first odd oversampled output signal OD90 have the same value "0." Since the first and second odd oversampled output signals OD90 and OD are sampled from the same odd data, namely, the second odd data od with a value "0", the values of the signals OD and OD90 are identical. In response to this determination, the lock control signal lock becomes continuous from the decoder 80 is released, since both signals ED and ED90 have the same data value "1" and both signals OD and OD90 have the same data value "0". In other words, valid data is output which confirms that the rising edge of the clock signal c0 is located at an appropriate position relative to the input even data ed, for example, in the middle of the even data ed, and the rising edge of the clock signal c180 is arranged at an appropriate position relative to the inputted odd data od, for example, in the middle of the odd data od.

Is unlike the input data 11A Assuming that the input data signal IN is continuously inputted with a data "1001", then "1" is a valid value of the first even amplified output signal ed, while "0" is a valid value of the second even amplified output signal ed as supplied by the equalizing circuits 10 ' . 10 '' or 10 ''' be issued. On the other hand, at the same input data, "0" is a valid value of the first odd amplified output signal od, while "1" is a valid value for the second odd amplified output signal od as supplied by the equalizing circuits 10 ' . 10 '' or 10 ''' be issued. Therefore, the order of the even input data ed is "10" while the order of the odd input signals od is "01". Accordingly, the data signal data, as shown 11B As can be seen, at the first rising edge of the fourth sample clock signal c270, a value of "1000" is present, although the current value of the data signal data should be "1100". The data signal data is sent to the decoder 80 which determines that the first just-oversampled output signal ED and the second just-oversampled output signal ED90 have different data values "1" and "0", and also determines that the first odd oversampled output signal OD90 and the second odd oversampled output signal OD are the same Value "0." In response to this determination, the down control signal dn from the decoder 80 enabled to shift the rising edge of the clock signal c0 more toward the center of the even data signal ed. Activation of the down control signal dn causes activation of the sampling clock signals c0, c90, c180 at an earlier timing by the timing control circuit 18 as stated above. In addition, the data signal data at the second rising edge of the fourth sampling clock signal c270 has a value of "0111", although the current value of the data signal data should be "0011". The data signal data is sent to the decoder 80 which determines that the first just-oversampled output signal ED and the second just-oversampled output signal ED90 have different data values "0" and "1", and also determines that the first odd oversampled output signal OD90 and the second odd oversampled output signal OD are the same Data value "1." In response to this determination, the down control signal dn is continuously received from the decoder 80 enabled to shift the rising edge of the clock signal c0 more toward the center of the even data signal ed.

It is assumed that, as in 11B , the input data signal IN is continuously inputted with a data "1001", then "1" is a valid value of the first even amplified output signal ed, while "0" is a valid value of the second even amplified output signal ed as supplied by the equalizing circuits 10 ' . 10 '' or 10 ''' be issued. On the other hand, at the same input data, "0" is a valid value of the first odd amplified output signal od, while "1" is a valid value for the second odd amplified output signal od as supplied by the equalizing circuits 10 ' . 10 '' or 10 ''' be issued. Therefore, the order of the even input data ed is "10" while the order of the odd input signals od is "01". Accordingly, the data signal data, as shown 11C It is clear that at the first rising edge of the fourth sample clock signal c270, a value of "1110" is required, although the current value of the data signal data should be "1100". The data signal data is sent to the decoder 80 which determines that the first just-oversampled output signal ED and the second just-oversampled output signal ED90 have the same data "1", and to determines that the first odd oversampled output signal OD90 and the second odd oversampled output signal OD have different data values "1" and "0". In response to this determination, the up control signal is up from the decoder 80 enabled to shift the rising edge of the clock signal c180 more toward the center of the odd data signal od. Activation of the up control signal up causes activation of the sampling clock signals c0, c90, c180 at a later time by the timing control circuit 18 as stated above. In addition, the data signal data at the second rising edge of the fourth sampling clock signal c270 has a value of "0001", although the current value of the data signal data should be "0011". The data signal data is sent to the decoder 80 which determines that the first just-oversampled output signal ED and the second just-oversampled output signal ED90 have the same data value "0", and further determines that the first odd oversampled output signal OD90 and the second odd oversampled output signal OD have different data values "0". and "1." In response to this determination, the up-control signal up is continuously output from the decoder 80 enabled to shift the rising edge of the clock signal c180 more toward the center of the odd data signal od. Activation of the up control signal up causes activation of the sampling clock signals c0, c90, c180 at a later time by the timing control circuit 18 as stated above.

12 shows a block diagram of an alternative embodiment of the DFE input buffer according to the invention. In this embodiment, the equalizer generates 10 '' in response to the input signal IN, a single serially amplified output signal in stead of the even and odd amplified output signal ed, od, resulting from the above-described equalizer unit 10 ' be generated. In this case, only a single in 7 shown Entzerrschaltung 10 ' required. In addition, only a single over-sampled output signal ain1 is multiplexed with that of the control circuit 22 generated equalization coefficient control signal eqco for Entzerreinheit 10 '' fed back. The single serially amplified output signal in may, for example, correspond to the even component of the signal.

Additionally generated in the embodiment according to 12 the timing control circuit 18 ' a plurality of sample clock signals ck1, ck2, ck3, ck4, which are sequential in response to the clock signal generator 20 generated reference clock signals c1, c2, ... cn are generated. As in the above-described embodiment, the timing of the sampling clock signals from the timing control circuit 18 ' in response to the counter output signal cout of the counter 16 controlled. In the illustrated embodiment, four sample clock signals ck1, ck2, ck3, ck4 are used which correspond to the four clock signals c0, c90, c180, c270 which, as in the embodiment described above, each have a phase shift of 90 degrees. In this embodiment, all the sampling clock signals ck1, ck2, ck3, ck4 including the fourth sampling clock ck4 of the oversampling circuit 12 ' in response, providing the first and second through fourth oversampled output signals ain1, ain2, ain3, ain4 to the phase detector 14 ' which performs an analogous operation as that described with reference to 10 described phase detector 14 ' and the lock control signal lock generates which of the equalizer coefficient control circuit 22 is provided, and the up-control signal up and the down-control signal dn generate which of the equalizer coefficient control circuit 22 and the counter 16 be provided as stated above.

While the circuit according to 4 provides a double data rate solution which interleaves the data by using even and odd branches, temporal interleaving is not required in low data rate applications as compared to the processing rate of the input buffer circuit. Under these conditions, the embodiment according to 12 be used. This embodiment offers the advantage of a single input branch, which simplifies the hardware configuration and reduces the required circuit footprint and manufacturing cost.

On this way, a DFE buffer can be provided in which Timing error and voltage error virtually completely compensated become. By implementing the variable equalizer coefficient β in the equalizer component the timing and voltage errors over the entire operating condition range compensated. this leads to to more reliable Signals and higher transmission rates between the circuits.

The invention can be applied to all types of integrated circuits, including memory devices and memory systems. In one embodiment as a memory device, the memory device may include a plurality of addressable memory cells, each memory cell having a data storage element. A decoder receives an address from an external source and generates a row signal and a column signal for addressing at least one the addressable memory cells. The DFE input buffer may be used in a memory device to receive signals transmitted from external sources located off-chip.

13 shows a block diagram of a memory system according to the invention. The memory system comprises a memory control circuit 100 which generates a command COM and address signals, such as bank addresses BA and addresses ADD, and a memory module 300 , The memory module 300 includes a plurality of memory devices 300-1 . 300-2 , ..., 300-n and receives the command COM and the address signals BA, ADD. In response, the memory module stores 300 Data Din / Dout in the memory devices 300-1 . 300-2 , ..., 300-n or reads data Din / Dout from the memory devices 300-1 . 300-2 , ..., 300-n out. An inventive DFE input buffer may be used in the memory devices to receive the signals transmitted from off-chip sources.

Claims (42)

DFE input buffer characterized by - an equalizer ( 10 ' ) which amplifies a voltage level difference between an input signal (IN) and an oversampled signal (ED, OD) in response to a variable equalization control signal (eqco) and generates an amplified output signal (ed, edB, od, odB), - a sampling unit ( 12 ) which samples the amplified output signal (ed, edB, od, odB) in response to a sampling clock signal (c0, c90, c180) to produce the oversampled signal (ED, OD), - a phase detector ( 14 ' ) which generates a timing control signal (up, dn, lock) for timing the activation of the sampling clock signals (c0, c90, c180, c270) in response to a phase of the oversampled signal (ED, OD), and - an equalization control circuit ( 22 ) which modifies the variable equalization control signal (eqco) in response to the timing control signal (up, dn, lock). DFE input buffer according to claim 1, characterized in that the equalizer ( 10 ' ) produces a straight amplified output signal (ed, edB) and an odd amplified output signal (od, odB). DFE input buffer according to claim 2, characterized in that the sampling circuit ( 12 ) samples the currently amplified output signal (ed, edB) with a first and a second sampling clock signal (c0, c90) having a phase shift of 90 degrees to each other, and in response thereto a first even oversampled signal (ED) and a second even overdubget tete signal (ED90) is generated, wherein the sampling circuit ( 12 ) samples the odd amplified output signal (od, odB) with the second and third sample clock signals (c90, c180) having a phase shift of 90 degrees to each other, and in response thereto a first odd oversampled signal (OD90) and a second odd oversampled one Signal (OD) generated. DFE input buffer according to claim 3, characterized in that the phase detector ( 14 ' ) determines whether a phase shift exists between the first even oversampled signal (ED) and the second even oversampled signal (ED90), and determines whether a phase shift occurs between the first odd oversampled signal (OD90) and the second odd oversampled signal (OD). exists, and in response generates the timing control signal (up, dn, lock). DFE input buffer according to claim 4, characterized in that the phase detector ( 14 ' ) in response to the first sample clock signal (c0) and / or the second sample clock signal (c90) and / or the third sample clock signal (c180) and / or a fourth sample clock signal (c270) which is 90 ° out of phase with the third sample signal (c180) Degree determines whether a phase shift exists between the first even oversampled signal (ED) and the second even oversampled signal (ED90), and determines whether a phase shift between the first odd oversampled signal (OD90) and the second odd oversampled signal (OD90). OD) exists. DFE input buffer according to claim 4 or 5, characterized characterized in that the timing control signal (up, dn, lock) on Lock control signal (lock), up control signal (up) and on From wärtsteuersignal (dn), wherein the lock control signal (lock) is active, if no phase shift between the first and the second even oversampled Signal (ED, ED90) exists and if there is no phase shift between the first and second odd oversampled signals (OD90, OD), the down control signal (dn) is active when a phase shift between the first and the second straight over-sampled Signal (ED, ED90) exists and the up control signal (up) is activated is when a phase shift between the first and the second odd oversampled signal (OD90, OD) exists. DFE input buffer according to claim 1, characterized in that - the amplified output signal amplifies a straight output signal (ed, edB) and an odd amplified output signal (od, odB), wherein the oversampled signal comprises a first even oversampled signal (ED), a second even oversampled signal (ED90), a first odd oversampled signal (OD90) and a second odd oversampled signal (OD), and - the phase detector ( 14 ' ) determines whether a phase shift exists between the first even oversampled signal (ED) and the second even oversampled signal (ED90), and determines whether a phase shift occurs between the first odd oversampled signal (OD90) and the second odd oversampled signal (OD). exists, and in response generates the timing control signal (up, dn, lock) comprising the lock control signal (lock), the up control signal (up) and the down control signal (dn), the lock control signal (lock) being active if there is no phase shift between the first and second odd over-sampled signals (ED, ED90) and when there is no phase shift between the first and second odd oversampled signals (OD90, OD), the down control signal (dn) is active when a phase shift between the first and second signals the second even oversampled signal (ED, ED90) exists, and the exp ertsteuersignal (up) is activated when a phase shift between the first and the second odd oversampled signal (OD90, OD) exists. DFE input buffer according to claim 6 or 7, characterized in that the equalization control circuit ( 22 ) sets the variable equalizing control signal (eqco) in response to the state of the up control signal (up), the down control signal (dn) and the lock control signal (lock). DFE input buffer according to one of Claims 6 to 8, characterized in that the equalization control circuit ( 22 ) comprises the following components: - an equalization control signal generator ( 30 ) which receives the up control signal (up), the down control signal (dn) and the lock control signal (lock) and generates an additional up control signal (uup) and an additional down control signal (ddn) in response thereto, the additional up control signal (uup) being active when the up control signal (up) and / or the down control signal (dn) is active, and the additional down control signal (ddn) is active when the lock control signal (lock) is active, and - a counter ( 32 ) which receives the additional up control signal (uup) and the additional down control signal (ddn) and in response generates the variable equalizing control signal (eqco), the counter ( 32 ) increases the value of the equalization control signal (eqco) when the additional up-control signal (uup) is active, and wherein the counter ( 32 ) decreases the value of the equalization control signal (eqco) when the additional down control signal (ddn) is active. DFE input buffer according to one of claims 1 to 9, characterized in that the Entzerrsteuersignal (eqco) comprises a digital signal having a plurality of bits and the Entzerreinheit ( 10 ' ) comprises a transistor bank having a plurality of transistors (N7-1 to N7-n), each of the transistors (N7-1 to N7-n) being activatable in response to a bit of the equalization control signal (eqco) such that the amplified output signal (ed, edB, od, odB) can be variably amplified in response to the activation states of the respective transistors (N7-1 to N7-n) of the transistor bank. DFE input buffer according to one of claims 1 to 10, characterized in that the Entzerrsteuersignal (eqco) comprises a digital signal having a plurality of bits and the Entzerreinheit ( 10 ' ) comprises the following components: a first transistor (P1) whose source terminal or drain terminal is coupled to a first voltage source (VDD) and whose remaining terminal is coupled to a first node, a second transistor (N1) and a third transistor (N5 ) serially connected between the first node and a second voltage source, the second transistor (N1) being activatable in response to the input signal (IN) and the third transistor (N5) being activatable in response to a first reference voltage (Vb) and a fourth transistor (N3) and a transistor bank connected between the first node and the second voltage source, wherein the fourth transistor (N3) is activated in response to an inverted oversampled signal (ODB) and the transistor bank has a plurality of fifth transistors (N7-1 to N7-n) connected in parallel, each in response to one bit of the Equalizing control signal (eqco) so that the amplified output signal (ed) provided at the first node is variably amplifiable in response to the activation states of the respective fifth transistors (N7-1 to N7-n) of the transistor bank. DFE input buffer according to Claim 11, characterized the transistor bank has a plurality of sixth transistors (N6-1 to N6-n), each of the sixth transistors (N6-1 to N6-n) in series with a corresponding fifth transistor (N7-1 to N7-n) and in response to the first reference voltage (Vb) is activatable. DFE input buffer according to claim 11 or 12, characterized in that the fifth transistors (N7-1 to N7-n) have different channel widths. DFE input buffer according to one of claims 11 to 13, characterized by - one seventh transistor (P2), its source or drain is coupled to the first voltage source (VDD), the remaining one Terminal is coupled to a second node and its gate to the gate of the first transistor (P1) and the second voltage source coupled, - one eighth transistor (N2), which is between the second node and the junction of the second and third transistors (N1, N5) is looped in, and - one ninth transistor (N4) connected between the second node and the junction between the fourth transistor (N3) and the Transistor bank is looped. DFE input buffer according to Claim 14, characterized that the reinforced Output signal a straight amplified Output signal (ed, edB) and an odd amplified output signal (od, odB) which is just reinforced Output signal (ed) can be provided at the first node and an inverted one Signal (edB) of the straight amplified Output signal (ed) can be provided at the second node. DFE input buffer according to claim 14 or 15, characterized characterized in that the eighth transistor (N2) in response to a inverted input signal (INB) is activated and the ninth Transistor (N4) in response to an inverted oversampled Signal (OD) can be activated. DFE input buffer according to claim 14 or 15, characterized characterized in that the eighth transistor (N2) in response to a second reference voltage (Vref) can be activated. DFE input buffer according to one of claims 11 to 17, characterized in that the amplified output signal (ed, edB) can be provided at the first node and at the second node. DFE input buffer according to one of claims 1 to 10, characterized in that the Entzerrsteuersignal (eqco) comprises a digital signal having a plurality of bits and the Entzerreinheit ( 10 ''' ) comprises the following components: a first transistor (P1) whose source terminal or drain terminal is coupled to a first voltage source (VDD) and whose remaining terminal is coupled to a first node, a second transistor (N1) and a third transistor (N5 ) serially connected between the first node and a second voltage source, the second transistor (N1) being activatable in response to the input signal (IN) and the third transistor (N5) being activatable in response to a reference voltage (Vb) , and a fourth transistor (N3) and a fifth transistor (N8) connected between the first node and the second voltage source, the fourth transistor (N3) being activatable in response to an oversampled signal (ODB) and the fifth transistor (N3) Transistor (N8) pulls a variable current in response to a voltage control signal (VCO), and - a voltage control circuit ( 60 ) for providing the voltage control signal (VCO) in response to the equalization control signal (eqco). DFE input buffer according to claim 19, characterized by - one sixth transistor (P2), its source or drain is coupled to the first voltage source (VDD), the remaining one Terminal is coupled to a second node and its gate to the gate of the first transistor (P1) and the second voltage source coupled, - one seventh transistor (N2) connected between the second node and the junction of the second and third transistors (N1, N5) is looped in, and - one eighth transistor (N4), which is between the second node and the junction between the fourth transistor (N3) and the fifth transistor (N8) is looped. DFE input buffer according to one of Claims 1 to 20, characterized in that the sampling circuit ( 12 ) comprises the following components: - a comparator ( 70 ) which compares the amplified output signal (ed) with a reference voltage (Vref) and generates a comparison signal (Ded), - a first sampling register (DFF1) which samples the comparison signal (Ded) in response to a first sampling clock signal (c0) generating a first oversampled signal (ED), and - a second sampling register (DFF2) which samples the comparison signal (Ded) in response to a second sampling clock signal (c90) having a phase different from the first sampling clock signal (c0) generating a second oversampled signal (ED90), wherein the first and second oversampled output signals (ED, ED90) form the oversampled signal. DFE input buffer according to claim 21, characterized in that the phase detector ( 14 ' ) comprises: a first detection register (DFF5) which samples the first oversampled signal (ED) in response to a detector sample clock signal (CK) Generating a bit of the phase detector data signal, a second detection register (DFF6) which samples the second oversampled signal (ED90) in response to the detector sample clock signal (CK) to produce a second bit of the phase detector data signal (data); Decoder ( 80 ) which generates the timing control signal (lock, up, dn) in response to the first and second bits of the phase detector data signal (data). DFE input buffer according to one of Claims 1 to 20, characterized in that the amplified output signal comprises even and odd amplified output signals (ed, od) and the sampling circuit ( 12 ) comprises the following components: a first comparator ( 70 ) which compares the currently amplified output signal (ed) with a reference voltage (Vref) and generates a first comparison signal (Ded), - a first sampling register (DFF1) which generates the first comparison signal (Ded) in response to a first sampling clock signal (c0) a second scan register (DFF2) which samples the first comparison signal (Ded) in response to a second sampling clock signal (c90) having a phase other than the first sampling clock signal (c0 ) to generate a second even oversampled signal (ED90), - a second comparator ( 72 ) which compares the odd amplified output signal (od) with the reference voltage (Vref) and generates a second comparison signal (Dod), - a third scan register (DFF3) which outputs the second comparison signal (Dod) in response to the second sampling clock signal (c90) a fourth sample register (DFF4) which samples the second comparison signal (Dod) in response to a third sample clock signal (c180) having a different phase than the second sample clock signal (DFF4). c90) to produce a second odd oversampled signal (OD). DFE input buffer according to claim 23, characterized in that the phase detector ( 14 ' ) comprises the following components: a first detection register (DFF5) which samples the first even oversampled signal (ED) in response to a detector sampling clock signal (CK) to produce a first bit of the phase detector data signal, a second detection register (DFF6 ) which samples the second even oversampled signal (ED90) in response to the detector sampling clock signal (CK) to produce a second bit of the phase detector data signal (data), - a third detection register (DFF7) representing the first odd oversampled signal (OD90). in response to the detector strobe clock signal (CK) to generate a third bit of the phase detector data signal (data), a fourth detection register (DFF8) which samples the second odd oversampled signal (OD) in response to the detector strobe clock signal (CK) generate a fourth bit of the phase detector data signal (data), and - a decoder ( 80 ) which generates the timing control signal (lock, up, dn) in response to the phase detector data signal (data). DFE input buffer according to Claim 24, characterized the timing control signal (up, dn, lock) is a lock control signal (lock), an up-control signal (up) and a down control signal (dn), wherein the lock control signal (lock) is active, if the values of the first and second bits are the same and if the values of the third and fourth bits are equal, the down control signal (dn) is active if the values of the first and second bits are not are equal and the values of the third and fourth bits are equal, and the up-control signal (up) is active when the values of the first and second bits are equal and the values of the third and fourth bits are not equal. DFE input buffer according to one of claims 1 to 25, characterized by a sampling clock signal generator, which generates the sampling clock signal (c0, c90, c180, c270). DFE input buffer according to Claim 26, characterized the sampling clock signal generator has a phase locked loop and / or a delay locked loop includes. DFE input buffer according to claim 26, characterized in that the sampling clock signal generator comprises the following components: - a timing control circuit ( 18 ) which generates the sampling clock signal (c0, c90, c180, c270), and - a clock signal generator ( 20 ), which receives a clock signal (CLK) and generates a plurality of internal clock signals (c1 to cn) and the timing control circuit ( 18 ). DFE input buffer according to one of claims 1 to 10, characterized in that the equalizer ( 10 ' ) comprises the following components: an equalizer coefficient control circuit ( 40 ) receiving the variable equalizing control signal (eqco) and generating in response an equalization coefficient (β), a multiplier which multiplies the oversampled output signal (OD, ED) by the equalizing coefficient (β) to obtain a product (βOD, βED) he and - a differential amplifier which subtracts the product (βOD, βED) from the input signal (IN) to produce the amplified output signal (ed, od). DFE input buffer according to one of claims 1 to 10, characterized in that the oversampled output signal comprises a straight over-sampled output signal (ED) and an odd oversampled output signal (OD) and the equalizer unit ( 10 ' ) comprises the following components: an equalizer coefficient control circuit ( 40 ) which receives the variable equalization control signal (eqco) and generates in response thereto an equalizing coefficient (β), - a first multiplier ( 42 ) which multiplies the odd oversampled output signal (OD) by the equalizer coefficient (β) to produce an odd product (βOD), - a second multiplier ( 46 ) which multiplies the just oversampled output signal (ED) by the equalizer coefficient (β) to produce a straight product (βED), - a first differential amplifier ( 44 ) which subtracts the odd product (βOD) from the input signal (IN) to produce the currently amplified output signal (ed), and - a second differential amplifier ( 48 ) which subtracts the even product (βED) from the input signal (IN) to produce the odd amplified output signal (od). Memory device with - a plurality of addressable Memory cells, each having a data storage element, and - one Decoder which receives an address from an external source and generates a line signal and a column signal to at least on to access one of the addressable memory cells, marked by - one DFE input buffer according to one of claims 1 to 30. Memory device according to claim 31, characterized in that the equalizer ( 10 ) a first and a second equalizer circuit ( 10 ' . 10 '' ), wherein the amplified output signal comprises a straight amplified output signal (ed, edB) which is output from the first equalizing circuit ( 10 ' ) and an odd amplified output signal (od, odB), which is supplied by the second equalizer circuit ( 10 '' ) can be output in parallel with the even amplified output signal (ed, edB). Memory system with - a memory control circuit ( 100 ), which generates command and address signals (COM, BA, ADD), and - a memory module ( 300 ) with a plurality of memory components ( 300-1 to 300-n ) which receives the command and address signals (COM, BA, ADD) and, in response, data (Din / Dout) in the memory devices (FIG. 300-1 to 300-n ) and from the memory devices ( 300-1 to 300-n ), the memory components ( 300-1 to 300-n ) each comprise a plurality of addressable memory cells, each comprising a data storage element, and a decoder receiving an address from an external source and generating a row signal and a column signal to access at least one of the addressable memory cells, characterized in that - at least one of the memory devices ( 300-1 to 300-n ) is one according to claim 31 or 32. Equalizer, which amplifies a voltage level difference between an input signal (IN) and an oversampled signal (ED, OD), characterized in that the equalizer ( 10 ' ) generates an amplified output signal (ed, edB, od, odB) in response to a variable equalizing control signal (eqco), comprising: a first current path between a first voltage source (VDD) and a second voltage source, the first current path being a first Load (P1), a first transistor (N1) activatable in response to a first input signal (IN), and a second transistor (N5) having a first channel width and activatable in response to a bias voltage (Vb) wherein the first current path draws a first current (I1), - a second current path between the first voltage source (VDD) and the second voltage source, the second current path a second load (P2), a third transistor (N4) which in response to a second input signal (OD), and comprising a transistor bank having a plurality of parallel-connected fourth transistors (N7-1 to N7-n), each of the fourth Transistors (N7-1 to N7-n) in response to a bit of the Entzerrsteuersignals (eqco) is activated, whereby selectively an effective second channel width of the transistor bank is modifiable, so that the second current path pulls a second current (I2), which in response to the variable equalizing control signal (eqco), such that an output signal (de) provided at an intersection of the first load (P1) and the first transistor (N1) outputs a variably amplified output signal (de) in response to the variable second current (I2) ). Entzerreinheit according to claim 35, characterized in that the first and second loads (P1, P2) are designed as load transistors. Entzerreinheit according to claim 34, characterized in that the first and second loads (P1, P2) are designed as load resistors. Entzerreinheit according to any one of claims 34 to 36, characterized in that the first load (P1) and the first Transistor (N1) are coupled to a first output node and the second load (P2) and the second transistor (N5) at a second output node are coupled, wherein a fifth transistor (N2) between the second node and a connection of the first Transistors (N1) and the second transistor (N5) looped which is in response to an inverted first input signal (INB) is activatable, and wherein a sixth transistor (N3) between the first node and a connection of the third transistor (N4) and the transistor bank is looped in response to an inverted second input signal (ODB) can be activated. Entzerreinheit according to any one of claims 34 to 37, characterized in that the transistor bank a plurality of seventh transistors (N6-1 to N6-n), each of the seventh transistors (N6-1 to N6-n) in series with a corresponding one fourth transistor (N7-1 to N7-n) is connected, each of the seventh transistors (N6-1 to N6-n) in response to the bias voltage (Vb) is activatable. Method for equalizing an input signal, which is received at an input buffer, marked by the steps: - Reinforcing one Voltage level difference between the input signal (IN) and an oversampled Signal (ED, OD) in response to a variable equalization control signal (eqco) and generating a boosted Output signal (ed, edB, od, odB), - Sampling of the amplified output signal (ed, edB, od, odB) in response to a sampling clock signal (c0, c90, c180), around the oversampled To generate signal (ED, OD), - generating a timing control signal (up, dn, lock) for timing the activation of the sampling clock signals (c0, c90, c180, c270) in response to a phase of the oversampled Signal (ED, OD), and - Modify the variable equalization control signal (eqco) in response to the timing signal (up, dn, lock). Method according to claim 39, characterized that - the increased Output signal a straight amplified Output signal (ed, edB) and an odd amplified output signal (od, odB) includes, wherein the oversampled Signal a first straight over-sampled Signal (ED), a second even oversampled signal (ED90), a first odd over-sampled one Signal (OD90) and a second odd oversampled signal (OD) includes, - in which generating the timing control signal (up, dn, lock) a determination includes whether a phase shift between the first even oversampled Signal (ED) and the second even oversampled signal (ED90) exists and whether a phase shift between the first odd oversampled Signal (OD90) and the second odd oversampled signal (OD) exists, in response to this, the timing control signal (up, dn, lock) which generates a lock control signal (lock), an up control signal (up) and a down control signal (dn), wherein the lock control signal (lock) is active, if no phase shift between the first and the second straight over-sampled Signal (ED, ED90) exists and if there is no phase shift between the first and second odd oversampled signals (OD90, OD), the down control signal (dn) is active when a phase shift between the first and the second straight over-sampled Signal (ED, ED90) exists and the up control signal (up) is activated is when a phase shift between the first and the second odd over-sampled Signal (OD90, OD) exists. Method according to claim 39 or 40, characterized in that the variable equalization control signal (eqco) in response to the conditions the up-control signal (up) and the down control signal (dn) and the lock control signal (lock) is modified. Method according to one of Claims 39 to 41, characterized that the modification of the equalization control signal (eqco) is the following Steps includes: - receive the up-control signal (up), the down control signal (dn) and the lock control signal (lock) and in response thereto Generating an additional up control signal (uup) and an additional down control signal (ddn), wherein the additional upstream control signal (uup) is activated when the up-control signal (up) and / or the down control signal (dn) are activated, and wherein the additional down control signal (ddn) is activated is when the lock control signal (lock) is activated, and - Produce the variable equalizing control signal (eqco) in response to the additional up control signal (uup) and the additional down control signal (ddn) by increasing the value of the variable equalization control signal (eqco) when the additional up control signal (uup) is active, and by decreasing the value of the variable Equalization control signal (eqco) when the additional down control signal (ddn) is active is.