WO2024087540A1

WO2024087540A1 - Data receiving circuit and semiconductor device

Info

Publication number: WO2024087540A1
Application number: PCT/CN2023/089142
Authority: WO
Inventors: 李思曼; 严允柱
Original assignee: 长鑫存储技术有限公司
Priority date: 2022-10-27
Filing date: 2023-04-19
Publication date: 2024-05-02
Also published as: CN117997683A

Abstract

Provided in the embodiments of the present disclosure are a data receiving circuit and a semiconductor device. The data receiving circuit comprises a plurality of data paths. The ith data path comprises an amplification circuit which is configured to amplify the voltage difference between the voltage of input data and the reference voltage and output a first signal pair; a sampling circuit which is configured to receive a corresponding sampling clock so as to sample the first signal pair and output a second signal pair; a first encoding circuit which is configured to receive second signal pairs output by the N data paths, perform encoding processing on all the received second signal pairs, and output a first control signal, wherein N ≤ M; and a first adjustment circuit which is configured to receive the first control signal, and, in response to the first control signal, adjust the first signal pair in the ith data path. The embodiments of the present disclosure can reduce power consumption and improve the transmission speed of input data while performing decision feedback equalization on the previously-transmitted multi-bit input data.

Description

Data receiving circuit and semiconductor device

cross reference

The present disclosure claims priority to the Chinese patent application entitled “DATA RECEIVING CIRCUIT AND SEMICONDUCTOR DEVICE” filed on October 27, 2022 and application number 202211328242.4, which is incorporated herein by reference in its entirety.

Technical Field

The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a data receiving circuit and a semiconductor device.

Background technique

In memory applications, as the signal transmission rate becomes faster and the clock frequency increases, the input data channel loss has an increasingly greater impact on the signal quality, which can easily lead to inter-symbol interference (ISI). ISI refers to the phenomenon that the previously transmitted input data affects the transmission of the currently transmitted input data due to the bandwidth limitation of the input data channel. At present, equalization circuits are usually used to compensate for the input data channel in order to reduce the adverse effects of inter-symbol interference. The equalization circuit can choose CTLE (Continuous Time Linear Equalizer) or DFE (Decision Feedback Equalizer).

However, the equalization circuit currently used is relatively complex and affects the input data transmission speed.

Summary of the invention

According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a data receiving circuit, comprising: multiple data paths, each of which receives input data and a sampling clock, and the phase of the sampling clock received by each data path is different, and the multiple data paths include: the 1st data path to the Mth data path numbered in ascending order of natural numbers, the i-th data path is any data path among the multiple data paths, 1≤i≤M, M≥2, and the phase difference between the sampling clocks received by any two consecutively numbered data paths from the 1st data path to the Mth data path is the same; wherein the i-th data path includes: an amplification circuit configured to amplify the voltage difference between the input data voltage and the reference voltage and output a first signal pair; a sampling circuit configured to receive a corresponding sampling clock, sample the first signal pair and output a second signal pair; a first encoding circuit configured to receive the second signal pairs output by N data paths, encode all the received second signal pairs, and output a first control signal, N≤M; a first adjustment circuit configured to receive the first control signal and adjust the first signal pair in the i-th data path in response to the first control signal.

For example, the first encoding circuit of the i-th data path receives the second signal pair output by at least two data paths except the i-1-th data path, and the first encoding circuit of the 1st data path receives the second signal pair output by at least two data paths except the M-th data path; wherein 1＜i≤M, M≥3.

For example, the first encoding circuit of the i-1th data path receives the second signal pair output by the i-1th data path and the second signal pair output by the i-th data path; the first encoding circuit of the Mth data path receives the second signal pair output by the 1st data path and the second signal pair output by the Mth data path.

For example, the first encoding circuit of the Mth data path receives the second signal pair output by the 1st data path and the second signal pair output by the 2nd data path; the first encoding circuit of the i-1th data path receives the second signal pair output by the i-th data path and the second signal pair output by the i+1th data path, i+1＜M; the first encoding circuit of the M-1th data path receives the second signal pair output by the 1st data path and the second signal pair output by the Mth data path.

For example, when M is 4, the phase difference is 90°.

For example, the first encoding circuit of the i-th data path receives the second signal pair including the output of the i-th data path, and the first encoding circuit of the 1st data path receives the second signal pair including the output of the 1st data path; wherein 1＜i≤M, M≥3.

For example, N=M.

For example, the second signal pair includes a second data signal and a second complementary data signal, and the second data signal and the second complementary data signal are inverted signals of each other; the control signal includes a first sub-control signal and a second sub-control signal; the first encoding circuit includes: a first sub-encoding circuit, the first sub-encoding circuit is used to perform an OR operation on the received second data signal to obtain a first sub-control signal; a second sub-encoding circuit, the second sub-encoding circuit is used to perform an OR operation on the received second complementary data signal to obtain a second sub-control signal.

For example, the first signal pair includes a first data signal and a first reference data signal, the amplifier circuit includes a first node and a second node, the first node outputs the first data signal, and the second node outputs the first reference data signal; the first regulation circuit includes: a first control circuit connected between the first node and the ground terminal, turned on or off according to the second sub-control signal; a second control circuit connected to the second node and ground, and is turned on or off according to the first sub-control signal.

For example, the first control circuit includes: a first NMOS tube, the gate of the first NMOS tube receives the first sub-control signal, and the first NMOS tube is connected between the first node and the ground terminal; the second control circuit includes: a second NMOS tube, the gate of the second NMOS tube receives the second sub-control signal, and the second NMOS tube is connected between the second node and the ground terminal.

For example, the first adjustment circuit also includes: a first compensation circuit, connected between the first control circuit and the ground terminal and between the second control circuit and the ground terminal, and the first control circuit and the second control circuit are both connected between the first compensation circuit and the first node, and the first compensation circuit is configured to receive the first tap signal and adjust the first signal pair with a first adjustment value corresponding to the first tap signal.

For example, the first compensation circuit includes: a plurality of third NMOS tubes connected in parallel, the gate of each third NMOS tube receives one bit of data in the first tap signal, and each third NMOS tube is connected between the first control circuit and the ground terminal and between the second control circuit and the ground terminal.

For example, the first tap signal is obtained by adding the first tap sub-signal and the second tap sub-signal.

For example, the i-th data path also includes: a second adjustment circuit, configured to receive a second signal pair output by the i-1-th data path, and adjust the first signal pair in the i-th data path in response to the received second signal pair, wherein if the i-th data path is the 1st data path, the i-1-th data path is the Mth data path.

For example, the i-th data path also includes: a third adjustment circuit, configured to receive a second signal pair output by the i-2 data path, and adjust the first signal pair in the i-th data path in response to the received second signal pair, wherein if the i-th data path is the second data path, the i-2 data path is the M-th data path, and if the i-th data path is the first data path, the i-2 data path is the M-1 data path.

For example, M-N≥2; the i-th data path also includes: a second encoding circuit, configured to receive second signal pairs output by at least two data paths, encode all received second signal pairs, and output a second control signal; wherein the second encoding circuit and the first encoding circuit respectively receive second signal pairs output by different data paths; a fourth adjustment circuit, configured to receive the second control signal, and adjust the first signal pair in the i-th data path in response to the second control signal.

For example, the amplification circuit includes: a fourth NMOS tube, the gate of the fourth NMOS tube receives input data, the drain is connected to the working power supply through the first resistor, the drain of the fourth NMOS tube outputs a first data signal, and the source is coupled to the ground; a fifth NMOS tube, the gate of the fifth NMOS tube receives a reference voltage, the drain is connected to the working power supply through the second resistor, and the drain of the fifth NMOS tube outputs a first reference data signal, the source is coupled to the ground, and the first reference data signal and the first data signal constitute a first signal pair.

For example, the amplifier circuit also includes: a sixth NMOS tube, the gate of the sixth NMOS tube receives a bias signal, the drain is connected to the fourth NMOS tube conduction electrode and the source of the fifth NMOS tube, and the source of the sixth NMOS tube is connected to the ground.

According to some embodiments of the present disclosure, another aspect of the present disclosure provides a semiconductor device, including: a data receiving circuit provided by any of the above embodiments.

For example, the semiconductor device includes a memory chip.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a functional block diagram of a data receiving circuit including a 4-tap equalization circuit;

FIG2 is a schematic diagram corresponding to FIG1;

FIG3 is a schematic diagram of a circuit structure of the 4-tap equalization circuit in FIG1 ;

FIG4 is a functional block diagram of a data receiving circuit provided by an embodiment of the present disclosure;

FIG5 is a functional block diagram of the i-th data path in FIG4;

FIG6 is another functional block diagram of a data path in a data receiving circuit;

FIG7 is another functional block diagram of a data path in a data receiving circuit;

FIG8 is another functional block diagram of a data path in a data receiving circuit;

9 to 12 are several different functional block diagrams of the data receiving circuit;

FIG13 is a schematic diagram of a circuit structure of an amplifier circuit and a first regulating circuit in any data path;

FIG14 is a schematic diagram of a circuit structure of the first sub-compensation circuit or the second sub-compensation circuit in FIG13;

FIG15 is another schematic diagram of the circuit structure of the amplifier circuit and the first regulating circuit in any data path;

FIG16 is a schematic diagram of another structure of the amplifier circuit, the first control circuit, the second control circuit and the first compensation circuit in any data path;

FIG. 17 is a schematic diagram of a circuit structure of a sampling circuit.

Detailed ways

According to the number of bits of input data participating in DFE in the previously transmitted input data, the equalization circuit in the data receiving circuit can be divided into 1-tap, 2-tap, 3-tap and 4-tap equalization circuits. The equalization circuit can even have more (that is, the number of taps can be greater than 4) taps. Tap means taps. It can be understood that the equalization circuit can include multiple tap adjustment circuits, each tap adjustment circuit corresponds to a tap signal, a tap signal corresponds to a bit of data, and the currently transmitted input data is adjusted according to the tap signal. Among them, 1-tap means that the previously transmitted 1-bit data participates in DFE; 2-tap means that the previously transmitted 2-bit data participates in DFE; 3-tap means that the previously transmitted 3-bit data participates in DFE; 4-tap means that the previously transmitted 4-bit data participates in DFE.

Generally, each tap adjustment circuit in the equalization circuit needs to design a corresponding circuit. The more taps there are in the equalization circuit, the larger the circuit volume required for the corresponding equalization circuit, and the corresponding load of the equalization circuit will also be larger, which will affect the feedback speed of the DFE and the delay of the DFE will also increase. The following will take a 4-tap equalization circuit as an example for explanation. FIG1 is a functional block diagram of a data receiving circuit including a 4-tap equalization circuit, FIG2 is an architecture diagram corresponding to FIG1, and FIG3 is a circuit structure diagram of the 4-tap equalization circuit in FIG1.

Referring to FIG. 1 and FIG. 2, taking the data receiving circuit sampling and transmitting input data in sequence based on the sampling phases of the input data sampling clock DQS of 0°, 90°, 180°, and 270° as an example, the data receiving circuit includes 4 data paths, each of which has an amplifier circuit 11, an equalizer circuit 12, and a sampling circuit 13, wherein the amplifier circuit 11 and the equalizer circuit 12 can be integrated into the same module 10, and T1, T2, T3, and T4 respectively represent the tap signals of the tap adjustment circuit corresponding to the previous 1st bit data, 2nd bit data, 3rd bit data, and 4th bit data, wherein "previous" here refers to the currently transmitted input data as a reference. The amplifier circuit 11 receives the input data IN and the reference voltage VREF, and the 4 sampling circuits 13 output OUT_0, OUT_90, OUT_180, and OUT_270 respectively.

For the first data path, the sampling phase of the sampling clock DQS is 0°, T1, T2, T3 and T4 are OUT_270, OUT_180, OUT_90 and OUT_0[n-1] respectively, OUT_0[n-1] refers to the input data output by the sampling circuit 13 in the previous clock cycle in response to the sampling clock with a sampling phase of 0°, wherein the previous clock cycle is relative to the sampling moment corresponding to the input data currently transmitted by the first data path; for the second data path, the sampling phase is 90°, T1, T2, T3 and T4 are OUT_0, OUT_270, OUT_180 and OUT_90[n-1] respectively, OUT_90[n-1] refers to the sampling circuit 13 in response to the sampling clock with a sampling phase of 90° The sampling clock outputs the input data in the previous clock cycle; for the third data path, the sampling phase is 180°, T1, T2, T3 and T4 are OUT_90, OUT_0, OUT_270 and OUT_180[n-1] respectively, and OUT_180[n-1] refers to the input data output by the sampling circuit 13 in response to the sampling clock with a sampling phase of 180° in the previous clock cycle; for the fourth data path, the sampling phase is 270°, T1, T2, T3 and T4 are OUT_180, OUT_90, OUT_0 and OUT_270[n-1] respectively, and OUT_270[n-1] refers to the input data output by the sampling circuit 13 in response to the sampling clock with a sampling phase of 270° in the previous clock cycle.

Taking the equalization circuit of the fourth data path as an example, in combination with reference to FIG. 1 to FIG. 3, the amplifier circuit 11 has a first node N1 and a second node N2, and the equalization circuit 12 includes four tap adjustment circuits 14, each of which includes: a first NMOS tube and a second NMOS tube, the gates of which respectively receive one of the two differential signals in the input data output by the sampling circuit 13, and the drains are respectively connected to the first node N1 and the second node N2; a third NMOS tube group and a fourth NMOS tube group, the third NMOS tube group includes a plurality of third NMOS tubes connected in parallel, the fourth NMOS tube group includes a plurality of fourth NMOS tubes connected in parallel, the gates of the third NMOS tube and the fourth NMOS tube both receive one bit of data in the tap signal, the third NMOS tube group is connected between the first NMOS tube and the ground terminal, and the fourth NMOS tube group is connected between the second NMOS tube and the ground terminal. It can be understood that in some examples, the third NMOS tube group and the fourth NMOS tube group can also be the same NMOS tube group.

Among them, for the tap adjustment circuit corresponding to T1, the two differential signals are Tap1_data and Tap1_datab, the tap signal is Tap1_coeffi<5:0>, and accordingly, the tap signal Tap1_coeffi<5:0> controls the third NMOS tube group and the fourth NMOS tube group at the same time; for the tap adjustment circuit corresponding to T2, the two differential signals are Tap2_data and Tap2_datab, the tap signal is Tap2_coeffi<4:0>, and accordingly, the tap signal Tap2_coeffi<4:0> controls the third NMOS tube group and the fourth NMOS tube group at the same time; for the tap adjustment circuit corresponding to T3, the two differential signals are Tap3_data and Tap3_datab, and the tap signal is Tap3_coeffi<4:0>, accordingly, the tap signal Tap3_coeffi<4:0> controls the third NMOS tube group and the fourth NMOS tube group at the same time; for the tap adjustment circuit corresponding to T4, the two differential signals are Tap4_data and Tap4_datab, and the tap signal is Tap4_coeffi<3:0>, accordingly, the tap signal Tap4_coeffi<3:0> controls the third NMOS tube group and the fourth NMOS tube group at the same time.

From the above analysis, it can be seen that for any data path, the number of tap adjustment circuits required is the same as the number of bits of input data participating in DFE. The more bits of input data participating in DFE, the larger the number of corresponding tap adjustment circuits, and the larger the area size of the data receiving circuit occupied by the corresponding tap adjustment circuit, which will affect the transmission speed of input data, and the speed of DFE feedback will be slower, that is, the delay of DFE will also increase. In addition, the total amount of the third NMOS tube group and the fourth NMOS tube group in the corresponding tap adjustment circuit will also increase, making the load of the data receiving circuit larger, which will also affect the transmission speed of the input data of the data receiving circuit.

The disclosed embodiment provides a data receiving circuit, which encodes multiple bits of previously transmitted input data to obtain a first control signal, and a first adjustment circuit performs decision feedback equalization on the currently transmitted input data in response to the first control signal to reduce the influence of inter-symbol interference and save the complexity of the circuit required to implement DFE, thereby reducing the circuit area, reducing the circuit load, and further reducing the power consumption of the data receiving circuit, and improving the input data transmission speed.

FIG. 4 is a functional block diagram of a data receiving circuit provided in an embodiment of the present disclosure, and FIG. 5 is a functional block diagram of an i-th data path in FIG. 4 .

4 and 5, in the embodiment of the present disclosure, the data receiving circuit includes: a plurality of data paths 100, the plurality of data paths 100 all receive input data IN and a sampling clock CLK, and the phase of the sampling clock CLK received by each data path 100 is different, the plurality of data paths 100 include: a first data path to an Mth data path numbered in ascending order of natural numbers, the i-th data path is any data path 100 among the plurality of data paths 100, 1≤i≤M, M≥2, and the phase difference between the sampling clocks CLK received by any two consecutively numbered data paths 100 among the first data path to the Mth data path is the same; wherein the i-th data path includes: an amplifier circuit 101, The first circuit 101 is configured to amplify the voltage difference between the voltage of the input data IN and the reference voltage VREF and output the first signal pair OUT1; the sampling circuit 102 is configured to receive the corresponding sampling clock CLK, sample the first signal pair OUT1 and output the second signal pair OUT2; the first encoding circuit 103 is configured to receive the second signal pairs OUT2 output by N data paths, encode all the received second signal pairs OUT2, and output the first control signal TapA, N≤M; the first adjustment circuit 104 is configured to receive the first control signal TapA, and adjust the first signal pair OUT1 in the i-th data path in response to the first control signal TapA.

In the above data receiving circuit, for any data path 100, the second signal pair OUT2 output by the N data paths 100 is the previously transmitted input data, and the previously transmitted N input data can participate in the adjustment of the first signal pair OUT1 transmitted by the data path 100 to reduce the interference of the previously transmitted input data on the data path of the currently transmitted input data, thereby realizing the DFE function. In addition, the first encoding circuit 103 encodes the second signal pair OUT2 output by the N data paths 100 to obtain the first control signal TapA, so that the influence of the previously transmitted N input data on the currently transmitted input data is converted into the influence of the first control signal TapA on the currently transmitted input data; accordingly, the first adjustment circuit 104 responds to the first control signal TapA to adjust the first signal pair OUT1 in the data path of the currently transmitted input data, thereby reducing the inter-symbol interference of the previously transmitted N input data on the data path of the currently transmitted input data, thereby improving the accuracy of input data transmission. The first adjustment circuit 104 can make adjustments in response to a plurality of previously transmitted input data, so there is no need to design an independent adjustment circuit for each previously transmitted input data that needs to participate in the DFE function, which is beneficial to reducing the complexity of the circuit required for the input data transmission path to implement the DFE function and reducing the volume of the circuit, thereby facilitating reducing the load of the first adjustment circuit 104, improving the adjustment speed of the first signal pair OUT1 and reducing the delay of adjusting the first signal pair OUT1, thereby ensuring that the previously transmitted multi-bit input data all participate in the DFE to improve the accuracy of the input data transmission, while reducing the load of the data receiving circuit and improving the input data transmission speed.

The data receiving circuit provided by the embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

The data receiving circuit can be applied to a memory, and the memory can be a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). In some embodiments, the data receiving circuit can be applied to an SDRAM (Synchronous Dynamic Random Access Memory), and the SDRAM can be a DDR (Double Data Rate) SDRAM, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

Referring to FIG. 5 , in some embodiments, the second signal pair OUT2 includes a second data signal OUT2_O and a second complementary data signal OUT2_E, and the second data signal OUT2_O and the second complementary data signal OUT2_E are inverted signals, wherein the level of the second data signal OUT2_O is used to reflect the level of the input data IN, that is, if the input data is 0, the second data signal OUT2_O is 0, and if the input data is 1, the second data signal OUT2_O is 1. Correspondingly, the first control signal TapA includes a first sub-control signal TapA1 and a second sub-control signal TapA2, wherein the first sub-control signal TapA1 is obtained based on encoding processing of all received second data signals OUT2_O, and the second sub-control signal TapA2 is obtained based on encoding processing of all received second complementary data signals OUT2_E. It can be understood that the two "encoding processes" here need to use the same encoding method. Mode.

Referring to FIG5 , the first encoding circuit 103 may be configured to perform an OR operation on all received second signal pairs OUT2, that is, the encoding process performed by the first encoding circuit 103 is an OR operation to obtain a first control signal TapA. The first encoding circuit 103 may include a first sub-encoding circuit 113 and a second sub-encoding circuit 123, the first sub-encoding circuit 113 is used to perform an OR operation on all received second data signals OUT2_O to obtain a first sub-control signal TapA1, and the second sub-encoding circuit 123 is used to perform an OR operation on all received second complementary data signals OUT2_E to obtain a second sub-control signal TapA2. The first encoding circuit 103 may be implemented using an OR gate circuit.

It can be understood that if all the received second data signals OUT2_O are 0, the first sub-control signal TapA1 is also correspondingly 0; if at least one of all the received second data signals OUT2_O is 1, the first sub-control signal TapA1 is also correspondingly 1. If all the received second complementary data signals OUT2_E are 0, the second sub-control signal is also correspondingly 0; if at least one of all the received second complementary data signals OUT2_E is 1, the second sub-control signal TapA2 is also correspondingly 1.

In some examples, the first signal pair OUT1 may include a first data signal OUT1_O and a first reference data signal OUT1_E, and accordingly, the amplifier circuit 101 includes a first node net1 and a second node net2, the first node net1 outputs the first data signal OUT1_O, and the second node net2 outputs the first reference data signal OUT1_E. If the input data is 1, the voltage of the input data IN is greater than the reference voltage VREF, the voltage of the first data signal OUT1_O is less than the voltage of the first reference data signal OUT1_E, and the corresponding voltage of the second data signal OUT2_O is greater than the voltage of the second complementary data signal OUT2_E; if the input data IN is 0, the voltage of the input data IN is less than the reference voltage, the voltage of the first data signal OUT1_O is greater than the voltage of the first reference data signal OUT1_E, and the corresponding voltage of the second data signal OUT2_O is less than the voltage of the second complementary data signal OUT2_E. Among them, the first regulation circuit 104 adjusts the voltage of the second node net2 in response to the first sub-control signal TapA1, that is, the first regulation circuit 104 adjusts the first reference data signal OUT1_E in response to the first sub-control signal TapA1; the first regulation circuit 104 adjusts the voltage of the first node net1 in response to the second sub-control signal TapA2, that is, the first regulation circuit 104 adjusts the first data signal OUT1_O in response to the second sub-control signal TapA2.

It can be understood that the amplifier circuit 101 can be configured to discharge between the first node net1 and the ground terminal in response to the input data IN, that is, the voltage of the first node net1 (the voltage of the first data signal OUT1_O) is pulled down, and the larger the voltage of the input data IN, the faster the first node net1 is pulled down, that is, the faster the discharge speed between the first node net1 and the ground terminal; it is also configured to discharge between the second node net2 and the ground terminal in response to the reference voltage VREF, that is, the voltage of the second node net2 (the voltage of the first reference data signal OUT1_E) is pulled down, wherein the reference voltage VREF can be a fixed value, and accordingly, under the premise that the first regulation circuit does not adjust the second node net2, the reference voltage VREF has no effect on the discharge speed between the second node net2 and the ground terminal.

The principle of the first regulating circuit 104 regulating the first signal pair OUT1 is described below:

Specifically, if all received second data signals OUT2_O are 0, then all corresponding received second complementary data signals OUT2_E are 1, the first sub-control signal TapA1 is 0, the second sub-control signal TapA2 is 1, and the first regulating circuit 104 can be a high-level signal valid, then the first regulating circuit 104 adjusts the voltage of the first node net1 in response to the second sub-control signal TapA2. Under this premise, there are the following two situations:

If the input data IN received by the i-th data path is 0, all the second data signals OUT2_O received by the first encoding circuit 103 are the same as the currently transmitted input data, and although no inter-code interference will be caused, in this case, the first adjustment circuit 104 will still adjust the voltage of the first node net1 in response to the second sub-control signal TapA2 to lower the level of the first data signal OUT1_O of the first node net1. Alternatively, if the input data IN received by the i-th data path is 1, that is, the currently transmitted input data is different from all the second data signals OUT2_O received by the first encoding circuit 103, and decision feedback equalization adjustment is required at this time, the first adjustment circuit 104 adjusts the voltage of the first node net1 in response to the second sub-control signal TapA2, so that the level of the first data signal OUT1_O becomes lower, that is, the speed at which the voltage of the first node net1 is lowered becomes faster, thereby further widening the level difference between the first data signal OUT1_O and the first reference data signal OUT1_E, so that the input data "1" is transmitted more accurately.

If all received second data signals OUT2_O are 1, then all corresponding received second complementary data signals OUT2_E are 0, the first sub-control signal TapA1 is 1, the second sub-control signal TapA2 is 0, and the first regulating circuit 104 can be a high-level signal valid, then the first regulating circuit 104 adjusts the voltage of the second node net2 in response to the first sub-control signal TapA1. Under this premise, there are the following two situations:

The input data IN received by the i-th data path is 0, that is, the currently transmitted input data is different from all the second data signals OUT2_O received by the first encoding circuit 103. At this time, decision feedback equalization adjustment is required. The first adjustment circuit 104 adjusts the voltage of the second node net2 in response to the first sub-control signal TapA1, so that the level of the first reference data signal OUT1_E becomes lower, that is, the speed at which the voltage of the second node net2 is pulled down becomes faster, thereby further widening the level difference between the first data signal OUT1_O and the first reference data signal OUT1_E, so that the input data "0" is transmitted more accurately. Alternatively, the input data IN received by the i-th data path is 1, that is, the currently transmitted input data is the same as all the second data signals OUT2_O received by the first encoding circuit 103. Then, all the second data signals OUT2_O received by the first encoding circuit 103 will not cause inter-symbol interference. In this case, the first regulating circuit 104 will still pull down the voltage of the second node net2 in response to the first sub-control signal TapA1.

If there is at least one 1 and at least one 0 in all the received second data signals OUT2_O, then there is at least one 1 and at least one 0 in all the corresponding received second complementary data signals OUT2_E, the first sub-control signal TapA1 is 1, the second sub-control signal TapA2 is 1, and the first regulating circuit 104 can be high level effective, then the first regulating circuit 104 adjusts the voltage of the second node net2 in response to the first sub-control signal TapA1, and the first regulating circuit 104 adjusts the voltage of the first node net1 in response to the second sub-control signal TapA2. Under this premise, there are the following two situations:

The input data IN received by the i-th data path is 0, that is, the currently transmitted input data is different from at least one signal of all the second data signals OUT2_O received by the first encoding circuit 103. The first regulating circuit 104 adjusts the voltage of the second node net2 in response to the first sub-control signal TapA1, so that the speed at which the voltage of the second node net2 is pulled down becomes faster, and the first regulating circuit 104 adjusts the voltage of the first node net1 in response to the second sub-control signal TapA2, so that the speed at which the voltage of the first node net1 is pulled down also becomes faster; control can be performed by adding a first compensation circuit that works in response to the first tap signal, and the speed difference is increased under the premise of ensuring that the speed at which the first node net1 is pulled down is less than the speed at which the second node net2 is pulled down, so that while ensuring that the level of the first data signal OUT1_O is greater than the level of the first reference data signal OUT1_E, the voltage difference between the first data signal OUT1_O and the first reference data signal OUT1_E is widened, so that the input data "0" is transmitted more accurately.

Alternatively, the input data IN received by the i-th data path is 1, that is, the currently transmitted input data is different from at least one of all the second data signals OUT2_O received by the first encoding circuit 103, and the first regulating circuit 104 adjusts the voltage of the second node net2 in response to the first sub-control signal TapA1, so that the speed at which the voltage of the second node net2 is pulled down becomes faster, and the first regulating circuit 104 adjusts the voltage of the first node net1 in response to the second sub-control signal TapA2, so that the speed at which the voltage of the first node net1 is pulled down also becomes faster; control can be performed by increasing the first tap signal, and the speed difference is increased while ensuring that the speed at which the first node net1 is pulled down is greater than the speed at which the second node net2 is pulled down, so that while ensuring that the level of the first data signal OUT1_O is less than the level of the first reference data signal OUT1_E, the voltage difference between the first data signal OUT1_O and the first reference data signal OUT1_E is widened, so that the input data "1" is transmitted more accurately.

It can be understood that if the first sub-control signal TapA1 and the second sub-control signal TapA2 are both 1, the speed at which the voltage of the first node net1 and the voltage of the second node net2 are pulled down becomes faster, which is beneficial to improving the speed of input data transmission, that is, reducing the time required for the sampling circuit to output the second signal pair OUT2.

The above-mentioned "0" means that the level of the corresponding signal is a low level, which is defined as logic "0", and "1" means that the level of the corresponding signal is a high level, which is defined as logic "1". In addition, "low level" and "high level" are level values relative to a reference level, a level higher than the reference level is a high level, and a level lower than the reference level is a low level.

Based on the above analysis, it can be known that at least one of the first sub-control signal TapA1 and the second sub-control signal TapA2 is 1. When the first sub-control signal TapA1 is 1, the first regulation circuit 104 will pull down the level of the second node net2 to make the first data signal OUT1_O further greater than the first reference data signal OUT1_E. When the second sub-control signal TapA2 is 1, the first regulation circuit 104 will pull down the level of the first node net1 to make the first data signal OUT1_O further less than the first reference data signal OUT1_E. In other words, the first regulation circuit 104 will pull down the level of the first node net1 and/or pull down the level of the second node net2. Among them, when the input data IN received by the i-th data path is 1, the first regulating circuit 104 of the i-th data path further pulls down the level of the first node net1, so that the first data signal OUT1_O is further less than the first reference data signal OUT1_E, which is beneficial to further increase the accuracy of the input data IN transmitted by the i-th data path; when the input data IN received by the i-th data path is 0, the first regulating circuit 104 will pull down the level of the second node net2, so that the first data signal OUT1_O is further greater than the first reference data signal OUT1_E, which is beneficial to further increase the accuracy of the input data IN transmitted by the i-th data path. In some embodiments, the data receiving circuit can be a two-terminal transmission circuit, that is, the second signal pair OUT2 output by the data receiving circuit includes a second data signal OUT2_O and a second complementary data signal OUT2_E that are inverted from each other. It can be understood that, in some other embodiments, the data receiving circuit can also be a single-ended transmission circuit, and accordingly, the second signal pair can also include a second data signal and a second complementary data signal, wherein the second data signal is the signal actually output by the sampling circuit, and the second complementary data signal is a signal obtained after inverting the output second data signal. Accordingly, the i-th data path can also include: an inverting circuit for generating a second complementary data signal based on the second data signal.

The data receiving circuit includes M data paths, where M is greater than or equal to 2. For example, it may include 2 data paths corresponding to 2 sampling clocks with different phases, may include 3 data paths corresponding to 3 sampling clocks with different phases, may include 4 data paths corresponding to 4 sampling clocks with different phases, and may include 6 or 8 data paths corresponding to 6 or 8 sampling clocks with different phases.

In some embodiments, the first encoding circuit 103 of the i-th data path 100 can receive the second signal pair OUT2 output by at least two data paths 100 except the i-1-th data path 100, and the first encoding circuit 103 of the 1st data path 100 can receive the second signal pair OUT2 output by at least two data paths 100 except the M-th data path 100; wherein 1＜i≤M, M≥3. Since the second signal pair OUT2 output by the i-1th data path 100 is the input data signal that is closest in time to the currently transmitted input data, the second signal pair OUT2 output by the i-1th data path 100 causes the most serious inter-code interference to the input data IN to be transmitted by the i-th data path 100. Therefore, an independent second adjustment circuit can be designed for the second signal pair OUT2 output by the i-1th data path 100, so that the second adjustment circuit responds to the second signal pair OUT2 output by the i-1th data path 100 to adjust the first signal pair OUT1 of the i-th data path 100, which is beneficial to further improve the effect of eliminating inter-code interference.

In a specific example, M=3, the first encoding circuit 103 of the second data path 100 can receive the second signal pair OUT2 outputted by the second data path 100 and the third data path 100, respectively, and the first encoding circuit 103 of the third data path 100 can receive the second signal pair OUT2 outputted by the first data path 100 and the third data path 100, respectively. It can be understood that the first encoding circuit 103 of the third data path 100 can receive the second signal pair OUT2 outputted by the first data path 100 and the third data path 100, respectively, and the third data path 100 receives the input data signal at the current moment, and the first encoding circuit 103 receives the second signal pair OUT2 outputted by the third data path 100 in the previous clock cycle. For example, the third data path 100 receives the input data IN to be sampled and outputted at the sampling phase of the second clock cycle, and the first encoding circuit 103 of the third data path 100 receives the second signal pair OUT2 sampled and outputted at the sampling phase of the first clock cycle. It should be noted that the subsequent similar descriptions can refer to the descriptions here, and will not be repeated.

In some examples, M≥4, the first encoding circuit 103 of the i-th data path 100 receives the second signal pair OUT2 output by all data paths 100 except the i-1-th data path 100, and the first encoding circuit 103 of the first data path 100 receives the second signal pair OUT2 output by all data paths 100 except the M-th data path 100. That is, except for the second signal pair OUT2 output by the i-1-th data path 100, the second signal pairs OUT2 output by all other data paths 100 are used to generate the first control signal TapA corresponding to the i-th data path 100; except for the second signal pair OUT2 output by the M-th data path 100, the second signal pairs OUT2 output by all other data paths 100 are used to generate the first control signal TapA corresponding to the first data path 100. In a specific example, M=4, the first encoding circuit 103 of the second data path 100 can receive three second signals outputted by the second data path 100, the third data path 100 and the fourth data path 100 respectively; the first encoding circuit 103 of the third data path 100 can receive the second signal pair OUT2 outputted by the first data path 100, the third data path 100 and the fourth data path 100 respectively; the first encoding circuit 103 of the fourth data path 100 can receive the second signal pair OUT2 outputted by the first data path 100, the second data path 100 and the fourth data path 100 respectively.

In other examples, the first encoding circuit 103 of the i-1th data path 100 receives the second signal pair OUT2 output by the i-1th data path 100 and the second signal pair OUT2 output by the i-th data path 100; the first encoding circuit 103 of the Mth data path 100 receives the second signal pair OUT2 output by the 1st data path 100 and the second signal pair OUT2 output by the Mth data path 100. The benefits of such a setting include: for the i-1th data path 100, compared with the remaining data paths 100, the second signal pair OUT2 output by the i-1th data path 100 and the i-th data path 100 causes less inter-code interference to the i-1th data path 100, and therefore two second signal pairs OUT2 with smaller inter-code interference are selected for encoding processing to obtain the first control signal TapA, which is beneficial to further ensure that the ability to improve inter-code interference is further improved while reducing the complexity of the equalization circuit. For the i-1th data path 100, an independent adjustment circuit can be designed for the second signal pair OUT2 output by the remaining data paths 100 other than the i-1th data path 100 and the i-th data path 100, and the adjustment circuit adjusts the first signal pair OUT1 of the i-1th data path 100 in response to the received second signal pair OUT2.

For example, M=4, and the first encoding circuit 103 of the second data path 100 can receive the second signal pair OUT2 outputted from the second data path 100 and the third data path 100 , respectively. The benefits of such a setting include: compared with the fourth data path 100, the second signal pair OUT2 output by the second data path 100 and the third data path 100 causes less inter-code interference to the second data path 100, so two second signal pairs OUT2 with less inter-code interference are selected for encoding processing to obtain the first control signal TapA, which is beneficial to further ensure that the ability to improve inter-code interference is further improved while reducing the complexity of the equalization circuit. For the second data path 100, an independent second adjustment circuit can be designed for the second signal pair OUT2 output by the first data path 100, and an independent third adjustment circuit can be designed for the second signal pair OUT2 output by the fourth data path 100. The second adjustment circuit adjusts the first signal pair OUT1 of the second data path 100 in response to the second signal pair OUT2 output by the first data path 100, and the third adjustment circuit adjusts the first signal pair OUT1 of the second data path 100 in response to the second signal pair OUT2 output by the fourth data path 100. It can be understood that the first encoding circuit 103 of the second data path 100 can receive any two second signal pairs OUT2 of the three second signal pairs OUT2 respectively output by the second data path 100, the third data path 100 and the fourth data path 100. For example, the first encoding circuit 103 of the second data path 100 can also receive the second signal pair OUT2 respectively output by the second data path 100 and the fourth data path 100, or receive the second signal pair OUT2 respectively output by the third data path 100 and the fourth data path 100, or receive the second signal pair OUT2 respectively output by the second data path 100 and the third data path 100.

M=4, the first encoding circuit 103 of the third data path 100 can receive any two second signal pairs OUT2 of the three second signal pairs OUT2 respectively output by the first data path 100, the third data path 100 and the fourth data path 100, for example, it can receive the second signal pair OUT2 respectively output by the third data path 100 and the fourth data path 100; the first encoding circuit 103 of the fourth data path 100 can receive any two second signal pairs OUT2 of the three second signal pairs OUT2 respectively output by the first data path 100, the third data path 100 and the fourth data path 100; The coding circuit 103 can receive any two second signal pairs OUT2 of the second signal pairs OUT2 respectively output by the first data path 100, the second data path 100 and the fourth data path 100, for example, the second signal pairs OUT2 respectively output by the first data path 100 and the fourth data path 100 can be received; the first coding circuit 103 of the first data path 100 can receive any two second signal pairs OUT2 of the three second signal pairs OUT2 respectively output by the first data path 100, the second data path 100 and the third data path 100, for example, the second signal pairs OUT2 respectively output by the first data path 100 and the second data path 100 can be received. For the effect of such a setting, please refer to the corresponding description in the previous paragraph, which will not be repeated here.

It can be understood that, in the above examples, for any data path 100, the 4-bit data previously transmitted can all participate in the decision feedback equalization of the currently transmitted input data, that is, the data receiving circuit has a 4-tap equalization circuit. In other examples, for any data path 100, it can also be set that the 3-bit data previously transmitted participate in the decision feedback equalization of the currently transmitted input data, that is, the data receiving circuit has a 3-tap equalization circuit, and accordingly, the first encoding circuit 103 of the i-th data path 100 can receive the second signal pair OUT2 output by the two data paths 100 other than the i-1-th data path 100 and the i-th data path 100, and the first encoding circuit 103 of the 1st data path 100 can receive the second signal pair OUT2 output by the two data paths 100 other than the 1st data path 100 and the M-th data path 100.

In some embodiments, the first encoding circuit 103 of the Mth data path 100 may receive the second signal pair OUT2 output by the second data path 100 and the second signal pair OUT2 output by the third data path 100; the first encoding circuit 103 of the i-1th data path 100 receives the second signal pair OUT2 output by the i-th data path 100 and the second signal pair OUT2 output by the i+1th data path 100, i+1＜M; the first encoding circuit 103 of the M-1th data path 100 receives the second signal pair OUT2 output by the first data path 100 and the second signal pair OUT2 output by the Mth data path 100. Among them, the sampling clock CLK can still have 4 different phases, that is, M can be 4.

With respect to the solution in which the data receiving circuit has a 3-tap equalization circuit and has four data paths 100, in a specific example, the first encoding circuit 103 of the first data path 100 can receive the second signal pair OUT2 outputted from the second data path 100 and the third data path 100 respectively, and the first data path 100 can further include a second adjustment circuit, and the second adjustment circuit can receive the second signal pair OUT2 outputted from the fourth data path 100 to adjust the first signal pair OUT1 outputted from the first data path 100; the first encoding circuit 103 of the second data path 100 receives the second signal pair OUT2 outputted from the third data path 100 and the fourth data path 100 respectively, and the second data path 100 can further include a second adjustment circuit, and the second adjustment circuit receives the second signal pair OUT2 outputted from the first data path 100 to adjust the first signal pair OUT1 outputted from the second data path 100. The first encoding circuit 103 of the third data path 100 can receive the second signal pair OUT2 output by the first data path 100 and the fourth data path 100 respectively, and the third data path 100 can also include a second adjustment circuit, the second adjustment circuit receives the second signal pair OUT2 output by the second data path 100 to adjust the first signal pair OUT1 output by the first data path 100; the first encoding circuit 103 of the fourth data path 100 receives the second signal pair OUT2 output by the second data path 100 and the third data path 100 respectively; the fourth data path 100 can also include a second adjustment circuit, the second adjustment circuit receives the second signal pair OUT2 output by the third data path 100 to adjust the first signal pair OUT1 output by the fourth data path 100.

It can be understood that in some embodiments, N can also be equal to M, that is, the first encoding circuit 103 of the i-th data path 100 can receive the second signal pair OUT2 output by all data paths 100 to obtain the first control signal TapA. In this way, without considering the high anti-inter-symbol interference capability, the equalization circuit required by the data receiving circuit can be further simplified, the load can be further reduced, and the input data transmission speed can be further improved.

As analyzed above, in some embodiments, M can be 4, and the phase difference between the sampling clocks received by any two consecutively numbered data paths is 90°. For example, the phase of the sampling clock received by the first data path is 0°, the phase of the sampling clock received by the second data path is 90°, the phase of the sampling clock received by the third data path is 180°, and the phase of the sampling clock received by the fourth data path is 270°. In other embodiments, the phase difference between the sampling clocks received by any two consecutively numbered data paths can also be 45°. For example, the phase of the sampling clock received by the first data path is 0°, the phase of the sampling clock received by the second data path is 45°, the phase of the sampling clock received by the third data path is 90°, the phase of the sampling clock received by the fourth data path is 135°, and the phase of the sampling clock received by the fifth data path is 180°.

The first encoding circuit 103 of the i-th data path 100 can receive the second signal pair OUT2 output by the i-th data path 100, and the first encoding circuit 103 of the first data path 100 receives the second signal pair OUT2 output by the first data path 100, wherein 1＜i≤M, M≥3. It can be understood that the i-th data path 100 receives the input data at the current moment, and the second signal pair OUT2 output by the first encoding circuit 103 of the i-th data path 100 is the second signal pair OUT2 output by the i-th data path in the previous time period compared to the current moment. For example, the i-th data path 100 receives input data in the 4th clock cycle, that is, the current moment is in the 4th clock cycle (or, the i-th data path 100 receives input data to be sampled and output at the sampling phase of the 4th clock cycle), and the first encoding circuit 103 of the i-th data path 100 receives the second signal pair OUT2 sampled and output by the i-th data path 100 at the sampling phase of the 3rd clock cycle. It can be understood that, for the i-th data path 100, compared with the interval between the time when the other data paths 100 transmit input data and the time when the i-th data path 100 currently transmits input data, the i-th data path 100 has a shorter time interval than the i-th data path 100. The time interval between the moment of the input data last transmitted by the i-th data path 100 and the moment of the input data currently transmitted by the i-th data path 100 is longer, that is, the influence of the inter-symbol interference caused by the input data last transmitted by the i-th data path 100 on the input data currently transmitted is relatively small. Using the input data last transmitted by the i-th data path 100 as one of the input data for obtaining the first control signal TapA can not only ensure that the input data with the smallest influence on the inter-symbol interference can participate in the decision feedback equalization to adjust the first signal pair OUT1, but also reduce the complexity of the circuit required for participating in the decision feedback equalization.

In some specific embodiments, the first encoding circuit 103 of the i-th data path 100 receives the second signal pair OUT2 output by at least two data paths 100 except the (i-1)-th data path 100, and the first encoding circuit 103 of the 1st data path 100 receives the second signal pair OUT2 output by at least two data paths 100 except the M-th data path 100; in addition, the first encoding circuit 103 of the i-th data path 100 may receive the second signal pair OUT2 output by the i-th data path 100, and the first encoding circuit 103 of the 1st data path 100 receives the second signal pair OUT2 output by the 1st data path 100, wherein 1＜i≤M, M≥3.

FIG6 is another functional block diagram of a data path in a data receiving circuit. Referring to FIG6 , the i-th data path 100 may further include: a second adjustment circuit 105 configured to receive a second signal pair OUT2 output by the i-1th data path 100, and adjust the first signal pair OUT1 in the i-th data path 100 in response to the received second signal pair OUT2, wherein if the i-th data path 100 is the 1st data path 100, the i-1th data path 100 is the Mth data path 100. As can be seen from the above analysis, the second signal pair OUT2 output by the i-1th data path 100 is the input data that has the greatest impact on the input data currently transmitted by the i-th data path 100, that is, the previously transmitted first bit data has the greatest impact on the inter-code interference caused by the currently transmitted input data. Therefore, an independent second adjustment circuit 105 can be set, so that the second adjustment circuit 105 responds to the second signal pair OUT2 output by the i-1th data path 100 to adjust the first signal pair OUT1 of the i-th data path 100, thereby reducing the impact of the inter-code interference caused by the previous bit data on the currently transmitted input data, and further improving the accuracy of input data transmission.

In a specific example, taking the 4-tap equalization circuit as an example, the second adjustment circuit of the first data path 100 receives the second signal pair OUT2 output by the fourth data path 100, the second adjustment circuit of the second data path 100 receives the second signal pair OUT2 output by the first data path 100, the second adjustment circuit of the third data path 100 receives the second signal pair OUT2 output by the second data path 100, and the second adjustment circuit of the fourth data path 100 receives the second signal pair OUT2 output by the third data path 100.

Figure 7 is another functional block diagram of the data path in the data receiving circuit. Referring to Figure 7, the i-th data path 100 may also include: a third adjustment circuit 106, configured to receive the second signal pair OUT2 output by the i-2 data path 100, and adjust the first signal pair OUT1 in the i-th data path 100 in response to the received second signal pair OUT2, wherein if the i-th data path 100 is the second data path 100, the i-2 data path 100 is the M-th data path 100, and if the i-th data path 100 is the first data path 100, the i-2 data path 100 is the M-1th data path 100. For the currently transmitted input data, the inter-code interference caused by the previously transmitted second bit data is also relatively large. Therefore, an independent third adjustment circuit 106 can be set, so that the third adjustment circuit 106 responds to the second signal pair OUT2 output by the i-2 data path 100 to adjust the first signal pair OUT1 of the i data path 100, thereby reducing the inter-code interference caused by the previously transmitted second bit data on the currently transmitted input data, and further improving the accuracy of input data transmission.

In a specific example, taking the 4-tap equalization circuit as an example, the third adjustment circuit of the first data path 100 receives the second signal pair OUT2 output by the third data path 100, the third adjustment circuit of the second data path 100 receives the second signal pair OUT2 output by the fourth data path 100, the third adjustment circuit of the third data path 100 receives the second signal pair OUT2 output by the first data path 100, and the third adjustment circuit of the fourth data path 100 receives the second signal pair OUT2 output by the second data path 100.

It can be understood that, in a specific example, the i-th data path 100 may include both the second regulating circuit and the third regulating circuit. In another specific example, the i-th data path 100 may include one of the second regulating circuit and the third regulating circuit.

FIG8 is another functional block diagram of a data path in a data receiving circuit. Referring to FIG8 , in some other specific embodiments, M-N≥2; then the i-th data path 100 may also include: a second encoding circuit 107, configured to receive the second signal pair OUT2 output by at least two data paths 100, encode all received second signal pairs OUT2, and output a second control signal; wherein the second encoding circuit and the first encoding circuit 103 respectively receive the second signal pair OUT2 output by different data paths 100; a fourth adjustment circuit 108, configured to receive the second control signal, and adjust the first signal pair OUT1 in the i-th data path 100 in response to the second control signal. In this way, it is beneficial to further reduce the circuit complexity, reduce the circuit volume, and reduce the load of the data receiving circuit, thereby further improving the input data transmission speed and further reducing the input data transmission delay.

For the manner in which the second encoding circuit 107 performs encoding processing and the principle of the fourth adjustment circuit adjusting the first signal pair OUT1, reference may be made to the above-mentioned specific description of the first encoding circuit 103 and the first adjustment circuit 104, which will not be repeated here. In a specific example, the second encoding circuit of the first data path 100 can receive the second signal pair OUT2 outputted by the fourth data path 100 and the third data path 100 respectively, the second encoding circuit of the second data path 100 can receive the second signal pair OUT2 outputted by the first data path 100 and the fourth data path 100 respectively, and the second encoding circuit of the third data path 100 can receive the second signal pair OUT2 outputted by the second data path 100 and the fourth data path 100 respectively. The second encoding circuit of the fourth data path 100 can receive the second signal pair OUT2 outputted by the third data path 100 and the second data path 100 respectively.

9 to 12 are several different functional block diagrams of the data receiving circuit. Taking M=4 as an example, the sampling clocks CLK corresponding to the first data path 100 to the fourth data path 100 are defined as DQS_0, DQS_90, DQS_180 and DQS_270, respectively. The second signal pairs OUT2 output by the first data path 100 to the fourth data path 100 are defined as OUT_0, OUT_90, OUT_180 and OUT_270, respectively. OUT_0[n-1] is the second signal pair output by the first data path in the previous clock cycle, and OUT_90[n-1] is the second signal pair output by the second data path in the previous clock cycle. The second signal pair output in the previous clock cycle, OUT_180[n-1] is the second signal pair output by the third data path in the previous clock cycle, and OUT_270[n-1] is the second signal pair output by the fourth data path in the previous clock cycle; the amplifier circuit, the first encoding circuit and the first adjustment circuit are collectively indicated by 20, T1, T2, T3 and T4 respectively represent control signals involved in DFE, for the first adjustment circuit 104, the control signal is the first control signal TapA, for the second adjustment circuit and the third adjustment circuit, the control signal is the corresponding received second signal pair OUT2. The following will describe several different implementations of the data receiving circuit in conjunction with the accompanying drawings, and the following "+" refers to an OR operation:

With reference to FIG. 4, FIG. 5, FIG. 7 and FIG. 9, in one example, for the sampling clock DQS_0, i.e., the first data path 100, OUT_270 is used as the control signal T1 of the second adjustment circuit 105, OUT_180 is used as the control signal T2 of the third adjustment circuit 106, OUT_90+OUT_0[n-1] is used as the first control signal TapA of the first adjustment circuit 104, i.e., T3+T4 is used as the first control signal TapA. For the sampling clock DQS_90, i.e., the second data path 100, OUT_0 is used as the control signal T1 of the second adjustment circuit 105, OUT_270 is used as the control signal T2 of the third adjustment circuit 106, OUT_180+OUT_90[n-1] is used as the first control signal TapA of the first adjustment circuit 104, i.e., T3+T4 is used as the first control signal TapA. For the sampling clock DQS_180, i.e., the third data path 100, OUT_90 is used as the control signal T1 of the second adjustment circuit 105, OUT_0 is used as the control signal T2 of the third adjustment circuit 106, OUT_270+OUT_180[n-1] is used as the first control signal TapA of the first adjustment circuit 104, i.e., T3+T4 is used as the first control signal TapA. For the sampling clock DQS_270, i.e., the fourth data path 100, OUT_180 is used as the control signal T1 of the second adjustment circuit 105, OUT_90 is used as the control signal T2 of the third adjustment circuit 106, OUT_0+OUT_270[n-1] is used as the first control signal TapA of the first adjustment circuit 104, i.e., T3+T4 is used as the first control signal TapA.

With reference to FIGS. 4 to 6 and 10, in another example, for the first data path 100, OUT_270 is used as the control signal T1 of the second regulating circuit 105, and OUT_90+OUT_180+OUT_0[n-1] is used as the first control signal TapA of the first regulating circuit 104, that is, T2+T3+T4 is used as the first control signal TapA. For the second data path 100, OUT_0 is used as the control signal T1 of the second regulating circuit 105, and OUT_270+OUT_180+OUT_90[n-1] is used as the first control signal TapA of the first regulating circuit 104, that is, T2+T3+T4 is used as the first control signal TapA. For the third data path 100, OUT_90 is used as the control signal T1 of the second regulating circuit 105, and OUT_0+OUT_270+OUT_180[n-1] is used as the first control signal TapA of the first regulating circuit 104, that is, T2+T3+T4 is used as the first control signal TapA. For the fourth data path 100 , OUT_180 serves as the control signal T1 of the second regulating circuit 105 , OUT_90+OUT_0+OUT_270[n−1] serves as the first control signal TapA of the first regulating circuit 104 , that is, T2+T3+T4 serves as the first control signal TapA.

With reference to FIG. 4 , FIG. 5 and FIG. 11 , in another example, for the first data path 100 , OUT_270+OUT_180+OUT_90+OUT_0[n-1] is used as the first control signal TapA of the first adjustment circuit 104, that is, T1+T2+T3+T4 is used as the first control signal TapA. For the second data path 100 , OUT_0+OUT_270+OUT_180+OUT_90[n-1] is used as the first control signal TapA of the first adjustment circuit 104, that is, T1+T2+T3+T4 is used as the first control signal TapA. For the third data path 100 , OUT_90+OUT_0+OUT_270+OUT_180[n-1] is used as the first control signal TapA of the first adjustment circuit 104, that is, T1+T2+T3+T4 is used as the first control signal TapA. For the fourth data path 100 , OUT_180+OUT_90+OUT_0+OUT_270[n−1] serves as the first control signal TapA of the first regulating circuit 104 , that is, T1+T2+T3+T4 serves as the first control signal TapA.

With reference to FIG. 4 , FIG. 5 and FIG. 12 , in another example, for the first data path 100 , OUT_90+OUT_0[n-1] is used as the first control signal TapA of the first adjustment circuit 104 , that is, T3+T4 is used as the first control signal TapA, and OUT_270+OUT_180 is used as the second control signal of the fourth adjustment circuit 104 , that is, T1+T2 is used as the second control signal; for the second data path 100 , OUT_180+OUT_90[n-1] is used as the first control signal TapA of the first adjustment circuit 104 , that is, T3+T4 is used as the first control signal TapA, and OUT_0+OUT_270 is used as the second control signal of the fourth adjustment circuit , that is, T1 +T2 is used as the second control signal; for the third data path 100, OUT_270+OUT_180[n-1] is used as the first control signal TapA of the first regulation circuit 104, that is, T3+T4 is used as the first control signal TapA, OUT_90+OUT_0 is used as the second control signal of the fourth regulation circuit, and T1+T2 is used as the second control signal; for the fourth data path 100, OUT_0+OUT_270[n-1] is used as the first control signal TapA of the first regulation circuit 104, that is, T3+T4 is used as the first control signal TapA, OUT_180+OUT_90 is used as the second control signal of the fourth regulation circuit, that is, T1+T2 is used as the second control signal.

FIG. 13 is a schematic diagram of a circuit structure of an amplifier circuit and a first adjustment circuit 104 in any data path 100. 14 is a schematic diagram of a circuit structure of the first sub-compensation circuit or the second sub-compensation circuit in FIG. 13 , and FIG. 15 is another schematic diagram of a circuit structure of the amplification circuit and the first adjustment circuit 104 in any data path 100 .

Referring to Figure 13, the first signal pair OUT1 includes a first data signal OUT1_O and a first reference data signal OUT1_E, the amplification circuit includes a first node net1 and a second node net2, the first node net1 outputs the first data signal OUT1_O, and the second node net2 outputs the first reference data signal OUT1_E; the first adjustment circuit 104 includes: a first control circuit 114, connected between the first node net1 and the ground, turned on or off according to the second sub-control signal TapA2; a second control circuit 124, connected between the second node net2 and the ground, turned on or off according to the first sub-control signal TapA1.

When the second sub-control signal TapA2 is 1, the first control circuit 114 is turned on, so that the transmission path between the first node net1 and the ground is turned on; when the second sub-control signal TapA2 is 0, the first control circuit 114 is turned off, so that the transmission path between the first node net1 and the ground via the first control circuit 114 is turned off; when the first sub-control signal TapA1 is 1, the second control circuit 124 is turned on, so that the transmission path between the second node net2 and the ground is turned on; when the first sub-control signal TapA1 is 0, the second control circuit 124 is turned off, so that the transmission path between the second node net2 and the ground via the second control circuit 124 is turned off.

The first control circuit 114 may include: a first NMOS transistor MN1, the gate of which receives the second sub-control signal TapA2, and the first NMOS transistor MN1 is connected between the first node net1 and the ground terminal; the second control circuit 124 may include: a second NMOS transistor MN2, the gate of which receives the first sub-control signal TapA1, and the second NMOS transistor MN2 is connected between the second node net2 and the ground terminal. The drain of the first NMOS transistor MN1 is connected to the first node net1, and the source is connected to the ground terminal; the drain of the second NMOS transistor MMN2 is connected to the second node net2, and the source is connected to the ground terminal.

When the second sub-control signal TapA2 is 1, the first NMOS transistor MN1 is turned on; when the second sub-control signal TapA2 is 0, the first NMOS transistor MN1 is turned off. When the first sub-control signal TapA1 is 1, the second NMOS transistor MN2 is turned on; when the first sub-control signal TapA1 is 0, the second NMOS transistor MN2 is turned off.

Referring to FIG. 13 , the first adjustment circuit 104 may further include: a first compensation circuit 134, connected between the first control circuit 114 and the ground terminal and between the second control circuit 124 and the ground terminal, and the first control circuit 114 and the second control circuit 124 are both connected between the first compensation circuit 134 and the first node net1, and the first compensation circuit 134 is configured to receive the first tap signal TapC and adjust the first signal pair OUT1 with a first adjustment value corresponding to the first tap signal TapC. Specifically, the equivalent resistance value of the first compensation circuit 134 is adjustable, so that the equivalent resistance value between the first node net1 and the ground terminal is variable, and the equivalent resistance value between the second node net2 and the ground terminal is variable, and the equivalent resistance value affects the ability to adjust the first signal pair OUT1, so that the DFE function of the i-th data path 100 has a variety of different adjustment capabilities.

The first compensation circuit 134 is connected between the source of the first NMOS transistor MN1 and the ground terminal, and is also connected between the source of the second NMOS transistor MN2 and the ground terminal.

Referring to FIGS. 13 to 15 , the first compensation circuit 134 may include: a plurality of third NMOS tubes MN3 connected in parallel, the gate of each third NMOS tube MN3 receiving one bit of data in the first tap signal TapC, and each third NMOS tube MN3 connected between the first control circuit 114 and the ground terminal and between the second control circuit 124 and the ground terminal. The more the number of the third NMOS tubes MN3 that are turned on in the first compensation circuit 134, the smaller the equivalent resistance value of the first compensation circuit 134. It should be noted that, for the convenience of illustration, FIG. 13 does not illustrate the situation where the third NMOS tubes MN3 are connected in parallel. In fact, the first compensation circuit 134 includes a plurality of third NMOS tubes MN3 connected in parallel, the drain of each third NMOS tube MN3 is connected to the source of the first NMOS tube MN1 and/or the source of the second NMOS tube MN2, and the source of each third NMOS tube MN3 is connected to the ground terminal.

In some examples, referring to FIG. 13 and FIG. 14 , the first compensation circuit 134 may include a first sub-compensation circuit and a second sub-compensation circuit, the first sub-compensation circuit is connected between the first control circuit 114 and the ground terminal, and the second sub-compensation circuit is connected between the second control circuit 124 and the ground terminal, wherein the first sub-compensation circuit and the second sub-compensation circuit both include a plurality of third NMOS transistors MN3 connected in parallel, the number of the third NMOS transistors MN3 of the first sub-compensation circuit and the third NMOS transistors MN3 of the second sub-compensation circuit are the same and correspond to each other, and the gates of the third NMOS transistors MN3 in the first sub-compensation circuit and the corresponding third NMOS transistors MN3 in the second sub-compensation circuit both receive one bit of data in the first tap signal TapC. That is, the first control circuit 114 and the second control circuit 124 are respectively connected to different third NMOS transistor groups, and the third NMOS transistor groups include a plurality of third NMOS transistors MN3 connected in parallel. It should be noted that, for the convenience of illustration, FIG13 uses a single third NMOS tube MN3 to illustrate multiple third NMOS tubes MN3 in parallel, and takes the bit number of the first tap signal TapC as a as an example. FIG14 illustrates that the gate of each third NMOS tube MN3 in the multiple third NMOS tubes MN3 in parallel is controlled by TapC[a-1] to TapC[0], respectively, wherein TapC[a-1] to TapC[0] correspond to the highest bit data to the lowest bit data of the first tap signal TapC, respectively. In other words, FIG14 illustrates a schematic diagram of the circuit structure of the first sub-compensation circuit or the second sub-compensation circuit. In conjunction with FIG13 and FIG14, the drain of the third NMOS tube MN3 of the first sub-compensation circuit is connected to the source of the first NMOS tube MN1, and the drain of the third NMOS tube MN2 of the second sub-compensation circuit is connected to the source of the second NMOS tube MN2.

In addition, the channel width-to-length ratio of the third NMOS tube MN3 controlled by different bit data of the first tap signal TapC may be different. For the third NMOS tube MN3, its equivalent resistance is negatively correlated with the channel width-to-length ratio, that is, the larger the channel width-to-length ratio, the smaller the equivalent resistance. By setting the channel width-to-length ratio of each third NMOS tube MN3, the equivalent resistance value of different third NMOS tubes MN3 can be set, thereby adjusting the amplitude of the level of the first signal pair adjusted by the first compensation circuit. Generally, the smaller the equivalent resistance value of the third NMOS tube MN3, the stronger the adjustment ability of the branch where the third NMOS tube MN3 is located to adjust the level of the first signal pair OUT1. Therefore, the channel width-to-length ratio of different third NMOS tubes MN3 can be reasonably set according to demand. In some examples, the channel width-to-length ratio of the third NMOS tube MN3 controlled by the high bit data in the first tap signal TapC is the first width-to-length ratio, and the channel width-to-length ratio of the third NMOS tube MN3 controlled by the low bit data is the second width-to-length ratio, and the first width-to-length ratio can be greater than the first width-to-length ratio.

In other examples, referring to FIG. 15 , each third NMOS transistor MN3 in the first compensation circuit 134 is connected both between the first control circuit 114 and the ground terminal and between the second control circuit 124 and the ground terminal. That is, the first control circuit 114 and the second control circuit 124 are connected to the same third NMOS transistor group, and the third NMOS transistor group includes a plurality of third NMOS transistors MN3 connected in parallel. The first control circuit 114 and the second control circuit 1124 can be connected to the same third NMOS transistor group, and the third NMOS transistor group includes a plurality of third NMOS transistors MN3 connected in parallel.

The first tap signal TapC is multi-bit data. It can be understood that the number of third NMOS tubes MN3 connected to the first control circuit 114 can be greater than or equal to the number of bits of the first tap signal TapC, and the number of third NMOS tubes MN3 connected to the second control circuit 124 can be greater than or equal to the number of bits of the first tap signal TapC.

The first tap signal TapC can be obtained based on the addition of the first tap sub-signal and the second tap sub-signal, wherein the first tap sub-signal and the second tap sub-signal are both multi-bit data, and the first tap sub-signal and the second tap sub-signal are added in a binary addition manner to obtain the first tap signal TapC. Taking the first tap sub-signal as 5-bit data and the second tap sub-signal as 4-bit data as an example, the first tap sub-signal and the second tap sub-signal can be added to obtain 5-bit data. In an example, the first tap sub-signal and the second tap sub-signal can be stored in a mode register 115 (MR115, Model Register 115) and a mode register 116 (MR116, Model Register 116), respectively.

In another example, the first tap signal TapC may also be multi-bit data stored in a mode register.

For the specific circuit implementation of the second regulating circuit 105 and the third regulating circuit 106, reference may be made to the specific circuit of the aforementioned first regulating circuit 104. Specifically, referring to FIG13 and FIG15, the second regulating circuit 105 may include: an eleventh NMOS transistor MN11, in the second regulating circuit 105 of the i+1th data path, the gate of the eleventh NMOS transistor MN11 receives the second data signal OUT2_O in the second signal pair OUT2 output by the i-th data path, and the eleventh NMOS transistor MN11 is connected between the second node net2 and the ground terminal; a twelfth NMOS transistor MN12, in the second regulating circuit 105 of the i+1th data path, the gate of the twelfth NMOS transistor MN12 receives the second complementary data signal OUT2_E in the second signal pair OUT2 output by the i-th data path, and the twelfth NMOS transistor MN12 is connected between the first node net1 and the ground terminal.

13 and 15 , the third regulating circuit 106 may include: a thirteenth NMOS transistor MN13; in the third regulating circuit 106 of the i+1th data path, the gate of the thirteenth NMOS transistor MN13 receives the second data signal OUT2_O in the second signal pair OUT2 output by the i-1th data path, and the thirteenth NMOS transistor MN13 is connected between the second node net2 and the ground; and a fourteenth NMOS transistor MN14; in the third regulating circuit 106 of the i+1th data path, the gate of the fourteenth NMOS transistor MN14 receives the second complementary data signal OUT2_E in the second signal pair OUT2 output by the i-th data path, and the fourteenth NMOS transistor MN14 is connected between the first node net1 and the ground.

Correspondingly, referring to FIG. 13 and FIG. 15 , the second adjustment circuit 105 and the third adjustment circuit 106 may also be respectively provided with a second compensation circuit 115 and a third compensation circuit 116, wherein the second compensation circuit 115 is connected between the second adjustment circuit 105 and the ground terminal, and the third compensation circuit 116 is connected between the third adjustment circuit 106 and the ground terminal. The second compensation circuit 115 includes a plurality of NMOS transistors connected in parallel, and each NMOS transistor receives a bit of data in the second tap signal Tap1 to be turned on or off, so that the equivalent resistance value of the second compensation circuit 115 is adjustable; the third compensation circuit 116 includes a plurality of NMOS transistors connected in parallel, and each NMOS transistor receives a bit of data in the third tap signal Tap2 to be turned on or off, so that the equivalent resistance value of the third compensation circuit 116 is adjustable. For the relevant description of the second compensation circuit 115 and the third compensation circuit 116, reference may be made to the corresponding description of the first compensation circuit 134, which will not be repeated here.

With reference to FIG9 and FIG13, for the first data path, OUT2_O and OUT2_E in the second adjustment circuit 105 are two differential signals in OUT_270, respectively, OUT2_O and OUT2_E in the third adjustment circuit 106 are two differential signals in OUT_180, respectively, and the first sub-control signal TapA1 and the second sub-control signal TapA2 are two differential signals in OUT_90+OUT_0[n-1] (i.e., the result of the OR operation); for the second data path, OUT2_O and OUT2_E in the second adjustment circuit 105 are respectively OUT_0, OUT2_O and OUT2_E in the third adjustment circuit 106 are two differential signals in OUT_270, and the first sub-control signal TapA1 and the second sub-control signal TapA2 are two differential signals in OUT_180+OUT_90[n-1] (i.e., the result of the OR operation); for the third data path, OUT2_O and OUT2_E in the second adjustment circuit 105 are two differential signals in OUT_90, and OUT2_O and OUT2_E in the third adjustment circuit 106 are two differential signals in OUT_0. Two differential signals, the first sub-control signal TapA1 and the second sub-control signal TapA2 are respectively two differential signals in OUT_270+OUT_180[n-1] (i.e., the result of the OR operation); for the fourth data path, OUT2_O and OUT2_E in the second adjustment circuit 105 are respectively two differential signals in OUT_180, OUT2_O and OUT2_E in the third adjustment circuit 106 are respectively two differential signals in OUT_90, and the first sub-control signal TapA1 and the second sub-control signal TapA2 are respectively two differential signals in OUT_0+OUT_270[n-1] (i.e., the result of the OR operation).

Continuing to refer to FIG. 13 , the amplifier circuit 101 may include: a fourth NMOS transistor MN4, the gate of the fourth NMOS transistor MN4 receives the input data IN, the drain is connected to the working power supply VDD through the first resistor R1, the drain of the fourth NMOS transistor MN4 is connected to the first node net1 and outputs the first data signal OUT1_O, and the source is coupled to the ground; a fifth NMOS transistor MN5, the gate of the fifth NMOS transistor MN5 receives the reference voltage VREF, the drain is connected to the working power supply VDD through the second resistor R2, the drain of the fifth NMOS transistor MN5 is connected to the second node net2 and outputs the first reference data signal OUT1_E, the source is coupled to the ground, and the first reference data signal OUT1_E and the first data signal OUT1_O constitute a first signal pair OUT1. The resistance values of the first resistor R1 and the second resistor R2 are the same or nearly the same.

Continuing to refer to FIG. 13 , the amplifier circuit 101 may further include: a sixth NMOS transistor MN6, the gate of the sixth NMOS transistor MN6 receives the bias signal Bias, the drain is connected to the conductive source of the fourth NMOS transistor MN4 and the source of the fifth NMOS transistor MN5, and the source of the sixth NMOS transistor MN6 is connected to the ground terminal. During the operation of the amplifier circuit 101, the bias signal Bias is a high-level signal, that is, the sixth NMOS transistor MN6 is turned on.

FIG16 is another structural diagram of the amplifier circuit, the first control circuit, the second control circuit and the first compensation circuit in any data path. Referring to FIG16, in other embodiments, the amplifier circuit 101 may include: a current source I0, one end of which is connected to the working power supply VDD; a third PMOS tube MP3, connected between the other end of the current source I0 and the first node net1, and the gate of the third PMOS tube MP3 receives the input data IN; a fourth PMOS tube MP4, connected between the other end of the current source I0 and the second node net2, and the gate of the fourth PMOS tube MP4 receives the reference voltage VREF. That is, the drain of the third PMOS tube MP3 is connected to the first node net1, and the drain of the fourth PMOS tube MP4 is connected to the second node net2.

It should be noted that the level values of the input data IN and the reference voltage VREF are different, so that the turn-on time of the third PMOS tube MP3 receiving the input data IN is different from the turn-on time of the fourth PMOS tube MP4 receiving the reference voltage VREF, and at the same time, the conduction degree of the third PMOS tube MP3 is different from the conduction degree of the fourth PMOS tube MP4. It can be understood that, based on the fact that the conduction degree of the third PMOS tube MP3 is different from the conduction degree of the fourth PMOS tube MP4, the third PMOS tube MP3 and the fourth PMOS tube MP4 have different shunting capabilities for the current provided by the current source I0, so that the level at the first node net1 is different from the level at the second node net2.

In one example, when the level of the input data IN is lower than the level of the reference voltage VREF, the conduction degree of the third PMOS tube MP3 is greater than the conduction degree of the fourth PMOS tube MP4, so that the current provided by the current source I0 flows more into the path where the third PMOS tube MP3 is located, so that the current at the first node net1 is greater than the current at the second node net2, thereby further making the level of the first data signal output by the first node net1 high and the level of the first reference data signal output by the second node net2 low. In other words, the level of the input data IN is lower than the level of the reference voltage VREF, and the level of the first data signal is higher than the level of the first reference data signal. In another example, the level of the input data IN is higher than the level of the reference voltage VREF, and the level of the first data signal is lower than the level of the first reference data signal.

Correspondingly, the first control circuit 114, the second control circuit 124 and the first compensation circuit 134 can also be composed of PMOS tubes. The working principles of the first control circuit 114, the second control circuit 124 and the first compensation circuit 134 are roughly the same as the aforementioned related circuits composed of NMOS tubes. The main difference is that the gate of the PMOS tube is turned on in response to a low-level signal and the gate of the NMOS tube is turned on in response to a high-level signal.

It can be understood that a suitable amplifier circuit can be selected according to the maximum level of the input data IN. For example, if the maximum level of the input data IN is relatively large, an amplifier circuit as shown in Figure 13 is used, that is, the gate of the NMOS tube receives the input data IN. If the maximum level of the input data IN is relatively small, an amplifier circuit as shown in Figure 16 is used, that is, the gate of the PMOS tube receives the input data IN.

FIG17 is a schematic diagram of a circuit structure of a sampling circuit. Referring to FIG17 , the sampling circuit 102 may include: a seventh NMOS transistor MN7, whose gate is connected to the first node net1 and whose source is connected to the ground; an eighth NMOS transistor MN8, whose gate is connected to the second node net2 and whose source is connected to the ground; a latch composed of a first PMOS transistor MP1, a second PMOS transistor MP2, a ninth NMOS transistor MN9 and a tenth NMOS transistor MN10, wherein the drain of the seventh NMOS transistor MN7 is connected to the source of the ninth NMOS transistor MN9 and the drain of the ninth NMOS transistor MN9 outputs the second data signal OUT2_O, and the drain of the eighth NMOS transistor MN8 is connected to the source of the tenth NMOS transistor MN10 and the drain of the tenth NMOS transistor MN10 outputs the second complementary data signal OUT2_E; and two reset PMOS transistors MP0, wherein the gate of the reset PMOS transistor MP0 receives the sampling clock CLK and the source is connected to the working power supply VDD, and the drain of the reset PMOS transistor MP0 is connected to the drain of the ninth NMOS transistor MN9 and the drain of the tenth NMOS transistor MN10.

When the sampling signal CLK is a high level signal, the sampling circuit 102 outputs a valid second data signal OUT2_O and a second complementary data signal OUT2_E; when the sampling signal CLK is a low level signal, the second data signal OUT2_O and the second complementary data signal OUT2_E are both reset to high level signals.

The working principles of the amplifier circuit and the sampling circuit are described below in conjunction with FIG. 13 and FIG. 17 :

The input data IN of the fourth data path 100 is 0, that is, a low-level signal, the voltage of the input data IN is less than the reference voltage VREF, and the conduction degree of the fourth NMOS tube MN4 is less than the conduction degree of the fifth NMOS tube MN5; the first node net1 is discharged via the fourth NMOS tube MN4, that is, the voltage of the first node net1 is pulled down, and the second node net2 is discharged via the fifth NMOS tube MN5, and the voltage of the second node net2 is also pulled down; because the conduction degree of the fourth NMOS tube MN4 is less than the conduction degree of the fifth NMOS tube MN5, the discharge speed of the first node net1 is less than the discharge speed of the second node net2, that is, the speed at which the first node net1 is pulled down is less than the speed at which the second node net2 is pulled down, and therefore, the voltage of the first data signal OUT1_O output by the first node net1 is greater than the voltage of the first reference data signal OUT1_E output by the second node net2. Correspondingly, the conduction degree of the seventh NMOS tube is greater than that of the eighth NMOS tube, so that the ninth NMOS tube is turned on before the tenth NMOS tube, the drain of the ninth NMOS tube outputs a low-level signal, and the drain of the tenth NMOS tube outputs a high-level signal, and finally the drain of the ninth NMOS tube outputs the second data signal OUT2_O, and the drain of the tenth NMOS tube outputs the second complementary data signal OUT2_E, and the second data signal OUT2_O is 0, and the second complementary data signal OUT2_E is 1.

The input data IN of the fourth data path 100 is 1, that is, a high-level signal, the voltage of the input data IN is greater than the reference voltage VREF, and the conduction degree of the fourth NMOS tube MN4 is greater than the conduction degree of the fifth NMOS tube MN5; the first node net1 is discharged via the fourth NMOS tube MN4, that is, the voltage of the first node net1 is pulled down, and the second node net2 is discharged via the fifth NMOS tube MN5, and the voltage of the second node net2 is also pulled down; since the conduction degree of the fourth NMOS tube MN4 is greater than the conduction degree of the fifth NMOS tube MN5, the discharge speed of the first node net1 is greater than the discharge speed of the second node net2, that is, the speed at which the first node net1 is pulled down is greater than the speed at which the second node net2 is pulled down, and therefore, the voltage of the first data signal OUT1_O output by the first node net1 is less than the voltage of the first reference data signal OUT1_E output by the second node net2. Correspondingly, the conduction degree of the seventh NMOS tube is less than that of the eighth NMOS tube, so that the ninth NMOS tube is turned on later than the tenth NMOS tube, the drain of the tenth NMOS tube outputs a low-level signal, and the drain of the ninth NMOS tube outputs a high-level signal, and finally the drain of the ninth NMOS tube outputs the second data signal OUT2_O, and the drain of the tenth NMOS tube outputs the second complementary data signal OUT2_E, and the second data signal OUT2_O is 1, and the second complementary data signal OUT2_E is 0.

For the principle of decision feedback equalization performed by the first adjustment circuit 104 , reference may be made to the above corresponding description, which will not be repeated here.

The data receiving circuit provided in the above embodiment can compensate the currently transmitted input data based on the multiple input data previously transmitted, so as to realize decision feedback equalization to improve the inter-symbol interference problem. And to achieve this purpose, the number of adjustment circuits required is less than the number of input data participating in DFE. Compared with the scheme in which the adjustment circuit corresponds to each bit of data participating in DFE, the embodiment of the present disclosure can reduce the complexity of the adjustment circuit, thereby reducing the load of the data receiving circuit, improving the speed of input data transmission, reducing the power consumption of the data receiving circuit, and reducing the DFE delay. For example, in some examples, more reaction time can be saved for 1-tap, so that 1-tap can better compensate for the currently transmitted input data, and further improve the accuracy of input data transmission. Among them, 1-tap here refers to the process in which the input data of the previous bit of the currently transmitted input data participates in DFE. It can be understood that in some embodiments, the adjustment circuit can only include the first adjustment circuit, and in other embodiments, the adjustment circuit can include any one or any combination of the aforementioned second adjustment circuit, third adjustment circuit and fourth adjustment circuit in addition to the first adjustment circuit.

Correspondingly, an embodiment of the present disclosure further provides a semiconductor device, comprising the data receiving circuit provided by the above embodiment.

The semiconductor device may be a wafer, a chip, or a system. In addition, the semiconductor device may also be a storage device, which may be a DRAM or an SRAM. The DRAM may be an SDRAM, which may be a DDR SDRAM, such as DDR4, DDR5, DDR6, LPDDR4, LPDDR5, or LPDDR6. In some embodiments, the semiconductor device may be a storage chip, which may be a DRAM chip or an SRAM chip. In addition, the input data may be DQ input data.

From the above analysis, it can be seen that the semiconductor device can reduce circuit complexity, save the area required for the circuit, reduce the load caused by the circuit, and improve the input data transmission speed while improving the inter-symbol interference problem.

Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

A data receiving circuit, comprising:

A plurality of data paths (100), each data path (100) in the plurality of data paths (100) receives input data and a sampling clock, and the sampling clock received by each data path (100) has a different phase, the plurality of data paths (100) comprising: a first data path to an Mth data path numbered in ascending order of natural numbers, the i-th data path being any one of the plurality of data paths (100), 1≤i≤M, M≥2, and the phase difference between the sampling clocks received by any two consecutively numbered data paths (100) in the plurality of data paths (100) being the same;

The i-th data path comprises: an amplifier circuit (101), configured to amplify the voltage difference between the voltage of the input data and the reference voltage and output a first signal pair; a sampling circuit (102), configured to receive the corresponding sampling clock, sample the first signal pair and output a second signal pair; a first encoding circuit (103), configured to receive the second signal pairs output by N data paths (100), encode all the received second signal pairs, and output a first control signal, N≤M; and a first adjustment circuit (104), configured to receive the first control signal and adjust the first signal pair in the i-th data path in response to the first control signal.
The data receiving circuit as claimed in claim 1, wherein the first encoding circuit (103) of the i-th data path receives the second signal pair output by at least two of the data paths (100) except the (i-1)-th data path, and the first encoding circuit (103) of the first data path receives the second signal pair output by at least two of the data paths (100) except the M-th data path; wherein 1＜i≤M, M≥3.
The data receiving circuit as described in claim 2, wherein the first encoding circuit (103) of the (i-1)th data path receives the second signal pair output by the (i-1)th data path and the second signal pair output by the (i)th data path; and the first encoding circuit (103) of the (M)th data path receives the second signal pair output by the (1)th data path and the second signal pair output by the (M)th data path.
The data receiving circuit as described in claim 2, wherein the first encoding circuit (103) of the Mth data path receives the second signal pair output by the first data path and the second signal pair output by the second data path; the first encoding circuit (103) of the (i-1)th data path receives the second signal pair output by the i-th data path and the second signal pair output by the (i+1)th data path, i+1＜M; the first encoding circuit (103) of the (M-1)th data path receives the second signal pair output by the first data path and the second signal pair output by the Mth data path.
The data receiving circuit according to claim 3 or 4, wherein M is 4, and the phase difference between the sampling clocks received by any two consecutively numbered data paths (100) is 90°.
The data receiving circuit as described in any one of claims 1 to 5, wherein the first encoding circuit (103) of the i-th data path receives the second signal pair including the output of the i-th data path, and the first encoding circuit (103) of the first data path receives the second signal pair including the output of the first data path; wherein 1＜i≤M, M≥3.
The data receiving circuit according to any one of claims 1 to 6, wherein N=M.
The data receiving circuit according to any one of claims 1 to 7, comprising:

The second signal pair includes a second data signal and a second complementary data signal, and the second data signal and the second complementary data signal are inverted signals to each other; the control signal includes a first sub-control signal and a second sub-control signal;

The first encoding circuit (103) comprises: a first sub-encoding circuit (113), the first sub-encoding circuit (113) being used to perform an OR operation on the received second data signal to obtain the first sub-control signal; and a second sub-encoding circuit (123), the second sub-encoding circuit (123) being used to perform an OR operation on the received second complementary data signal to obtain the second sub-control signal.
The data receiving circuit as claimed in claim 8, comprising:

The first signal pair includes a first data signal and a first reference data signal, the amplification circuit (101) includes a first node and a second node, the first node outputs the first data signal, and the second node outputs the first reference data signal;

The first regulating circuit (104) comprises: a first control circuit (114), connected between the first node and the ground, and turned on or off according to the second sub-control signal; a second control circuit (124), connected between the second node and the ground, and turned on or off according to the second sub-control signal The first sub-control signal is turned on or off.
The data receiving circuit as claimed in claim 9, comprising:

The first control circuit (114) comprises: a first NMOS transistor, a gate of the first NMOS transistor receiving the second sub-control signal, the first NMOS transistor being connected between the first node and the ground terminal;

The second control circuit (124) comprises: a second NMOS transistor, a gate of the second NMOS transistor receives the first sub-control signal, and the second NMOS transistor is connected between the second node and the ground terminal.
The data receiving circuit as described in claim 9, wherein the first adjustment circuit (104) further includes: a first compensation circuit (134), connected between the first control circuit (114) and the ground terminal and between the second control circuit (124) and the ground terminal, and the first control circuit (114) and the second control circuit (124) are both connected between the first compensation circuit (134) and the first node, and the first compensation circuit (134) is configured to receive a first tap signal and adjust the first signal pair with a first adjustment value corresponding to the first tap signal.
The data receiving circuit as described in claim 11, wherein the first compensation circuit (134) includes: a plurality of third NMOS transistors connected in parallel, the gate of each of the third NMOS transistors receiving one bit of data in the first tap signal, and each of the third NMOS transistors being connected between the first control circuit (114) and the ground terminal and between the second control circuit (124) and the ground terminal.
The data receiving circuit according to claim 11, wherein the first tap signal is obtained by adding the first tap sub-signal and the second tap sub-signal.
The data receiving circuit as described in any one of claims 1 to 13, wherein the i-th data path further includes: a second adjustment circuit (105), configured to receive the second signal pair output by the i-1th data path, and adjust the first signal pair in the i-th data path in response to the received second signal pair, wherein if the i-th data path is the 1st data path, then the i-1th data path is the Mth data path.
The data receiving circuit as described in claim 14, wherein the i-th data path further includes: a third adjustment circuit (106), configured to receive the second signal pair output by the i-2th data path, and adjust the first signal pair in the i-th data path in response to the received second signal pair, wherein if the i-th data path is the second data path, the i-2 data path is the M-th data path, and if the i-th data path is the first data path, the i-2 data path is the M-1th data path.
The data receiving circuit according to any one of claims 1 to 15, wherein M-N≥2; the i-th data path further comprises:

The second encoding circuit (107) is configured to receive the second signal pairs output by at least two of the data paths (100), encode all the received second signal pairs, and output a second control signal; wherein the second encoding circuit (107) and the first encoding circuit (103) respectively receive the second signal pairs output by different data paths (100);

A fourth adjustment circuit (108) is configured to receive the second control signal and adjust the first signal pair in the i-th data path in response to the second control signal.
The data receiving circuit according to any one of claims 1 to 16, wherein the amplifying circuit (101) comprises:

a fourth NMOS tube, wherein a gate of the fourth NMOS tube receives the input data, a drain of the fourth NMOS tube is connected to a working power supply via a first resistor, and a drain of the fourth NMOS tube outputs a first data signal, and a source of the fourth NMOS tube is coupled to a ground terminal;

A fifth NMOS tube, wherein the gate of the fifth NMOS tube receives the reference voltage, the drain is connected to the working power supply through a second resistor, and the drain of the fifth NMOS tube outputs a first reference data signal, the source is coupled to the ground, and the first reference data signal and the first data signal constitute the first signal pair.
The data receiving circuit as described in claim 17, wherein the amplifying circuit further includes: a sixth NMOS tube, the gate of the sixth NMOS tube receives a bias signal, the drain is connected to the conduction source of the fourth NMOS tube and the source of the fifth NMOS tube, and the source of the sixth NMOS tube is connected to the ground terminal.
A semiconductor device, comprising: a data receiving circuit as claimed in any one of claims 1 to 18.
The semiconductor device according to claim 19, wherein the semiconductor device comprises a memory chip.