CN102882817A - Equalizer circuit, data transmission system and equalization method - Google Patents
Equalizer circuit, data transmission system and equalization method Download PDFInfo
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- CN102882817A CN102882817A CN2012103625034A CN201210362503A CN102882817A CN 102882817 A CN102882817 A CN 102882817A CN 2012103625034 A CN2012103625034 A CN 2012103625034A CN 201210362503 A CN201210362503 A CN 201210362503A CN 102882817 A CN102882817 A CN 102882817A
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Abstract
The invention provides an equalizer circuit, a data transmission system and an equalization method. The equalizer circuit comprises a first adder, a decoder and a decision feedback equalizer, wherein the first adder receives a feedback signal and first input data which are output by a feed forward equalizer circuit, and is used for adding the first input data and the feedback signal to acquire an equalization output result; the decoder receives the equalization output result, and is used for decoding the equalization output result to acquire a decoding result; and the decision feedback equalizer receives the decoding result, and is used for filtering the decoding result on the basis of a first filter coefficient to acquire the feedback signal and outputs the feedback signal to the first adder, so that time-lag inter-symbol interference is eliminated. By the circuit, the system and the method, the decision feedback equalizer for filtering the output of a decision device to eliminate the inter-symbol interference is eliminated, so that error propagation can be avoided in the decision feedback equalizer.
Description
The present invention relates to the communications field, especially relate to a kind of equalizing circuit, the data transmission system equalization methods of unifying.
Background technology
Gigabit Ethernet physical layer (Gigabit Ethernet Physical Layer, GEPHY) is electricity mouthful ethernet physical layer.Hereinafter, GEPHY refers in particular to the physical layer subsystem (module) that is implemented in the electricity mouthful ethernet communication chip, in five classes or surpass five class unshielded twisted pairs (Unshielded Twisted Pair, UTP) finish both sides' communication on, and need to support the 1000BASE-T/100BASE-TX/10BASE-T agreement.In this article, relate in particular to communication under the 1000BASE-T consensus standard.
According to the ieee specification requirement, the 1000Base-T system transmits the 4D-PAM5 signal with the 125MBaud modulation rate on 4 pairs of unshielded twisted pairs, can reach the full-duplex data transmission of 1Gb/s.The 4D-PAM5 signal is when improving the availability of frequency spectrum, and its level hypotelorism is to 1/2 of 100 m ethernet MLT3 coding.In 1000Base-T, can use Trellis-coded modulation (Trellis Coded Modulation, TCM) and remedy this loss.Simultaneously, the length of cable of supporting is wanted to reach 100 meters, and cable transmission speed is as follows: (1) 125M symbol/second, 2b bit/symbol; (2) bit rate on the every pair of line is 250Mb/s.The GEPHY system uses the 4D-PAM5 signal, bit error rate (Bit Error Rate, BER) is along with the increase meeting of signal to noise ratio (Signal Noise Ratio, SNR) sharply descends, thereby receiver needs fully to eliminate to disturb and noise, increases SNR to obtain the less error rate.
For the GEPHY system, the key factor that affects the BER index is intersymbol interference (Inter-symbol Interference, ISI) and the noise in the channel.The impact that the data that receiver receives are disturbed owing to be subject to decaying and noise etc., the data that decoding obtains have certain error rate.Intersymbol interference comprises backward intersymbol interference (post-cursor ISI) and forward direction intersymbol interference (pre-cursor ISI).The forward direction intersymbol interference refers to that leading time is disturbed and the time interference that backward intersymbol interference lags behind to current sign in time for the time-domain signal more Zao than this cycle in time to current sign than late time-domain signal of this cycle.
An important means that overcomes intersymbol interference is at receiving terminal the signal distortion that channel causes to be compensated, and namely carries out channel equalization.Usually adopt forward equalizer (Feed Forward Equalizer, FFE) to eliminate the forward direction intersymbol interference, eliminate backward intersymbol interference and adopt based on the feedback equalizer (Decision Feed Back Equalizer, DFE) of hard decision.For example, to carrying out filtering from modulus according to the data that transducer (ADC) receives, with the intersymbol interference of elimination forward direction, and obtain FFE output data by FFE.The feedback signal addition that FFE output data and DFE export eliminating backward intersymbol interference, and obtains balanced output signal, i.e. soft decision signal r
kBalanced output signal r
kHard decision through decision device or amplitude limiter (Slicer) obtains court verdict, i.e. hard decision signal d
k, and with balanced output signal and court verdict addition, obtain decision error e, wherein decision error e is used for the factor updating operation of FFE and DFE.DFE is to court verdict d
kCarry out filtering, eliminating backward intersymbol interference, and obtain above-mentioned feedback signal.
Yet, when decision device carries out hard decision, if mistake appears in hard decision, then the court verdict dk of the mistake of decision device output can keep a period of time in the delay time register of DFE, so that during this period, the output of DFE is inaccurate, namely has error propagation (error propagation), and then causes equalizer output signal rk mistake to occur.
Summary of the invention
Embodiments of the invention provide a kind of equalizing circuit, the data transmission system equalization methods of unifying, and can avoid occurring in the equalizer error propagation.
First aspect provides a kind of equalizing circuit, comprising: first adder, and receiving feedback signals and by the first input data of forward equalizer output is used for the first input data and this feedback signal addition obtained balanced Output rusults; Decoder receives this equilibrium Output rusults, obtains decode results for this equilibrium Output rusults is deciphered; Feedback equalizer receives this decode results, is used for based on the first filter factor this decode results being carried out filtering, obtains this feedback signal, and exports this feedback signal to first adder, in order to eliminate the intersymbol interference that lags behind in time.
In the possible implementation of the first, above-mentioned equalizing circuit also comprises: forward equalizer, receive the second input data, be used for based on the second filter factor the second input data being carried out filtering, input data to eliminate leading in time intersymbol interference and to obtain first, and to first adder output the first input data; Decision device receives this equilibrium Output rusults, is used for that this equilibrium Output rusults is carried out hard decision and obtains court verdict; Second adder receives this court verdict and this equilibrium Output rusults, be used for should the equilibrium Output rusults and this court verdict addition obtain decision error; The first coefficient updating module receives this decision error, is used for upgrading the first filter factor according to this decision error, and exports the first filter factor to this feedback equalizer; The second coefficient updating module receives this decision error, is used for upgrading the second filter factor according to this decision error, and exports the second filter factor to this forward equalizer.
In conjunction with the possible implementation of the first of first aspect, in the possible implementation of the second, above-mentioned equalizing circuit also comprises: selector, receive this court verdict and this decode results, be used for selecting this decode results or this court verdict according to control information, and this decode results that will select or this court verdict output to this feedback equalizer as this feedback signal.
In conjunction with the possible implementation of the second of first aspect, in the third possible implementation, this selector selects this decode results to output to this feedback equalizer under the normal mode of operation of this equalizing circuit, selects this court verdict to output to this feedback equalizer under the training mode before the normal operation of this equalizing circuit.
Be combined in above-mentioned any possible implementation, in the 4th kind of possible implementation, this forward equalizer also is used for based on the second filter factor the second input data being carried out this filtering and eliminates the intersymbol interference that lags behind in time.
In conjunction with above-mentioned any possible implementation, in the 5th kind of possible implementation, be connected with a plurality of delay time registers between this decoder and this feedback equalizer.
In conjunction with above-mentioned any possible implementation, in the 6th kind of possible implementation, this decoder is the Trellis-coded modulation decoder.
Second aspect provides a kind of data transmission system, comprising: local transmitter is used for sending data to remote receiver; Local receiver is used for from long-range transmitter receive data; Blender is connected between this this locality transmitter and this data transmission system transmission line, and is connected between this local receiver and this transmission line; Above-mentioned any equalizing circuit is connected between this local receiver and this blender, is used for the intersymbol interference of the data of this local receiver reception of elimination.
The third aspect provides a kind of equalization methods, comprising: with the first input data and feedback signal addition, obtain balanced Output rusults; This equilibrium Output rusults deciphered obtain decode results; Based on the first filter factor this decode results is carried out filtering, obtain this feedback signal, in order to eliminate the intersymbol interference that lags behind in time.
In the possible implementation of the first, this equalization methods also comprises: based on the second filter factor the second input data are carried out filtering, to eliminate leading in time intersymbol interference and to obtain the first input data; This equilibrium Output rusults is carried out hard decision obtain court verdict; Should the equilibrium Output rusults and this court verdict addition obtain decision error; Upgrade the first filter factor according to this decision error; Upgrade the second filter factor according to this decision error.
In conjunction with the possible implementation of the first of the third aspect, in the possible implementation of the second, above-mentionedly based on the first filter factor this decode results is carried out filtering, also comprise: select this decode results according to control information, and based on the first filter factor this decode results is carried out filtering, wherein this equalization methods also comprises: select this court verdict according to this control information, and based on the first filter factor this court verdict is carried out filtering, obtain this feedback signal, in order to eliminate the intersymbol interference that lags behind in time.
In conjunction with the possible implementation of the second of the third aspect, in the third possible implementation, above-mentionedly select this decode results according to control information, comprise: in the situation of this control information indication normal mode of operation, select this decode results, wherein above-mentionedly select this court verdict according to this control information, comprising: in the situation of this control information indication training mode, select this court verdict.
In conjunction with above-mentioned any possible implementation, in the 4th kind of possible implementation, above-mentioned equalization methods also comprises: based on the first filter factor the data of this feedback equalizer input are carried out filtering and eliminate the intersymbol interference that lags behind in time.
In conjunction with above-mentioned any possible implementation, in the 5th kind of possible implementation, above-mentioned equalization methods also comprises: before based on the first filter factor this decode results being carried out filtering this decode results is carried out delay disposal.
In conjunction with above-mentioned any possible implementation, in the 6th kind of possible implementation, this is deciphered this equilibrium Output rusults and obtains decode results, comprising: this equilibrium Output rusults is carried out Trellis-coded modulation decoding obtain decode results.
The technical program can be eliminated intersymbol interference in the balanced Output rusults by with feedback equalizer decode results being carried out filtering, owing to no longer eliminate intersymbol interference by with feedback equalizer filtering being carried out in the output of decision device, therefore, can not occur in the feedback equalizer because the error propagation that causes of decision device mistake in judgment, thereby can in balanced Output rusults, mistake not occur.
Description of drawings
In order to be illustrated more clearly in the technical scheme of the embodiment of the invention, the below will do to introduce simply to the accompanying drawing of required use in the embodiment of the invention, apparently, below described accompanying drawing only be some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the schematic block diagram of a kind of equalizing circuit according to an embodiment of the invention.
Fig. 2 is the schematic block diagram of a kind of equalizing circuit according to another embodiment of the present invention.
Fig. 3 is the schematic block diagram of a kind of equalizing circuit according to still another embodiment of the invention
Fig. 4 is the schematic block diagram of forward equalizer according to an embodiment of the invention.
Fig. 5 is the schematic realization figure of forward equalizer according to another embodiment of the present invention.
Fig. 6 is the schematic realization figure of decision feedback equalization circuit according to an embodiment of the invention.
Fig. 7 is the schematic realization figure of equalizing circuit according to another embodiment of the present invention.
Fig. 8 is the structural diagram of data transmission system according to an embodiment of the invention.
Fig. 9 is the indicative flowchart of a kind of equalization methods according to an embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
For the error propagation phenomenon that exists in the above-mentioned equalizing circuit, the decoding of feedback equalization and Trellis-coded modulation (Trellis Coded Modulation, TCM) can be combined and avoid this phenomenon.Specifically, can utilize feedback equalization to eliminate a part of backward intersymbol interference, for example, only need except the later backward intersymbol interference in the second level and the second level, and in TCM decoding, eliminate the rear to intersymbol interference of the first order.This scheme can be avoided the error propagation phenomenon, still, eliminates intersymbol interference because 8 status signals that this scheme adopts feedback equalization that TCM decoding survivor path unit is exported carry out filtering, and therefore higher to processing requirements, implementation complexity is higher.For example, the selection of survival signal must be finished within the monocycle, and is harsh for timing (timing) requirement of TCM decoding loop.In addition, owing to need to all carry out the feedback equalization computing to 8 status signals, need more hardware, so that whole system area and power consumption are larger, affect the complete machine cost.
Fig. 1 is the schematic block diagram of a kind of equalizing circuit 100 according to an embodiment of the invention.Equalizing circuit 100 comprises: feedback equalizer 130, first adder 140 and decoder 120.
The first input data of first adder 140 receiving feedback signals and forward equalizer output are used for the first input data and this feedback signal addition obtained balanced Output rusults; Decoder 120 receives this equilibrium Output rusults, obtains decode results for this equilibrium Output rusults is deciphered; Feedback equalizer 130 receives this decode results, is used for based on the first filter factor this decode results being carried out filtering, obtains this feedback signal, and to first adder 140 these feedback signals of output, in order to eliminate the intersymbol interference that lags behind in time.
According to embodiments of the invention, feedback equalizer 130 can be preset equalizer, also can be adaptive equalizer, and namely above-mentioned filter factor can be predefined, also can be real-time update.Preset equalizer can before the transmission of data, determine filter factor by the test pulse signal, and sef-adapting filter can during the transmission of data, utilize intersymbol interference information automatically to adjust filter factor.Be not limited to this according to embodiments of the invention, for example, adaptive equalizer can be mixed use with preset equalizer, under training mode, the coefficient of equalizer is set according to training sequence, and under normal mode of operation, follow the tracks of the characteristic of channel that constantly changes by the adaptive algorithm of equilibrium, automatically adjust filter factor.Feedback equalizer 130 can be realized by nonlinear filter the filter of decision feedback equalization (for example, based on).Describe as example to realize equalizing circuit (being the decision feedback equalization circuit) based on the filter of decision feedback equalization according to embodiments of the invention.
According to embodiments of the invention, at the receiving terminal of data transmission system, equalizing circuit 100 can receive the data that ADC sends.Equalizing circuit 100 can use forward equalizer and feedback equalizer to eliminate intersymbol interference, certainly, also can only eliminate intersymbol interference with feedback equalizer.Particularly, adder 140 can be with data or the data of ADC output and the feedback signal addition of feedback equalizer 130 outputs of forward equalizer output, obtain balanced Output rusults, and balanced Output rusults is outputed to decoder 120, decoder 120 can be deciphered the data of input, obtains decode results.Feedback equalizer 130 carries out filtering based on filter factor to the decode results of decoder 120 outputs, and the intersymbol interference to estimate to lag behind in time obtains above-mentioned feedback signal, and above-mentioned feedback signal is outputed to adder 140.
Equalizing circuit programmable gate array (Field Programmable Gate Array at the scene according to an embodiment of the invention, FPGA) realize on the platform, be not limited to this according to embodiments of the invention, for example, also can realize at Digital Signal Processing (Digital Signal Processing, DSP) platform.
Can eliminate intersymbol interference in the balanced Output rusults by with feedback equalizer decode results being carried out filtering according to embodiments of the invention, owing to no longer eliminate intersymbol interference by with feedback equalizer filtering being carried out in the output of decision device, therefore, can not occur in the feedback equalizer because the error propagation that causes of decision device mistake in judgment, thereby can in balanced Output rusults, mistake not occur.
In addition, carry out filtering with above-mentioned 8 status signals to the output of TCM decoding survivor path unit and eliminate the technical scheme of intersymbol interference and compare, implementation complexity is lower, and because the hardware that uses is less, therefore, power consumption and the area of system are also less.
Alternatively, as another embodiment, be connected with a plurality of delay time registers between decoder 120 and the feedback equalizer 130.
For so that decoder 120 and feedback equalizer 130 can co-ordinations, can be input to feedback equalizer 130 in the decode results with decoder 120 outputs before, carry out delay process to decode results, the path delay of introducing when being used for regulating logic realization.
According to embodiments of the invention, decoder 120 is the Trellis-coded modulation decoder.For example, this Trellis-coded modulation decoder is viterbi decoder.
Fig. 2 is the schematic block diagram of a kind of equalizing circuit 200 according to another embodiment of the present invention.Equalizing circuit 200 comprises: feedback equalizer 230, first adder 240 and decoder 220, and similar with feedback equalizer 130, first adder 140 and the decoder 120 of Fig. 1 respectively, suitably omit detailed description at this.
According to embodiments of the invention, equalizing circuit 200 also comprises: forward equalizer 210, decision device 250, second adder 270, the first coefficient updating module 260 and the second coefficient updating module 280.
According to embodiments of the invention, forward equalizer 110 can be preset equalizer, also can be adaptive equalizer, and namely above-mentioned filter factor can be predefined, also can be real-time update.Preset equalizer can before the transmission of data, determine filter factor by the test pulse signal, and sef-adapting filter can during the transmission of data, utilize intersymbol interference information automatically to adjust filter factor.Be not limited to this according to embodiments of the invention, for example, adaptive equalizer can be mixed use with preset equalizer, under training mode, the coefficient of equalizer is set according to training sequence, and under normal mode of operation, follow the tracks of the characteristic of channel that constantly changes by the adaptive algorithm of equilibrium, automatically adjust filter factor.Above-mentioned forward equalizer can realize by linear filter (for example, transversal filter),
According to embodiments of the invention, at receiving terminal, forward equalizer 210 is carried out filtering based on filter factor to the second input data that receive, to eliminate leading in time intersymbol interference, namely the transmission characteristic of data transmission system is proofreaied and correct or compensated, thereby reduce the error rate.The intersymbol interference that lags behind in time can be further eliminated in feedback signal addition in adder 140 of the output data of forward equalizer 210 and feedback equalizer 130 outputs, obtains balanced Output rusults.For example, when forward direction equalizer 210 and feedback equalizer 230 are sef-adapting filter, can adopt the first coefficient updating module 260 and the second coefficient updating module 280 respectively the first filter factor and the second filter factor to be carried out real-time update.Certainly forward equalizer 210 and feedback equalizer 230 also can use same coefficient updating module that filter factor is carried out filtering.
Alternatively, as another embodiment, forward equalizer 210 also is used for based on the second filter factor the second input data being carried out filtering and eliminates the intersymbol interference that lags behind in time.
Postpone because the decoding of TCM decoder is processed to produce, therefore, when carrying out filtering based on the decode results of TCM decoder output, feedback equalizer might be able to not be eliminated all intersymbol interferences that lags behind in time.The delay that produces in order to remedy the TCM decoder can be eliminated the intersymbol interference that part lags behind in time in forward equalizer.
Fig. 3 is the schematic block diagram of a kind of equalizing circuit 300 according to still another embodiment of the invention.Equalizing circuit 300 comprises: forward equalizer 310, feedback equalizer 330, first adder 340, decoder 320, decision device 350, second adder 370 and coefficient updating module 360, with forward equalizer 210, feedback equalizer 230, first adder 240, decoder 220, decision device 250, second adder 270 and the coefficient updating module 260 of Fig. 2, suitably omit detailed description at this respectively.
According to embodiments of the invention, equalizing circuit 300 also comprises: selector 390.
According to embodiments of the invention, selector 390 receives above-mentioned court verdict and above-mentioned decode results, be used for selecting this decode results or this court verdict according to control information, and this decode results that will select or this court verdict output to this feedback equalizer as above-mentioned feedback signal.
According to embodiments of the invention, whether selector 390 is used for selecting the decode results of decoder 320 is outputed to feedback equalizer 330.Like this, can be as required or in the situation that satisfies default condition, just the decode results of decoder 320 is outputed to feedback equalizer 330.For example, only have at selector 390 in the situation of one tunnel input, the control information of selector 390 be 1 expression with the input of selector 390 as output, the control information of selector 390 is that 0 expression is not exported.Alternatively, the control information of selector 390 can be comprised of a plurality of bits, in order to can select road input conduct in the multichannel input to export according to the value of bit, for example, control information is the road input conduct output that selector 390 is selected in 0 expression, and control information is another road input conduct output that selector 390 is selected in 1 expression.
According to embodiments of the invention, selector 390 selects this decode results to output to feedback equalizer 330 under the normal mode of operation of equalizing circuit 300, selects court verdict to output to feedback equalizer 330 under the training mode before the normal operation of this equalizing circuit 300.
Owing under training mode, exist and exist erroneous transmissions to exert an influence to normal transfer of data in the feedback equalizer, and, under training mode, what send is the PAM3 signal, this PAM3 signal can be encoded without TCM, therefore, feedback equalizer carries out the time that filtering can be shortened training based on the court verdict of decision device under training mode, thereby has improved the efficient of system.
Fig. 4 is the schematic block diagram of forward equalizer 400 according to an embodiment of the invention.Forward equalizer 400 can be realized by transversal filter.
The first tap part 411 comprises filter factor C
-1And C
-2With corresponding delay time register, be used for to eliminate leading in time intersymbol interference to the impact of data transmission system, disturb in time by leading time to current sign for the time-domain signal of namely eliminating evening in this cycle.Centre cap 412 comprises filter factor C
0With corresponding delay time register, be used for eliminating the intersymbol interference (Current cursor ISI) of current sign.The second tap part 413 comprises C
1, C
2..., C
NWith corresponding delay time register, be used for eliminating the intersymbol interference of in time hysteresis to the impact of data transmission system, time-domain signal more Zao than this cycle after namely eliminating disturbed the time that current sign lags behind in time.
The first tap part 411 can receive the data of ADC 420 output and input data (ffe_data_in) as FFE, can also be connected at least one delay time register 440 between ADC 420 and FFE 410.Above-mentioned data are after process each tap of FFE, and the addition in adder 414 of the Output rusults of each tap obtains FFE output data (ffe_data_out).
The second tap part 413 can be at least part of overlapping with the tap of feedback equalizer, to promote the signal to noise ratio of data transmission system.
Fig. 5 is the schematic realization figure of forward equalizer 500 according to another embodiment of the present invention.Forward equalizer 500 is to realize the example of the forward equalizer 400 of Fig. 4.
The first tap part 520 comprises: first order tap, be used for the eq_tap_n1 of 8 bits and the filter factor eq_coef_n1 of 8 bits are multiplied each other, and the result that will obtain outputs to adder 510, second level tap, be used for the eq_tap_n2 of 8 bits and the filter factor eq_coef_n2 of 8 bits are multiplied each other, and the result that will obtain outputs to adder 510.Centre cap be used for eq_tap_0 with 8 bits 9 bits (＜＜9) that move to left, and the result that will obtain outputs to adder 510.The second tap part 530 comprises: first order tap, be used for the eq_tap_1 of 8 bits and the coefficient eq_coef_1 of 10 bits are multiplied each other, and the result that will obtain outputs to adder 510, second level tap, be used for the eq_tap_2 of 8 bits and the filter factor eq_coef_2 of 9 bits are multiplied each other, and the result that will obtain outputs to adder 510, the tenth grade of tap, be used for the eq_tap_10 of 8 bits and the coefficient eq_coef_10 of 8 bits are multiplied each other, and the result that will obtain outputs to adder 510, etc.For convenience, Fig. 5 has omitted delay time register corresponding to each tap.
The bit number that should be understood that each signal in the present embodiment only is example, and as required, the bit number of each signal also can be worth for other.
Fig. 6 is the schematic realization figure of decision feedback equalization circuit 600 according to an embodiment of the invention.Decision feedback equalization circuit 600 is the feedback equalizer of the embodiment of the invention and the example that decision device is realized equalizing circuit, and comprising: DFE 610, decision device 620, selector 630 and output processing part divide 640.
Output processing part divides 640 to comprise shift operation 641, saturation arithmetic 642, adder 643 and saturation arithmetic 644.Shift operation 641 is with 7 bits of signal right shift (〉 of 23 bits of adder 613 output〉7), obtain the signal of 16 bits.The data limit of 16 bits of saturation arithmetic 642(Sat10) shift operation 641 being exported is the signal of 10 bits.Adder 643 is with signal and the addition of FFE output data of 10 bits of saturation arithmetic 642 outputs.The signal of adder 643 output is through saturation arithmetic 644(Sat6) obtain the data of 6 bits.The data of 6 bits of saturation arithmetic output are as soft decision signal r
kBe input in the decision device 620, adder 621 is with the court verdict d of decision device 620
kWith soft decision signal r
kAddition obtains decision error, and this decision error is through saturation arithmetic 622(Sat4) obtain the decision error e of 4 bits
k
In addition, selector 630 can arrange option (option) for DFF, for example, in physical layer control (PHY Control) stage, can use the symbol (being court verdict) of decision device output as the input of DFE 610, and after entering normal mode of operation, adopt the decode results of TCM decoding output as the input of DFE 610.Before decode results va_tent_sym enters into selector 630, can carry out delay process through a plurality of delay time registers (ND) first.
The bit number that should be understood that each signal in the present embodiment only is example, and as required, the bit number of each signal also can be worth for other.
Fig. 7 is the schematic realization figure of equalizing circuit 700 according to another embodiment of the present invention.Equalizing circuit 700 is examples of the equalizing circuit of the embodiment of the invention.
Equalizing circuit 700 comprises: four road FFE 710, four adders 720, TCM decoder 730, four road DFE 740(for the sake of clarity only show one road DFE among Fig. 7) and the first coefficient updating module 750, the second coefficient updating module 760 and selector 770.
Four road FFE 710(comprise FFE1 to FFE4) input comprise ADC1 to ADC4 with four road ADC 780(respectively) output be connected, and the output of four road FFE 710 is connected with the 1DLA-BMU 731 of TCM decoder 730.Four tunnel adders 720 obtain balanced Output rusults (being soft decision signal) Z respectively with the output of four road EC/NC790, four road FFE 710 and the output addition of four road DFE 740
1(n), Z
2(n), Z
3(n) and Z
4(n).
1DLA-BMU 731 is used for constantly receiving four road soft decision signals at n, and seeks in the one dimension subset with it that immediate symbol obtains corresponding error simultaneously as 64 one dimension decision values.4DBMU 732 is used for generating 32 four-dimensional judgements and corresponding error according to 64 one dimensions judgements that receive from 1DLA-BMU 731 and error.ACSU 733 is used for obtaining the path metric of each state according to the output of 4DBMU 732, and records decoded result and the path metric of each state survivor path.SMU734 is trace unit, after satisfying traceback depth, seeks the corresponding state of minimal path metric, recalls as initial condition take this state, obtains four tunnel preferred decode results va_tent_sym, for example, and the PAM-5 bit signal.Alternatively, SMU may generate different decode results according to different traceback depth, respectively different decode results is sent to respectively selector and as final decode results output.
Four tunnel decode results va_tent_sym of SMU 734 outputs of four selector 770 reception TCM decoders 730 and the court verdict (being the hard decision signal) of decision device output, and select output decode results or court verdict to four road DFE 740 according to control information (for example, 0 or 1) respectively.The first coefficient updating module 750 is upgraded according to the decision error of the decision device output filter factor to FFE 710, and the second coefficient updating module 760 is upgraded according to the decision error of the decision device output filter factor to DFE 740.
Fig. 8 is the structural diagram of data transmission system 800 according to an embodiment of the invention.Data transmission system 800 comprises: the equalizing circuit of local transmitter 895, local receiver 890, blender 810 and above-described embodiment.
In addition, data transmission system 800 can also comprise Echo Canceller 885, be used for the echo signal based on the data estimation transmission line of local transmitter 895 transmissions, and with the echo signal of estimation and the output addition of forward equalizer, so that the echo in the elimination transmission line.
Above-mentioned equalizing circuit can comprise: forward equalizer 830, feedback equalizer 870, selector 880, coefficient updating module 860, TCM decoder 840, decision device 850, adder 835 and adder 855.Data transmission system 800 can also comprise ADC 820, and the analog signal conversion that is used for receiving from a pair of twisted-pair feeder becomes digital signal.The digital signal of ADC 820 outputs is transferred to forward equalizer 830 as the input data.The input data that 830 pairs of forward equalizer receive are carried out filtering, to eliminate leading in time intersymbol interference, i.e. forward direction intersymbol interference.Adder 855 is used for the data addition of the court verdict of decision device 850 outputs and decision device 850 inputs is obtained decision error.Adder 835 is used for the output of forward equalizer 830 and the output addition of feedback equalizer 870 are obtained balanced Output rusults.In addition, can also be used for the output of forward equalizer 830 and the output addition of Echo Canceller 885, be used for eliminating the echo of transmission line.TCM decoder 840 is used for balanced Output rusults is deciphered, with the symbol of decoding through grid coding.In addition, TCM decoder 840 can also receive corresponding to other to the balanced Output rusults of twisted-pair feeder as input.Selector 880 is used for outputing to feedback equalizer 870 according to the decode results of the court verdict of the output of control information selection decision device 850 or 840 outputs of TCM decoder.Feedback equalizer 870 is used for the input data are carried out filtering, in order to estimate the intersymbol interference that lags behind in time in the Double-strand transmission cable, i.e. backward intersymbol interference.The decision error that coefficient updating module 860 is used for obtaining according to adder 855 is upgraded the filter factor of forward equalizer 830, feedback equalizer 870, Echo Canceller 885.
Fig. 9 is the indicative flowchart of a kind of equalization methods according to an embodiment of the invention.
910, with the first input data and feedback signal addition, obtain balanced Output rusults.
920, this equilibrium Output rusults deciphered obtaining decode results.
930, based on the first filter factor this decode results is carried out filtering, obtain this feedback signal, in order to eliminate the intersymbol interference that lags behind in time.
Can eliminate intersymbol interference in the balanced Output rusults by with feedback equalizer decode results being carried out filtering according to embodiments of the invention, owing to no longer eliminate intersymbol interference by with feedback equalizer filtering being carried out in the output of decision device, therefore, can not occur in the feedback equalizer because the error propagation that causes of decision device mistake in judgment, thereby can in balanced Output rusults, mistake not occur.
Alternatively, as another embodiment, the method for Fig. 9 also comprises: based on the second filter factor the second input data are carried out filtering, to eliminate leading in time intersymbol interference and to obtain the first input data; This equilibrium Output rusults is carried out hard decision obtain court verdict; Should the equilibrium Output rusults and this court verdict addition obtain decision error; Upgrade the first filter factor according to this decision error; Upgrade the second filter factor according to this decision error.
In 930, can select this decode results according to control information, and based on the first filter factor this decode results is carried out filtering, wherein this equalization methods also comprises: select this court verdict according to this control information, and based on the first filter factor this court verdict is carried out filtering, obtain this feedback signal, in order to eliminate the intersymbol interference that lags behind in time.
In 930, can in the situation of this control information indication normal mode of operation, select this decode results, and in the situation of this control information indication training mode, select this court verdict.
Alternatively, as another embodiment, the method for Fig. 9 also comprises: based on the first filter factor the data of this feedback equalizer input are carried out filtering and eliminate the intersymbol interference that lags behind in time.
Alternatively, as another embodiment, the method for Fig. 9 also comprises: before based on the first filter factor this decode results being carried out filtering this decode results is carried out delay disposal.
In 920, can carry out Trellis-coded modulation decoding to this equilibrium Output rusults and obtain decode results.
Those of ordinary skills can recognize, unit and the algorithm steps of each example of describing in conjunction with embodiment disclosed herein can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are carried out with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.The professional and technical personnel can specifically should be used for realizing described function with distinct methods to each, but this realization should not thought and exceeds scope of the present invention.
The those skilled in the art can be well understood to, and is the convenience described and succinct, and the specific works process of the system of foregoing description, device and unit can with reference to the corresponding process among the preceding method embodiment, not repeat them here.
In several embodiment that the application provides, should be understood that disclosed system, apparatus and method can realize by another way.For example, device embodiment described above only is schematic, for example, the division of described unit, only be that a kind of logic function is divided, during actual the realization other dividing mode can be arranged, for example a plurality of unit or assembly can in conjunction with or can be integrated into another system, or some features can ignore, or do not carry out.Another point, the shown or coupling each other discussed or direct-coupling or communication connection can be by some interfaces, indirect coupling or the communication connection of device or unit can be electrically, machinery or other form.
Described unit as separating component explanation can or can not be physically to separate also, and the parts that show as the unit can be or can not be physical locations also, namely can be positioned at a place, perhaps also can be distributed on a plurality of network element.Can select according to the actual needs wherein some or all of unit to realize the purpose of present embodiment scheme.
In addition, each functional unit in each embodiment of the present invention can be integrated in the processing unit, also can be that the independent physics of unit exists, and also can be integrated in the unit two or more unit.
If described function realizes with the form of SFU software functional unit and during as independently production marketing or use, can be stored in the computer read/write memory medium.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words or the part of this technical scheme can embody with the form of software product, this computer software product is stored in the storage medium, comprise that some instructions are with so that a computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out all or part of step of the described method of each embodiment of the present invention.And aforesaid storage medium comprises: the various media that can be program code stored such as USB flash disk, portable hard drive, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disc or CD.
The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (15)
1. an equalizing circuit is characterized in that, comprising:
First adder, receiving feedback signals and by the first input data of forward equalizer output is used for will described first inputting data and described feedback signal addition, obtains balanced Output rusults;
Decoder receives described balanced Output rusults, obtains decode results for described balanced Output rusults is deciphered;
Feedback equalizer receives described decode results, is used for based on the first filter factor described decode results being carried out filtering, obtains described feedback signal, and exports described feedback signal to described first adder, in order to eliminate the intersymbol interference that lags behind in time.
2. equalizing circuit according to claim 1 is characterized in that, also comprises:
Described forward equalizer, receive the second input data, be used for based on the second filter factor described the second input data being carried out filtering, input data to eliminate leading in time intersymbol interference and to obtain described first, and export described the first input data to described first adder;
Decision device receives described balanced Output rusults, is used for that described balanced Output rusults is carried out hard decision and obtains court verdict;
Second adder receives described court verdict and described balanced Output rusults, is used for described balanced Output rusults and described court verdict addition are obtained decision error;
The first coefficient updating module receives described decision error, is used for upgrading described the first filter factor according to described decision error, and exports described the first filter factor to described feedback equalizer;
The second coefficient updating module receives described decision error, is used for upgrading described the second filter factor according to described decision error, and exports described the second filter factor to described forward equalizer.
3. equalizing circuit according to claim 2 is characterized in that, also comprises:
Selector, receive described court verdict and described decode results, be used for selecting described decode results or described court verdict according to control information, and the described decode results that will select or described court verdict output to described feedback equalizer as described feedback signal.
4. equalizing circuit according to claim 3, it is characterized in that, described selector selects described decode results to output to described feedback equalizer under the normal mode of operation of described equalizing circuit, selects described court verdict to output to described feedback equalizer under the training mode before the normal operation of described equalizing circuit.
5. each described equalizing circuit in 4 according to claim 2 is characterized in that described forward equalizer also is used for based on described the second filter factor described the second input data being carried out filtering and eliminates the intersymbol interference that lags behind in time.
6. each described equalizing circuit in 5 according to claim 1 is characterized in that, is connected with a plurality of delay time registers between described decoder and the described feedback equalizer.
7. each described equalizing circuit in 6 according to claim 1 is characterized in that described decoder is the Trellis-coded modulation decoder.
8. a data transmission system is characterized in that, comprising:
Local transmitter is used for sending data to remote receiver;
Local receiver is used for from long-range transmitter receive data;
Blender is connected between described local transmitter and the described data transmission system transmission line, and is connected between described local receiver and the described transmission line;
Such as each the described equalizing circuit in the claim 1 to 7, be connected between described local receiver and the described blender, for the intersymbol interference of the data of eliminating described local receiver reception.
9. an equalization methods is characterized in that, comprising:
With the first input data and feedback signal addition, obtain balanced Output rusults;
Described balanced Output rusults deciphered obtain decode results;
Based on the first filter factor described decode results is carried out filtering, obtain described feedback signal, in order to eliminate the intersymbol interference that lags behind in time.
10. equalization methods according to claim 9 is characterized in that, also comprises:
Based on the second filter factor the second input data are carried out filtering, to eliminate leading in time intersymbol interference and to obtain described the first input data;
Described balanced Output rusults is carried out hard decision obtain court verdict;
Described balanced Output rusults and described court verdict addition are obtained decision error;
Upgrade described the first filter factor according to described decision error;
Upgrade described the second filter factor according to described decision error.
11. equalization methods according to claim 10 is characterized in that, describedly based on the first filter factor described decode results is carried out filtering, comprising:
Select described decode results according to control information, and based on described the first filter factor described decode results carried out filtering,
Wherein this equalization methods also comprises:
Select described court verdict according to described control information, and based on described the first filter factor described court verdict is carried out filtering, obtain described feedback signal, in order to eliminate the intersymbol interference that lags behind in time.
12. equalization methods according to claim 11 is characterized in that, describedly selects described decode results according to control information, comprising:
In the situation of described control information indication normal mode of operation, select described decode results,
Wherein saidly select described court verdict according to described control information, comprising:
In the situation of described control information indication training mode, select described court verdict.
13. each the described equalization methods in 12 is characterized in that according to claim 10, also comprises:
Based on described the first filter factor the data of described feedback equalizer input are carried out filtering and eliminate the intersymbol interference that lags behind in time.
14. each the described equalization methods in 13 is characterized in that according to claim 9, also comprises: before based on described the first filter factor described decode results being carried out filtering described decode results is carried out delay disposal.
15. each described equalization methods in 14 according to claim 9 is characterized in that described described balanced Output rusults is deciphered obtains decode results, comprising:
Described balanced Output rusults is carried out Trellis-coded modulation decoding obtain decode results.
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