CN102882817B - Equalizing circuit, data transmission system and equalization methods - Google Patents
Equalizing circuit, data transmission system and equalization methods Download PDFInfo
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Abstract
The invention provides a kind of equalizing circuit, data transmission system and equalization methods.Equalizing circuit includes：First adder receives the first input data of feedback signal and the output of forward direction equalizing circuit, for the first input data to be added with the feedback signal, is equalized output result；Decoder receives the equalization output result, obtains decoding result for entering the equalization output result row decoding；Feedback equalizer receives the decoding result, for being filtered based on the first filter factor to the decoding result, obtains the feedback signal, and exports the feedback signal to first adder, to eliminate intersymbol interference delayed in time.Intersymbol interference is eliminated due to being no longer filtered by using feedback equalizer to the output of decision device, therefore, it is possible to avoid occurring error propagation in balanced device.
Description
The present invention relates to the communications field, more particularly, to a kind of equalizing circuit, data transmission system and equalization methods.
Background technology
Gigabit Ethernet physical layer（Gigabit Ethernet Physical Layer, GEPHY）For power port Ethernet thing
Manage layer.Hereinafter, GEPHY refers in particular to the physical layer subsystem being implemented in power port ethernet communication chip（Module）, in five classes or
Surpass five class unshielded twisted pairs（Unshielded Twisted Pair, UTP）It is upper to complete the communication of both sides, and need to support
1000BASE-T/100BASE-TX/10BASE-T agreements.Herein, it is logical more particularly under 1000BASE-T consensus standards
Letter.
Required according to ieee specification, 1000Base-T systems are passed on 4 pairs of unshielded twisted pairs with 125MBaud modulation rates
4D-PAM5 signals are sent, 1Gb/s full-duplex data transmission can be reached.4D-PAM5 signals are improving the same of the availability of frequency spectrum
When, its level hypotelorism to 100 m ethernet MLT3 encode 1/2.In 1000Base-T, it can be adjusted using grid coding
System（Trellis Coded Modulation, TCM) make up this loss.Meanwhile, the length of cable supported will can reach 100
Rice, cable transmission speed is as follows：（1）125M symbols/second, 2b bit/symbols；（2）Bit rate on each pair line is 250Mb/s.
GEPHY systems use 4D-PAM5 signals, bit error rate（Bit Error Rate, BER）With signal to noise ratio（Signal Noise
Ratio, SNR）Increase can drastically decline, thus receiver need fully eliminate interference and noise, increase SNR it is smaller to obtain
The bit error rate.
For GEPHY systems, the key factor of influence BER indexs is the intersymbol interference in channel（Inter-symbol
Interference, ISI）And noise.The data that receiver is received are due to the influence of the interference such as attenuated and noise, decoding
Obtained data have certain bit error rate.Intersymbol interference includes backward intersymbol interference（post-cursor ISI）With forward direction code
Between disturb（pre-cursor ISI）.Forward direction intersymbol interference refers to the time-domain signal more late than this cycle and current sign is surpassed in time
Preceding time interference, and backward intersymbol interference is the time-domain signal more early than this cycle time delayed in time to current sign
Interference.
An important means for overcoming intersymbol interference is that signal distortion caused by channel is compensated in receiving terminal, that is, is entered
Row channel equalization.Generally use forward equalizer（Feed Forward Equalizer, FFE）To intersymbol interference before eliminating, and
Using the feedback equalizer based on hard decision（Decision Feed Back Equalizer, DFE）Eliminate backward intersymbol interference.
For example, by FFE to from mould data converter（ADC）The data of reception are filtered, preceding to intersymbol interference to eliminate, and
To FFE output datas.FFE output datas are added with the DFE feedback signals exported, to eliminate backward intersymbol interference, and are obtained
Balanced output signal, i.e. soft decision signal rk.Balanced output signal rkBy decision device or limiter（Slicer）Hard decision,
Obtain court verdict, i.e. hard decision signal dk, and balanced output signal is added with court verdict, decision error e is obtained, its
Middle decision error e is used for FFE and DFE factor updating operation.DFE is to court verdict dkIt is filtered, to eliminate backward intersymbol
Interference, and obtain above-mentioned feedback signal.
However, when decision device carries out hard decision, if there is mistake, the wrong judgement of decision device output in hard decision
As a result dk can keep a period of time in DFE delay time register so that during this period, DFE output is inaccurate, that is, deposits
In error propagation（error propagation）, in turn result in equalizer output signal rk and mistake occur.
The content of the invention
The embodiment provides a kind of equalizing circuit, data transmission system and equalization methods, equilibrium can be avoided
Occurs error propagation in device.
First aspect there is provided a kind of equalizing circuit, including：First adder, receives feedback signal and balanced by forward direction
First input data of device output, for the first input data to be added with the feedback signal, is equalized output result；Decoding
Device, receives the equalization output result, obtains decoding result for entering the equalization output result row decoding；Feedback equalizer, connects
The decoding result is received, for being filtered based on the first filter factor to the decoding result, the feedback signal is obtained, and to
One adder exports the feedback signal, to eliminate intersymbol interference delayed in time.
In the first possible implementation, above-mentioned equalizing circuit also includes：Forward equalizer, receives second and inputs number
According to for being filtered based on the second filter factor to the second input data, to eliminate intersymbol interference advanced in time simultaneously
The first input data is obtained, and the first input data is exported to first adder；Decision device, receives the equalization output result,
Court verdict is obtained for carrying out hard decision to the equalization output result；Second adder, receives the court verdict and the equilibrium
Output result, decision error is obtained for the equalization output result to be added with the court verdict；First coefficient updating module, connects
The decision error is received, for updating the first filter factor according to the decision error, and is filtered to feedback equalizer output first
Wave system number；Second coefficient updating module, receives the decision error, for updating the second filter factor according to the decision error, and
And export the second filter factor to the forward equalizer.
With reference to the first possible implementation of first aspect, in second of possible implementation, above-mentioned equilibrium
Circuit also includes：Selector, receives the court verdict and the decoding result, for according to control information select the decoding result or
Person's court verdict, and the decoding result of selection or the court verdict are output to the feedback equalizer as the feedback
Signal.
With reference to second of possible implementation of first aspect, in the third possible implementation, the selector
Select the decoding result to be output to the feedback equalizer under the normal mode of operation of the equalizing circuit, in the equalizing circuit just
Often the court verdict is selected to be output to the feedback equalizer under the training mode before work.
With reference in a kind of any of the above described possible implementation, in the 4th kind of possible implementation, this is preceding to equilibrium
Device is additionally operable to carry out the filtering to the second input data to eliminate intersymbol interference delayed in time based on the second filter factor.
With reference to a kind of any of the above described possible implementation, in the 5th kind of possible implementation, the decoder is with being somebody's turn to do
Multiple delay time registers are connected between feedback equalizer.
With reference to a kind of any of the above described possible implementation, in the 6th kind of possible implementation, the decoder is net
Trellis coded modulation decoder.
Second aspect there is provided a kind of data transmission system, including：Local transmitter, for being sent to remote receiver
Data；Local receiver, for receiving data from long-range transmitter；Blender, is connected to the local transmitter and is passed with the data
Between defeated system communications line, and it is connected between the local receiver and the transmission line；A kind of any of the above described equalizing circuit, even
It is connected between the local receiver and the blender, the intersymbol interference in data for eliminating local receiver reception.
The third aspect there is provided a kind of equalization methods, including：First input data is added with feedback signal, obtained
Weigh output result；Enter row decoding to the equalization output result to obtain decoding result；Based on the first filter factor to the decoding result
It is filtered, obtains the feedback signal, to eliminate intersymbol interference delayed in time.
In the first possible implementation, the equalization methods also include：Inputted based on the second filter factor to second
Data are filtered, to eliminate intersymbol interference advanced in time and obtain the first input data；To the equalization output result
Carry out hard decision and obtain court verdict；The equalization output result is added with the court verdict and obtains decision error；Sentenced according to this
The certainly filter factor of error update first；Second filter factor is updated according to the decision error.
It is above-mentioned to be based in second of possible implementation with reference to the first possible implementation of the third aspect
First filter factor is filtered to the decoding result, is also included：The decoding result is selected according to control information, and based on the
One filter factor is filtered to the decoding result, and wherein the equalization methods also include：The judgement is selected according to the control information
As a result, and based on the first filter factor the court verdict is filtered, the feedback signal is obtained, to eliminate in time
Delayed intersymbol interference.
With reference to second of possible implementation of the third aspect, in the third possible implementation, above-mentioned basis
Control information selects the decoding result, including：In the case where the control information indicates normal mode of operation, the decoding knot is selected
Really, wherein above-mentioned select the court verdict according to the control information, including：The situation of training mode is indicated in the control information
Under, select the court verdict.
With reference to a kind of any of the above described possible implementation, in the 4th kind of possible implementation, above-mentioned equalization methods
Also include：The data inputted based on the first filter factor to the feedback equalizer are filtered to eliminate code delayed in time
Between disturb.
With reference to a kind of any of the above described possible implementation, in the 5th kind of possible implementation, above-mentioned equalization methods
Also include：Delay disposal is carried out to the decoding result before being filtered based on the first filter factor to the decoding result.
With reference to a kind of any of the above described possible implementation, in the 6th kind of possible implementation, this pair equilibrium is defeated
Go out result enter row decoding obtain decode result, including：Trellis-coded modulation is carried out to the equalization output result to be decoded
As a result.
The technical program can be filtered to eliminate equalization output result by using feedback equalizer to decoding result
In intersymbol interference, eliminate intersymbol interference due to being no longer filtered by using feedback equalizer to the output of decision device,
Therefore, be not in due to the error propagation that decision device mistake in judgment is caused, so that will not be in equilibrium output in feedback equalizer
As a result occurs mistake in.
Brief description of the drawings
Technical scheme in order to illustrate more clearly the embodiments of the present invention, below will be to that will make needed for the embodiment of the present invention
Accompanying drawing is briefly described, it should be apparent that, drawings described below is only some embodiments of the present invention, for
For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is a kind of schematic block diagram of equalizing circuit according to an embodiment of the invention.
Fig. 2 is a kind of schematic block diagram of equalizing circuit according to another embodiment of the present invention.
Fig. 3 is a kind of schematic block diagram of equalizing circuit according to still another embodiment of the invention
Fig. 4 is the schematic block diagram of forward equalizer according to an embodiment of the invention.
Fig. 5 is the schematic realization figure of forward equalizer according to another embodiment of the present invention.
Fig. 6 is the schematic realization figure of decision feedback equalization circuit according to an embodiment of the invention.
Fig. 7 is the schematic realization figure of equalizing circuit according to another embodiment of the present invention.
Fig. 8 is the structural diagram of data transmission system according to an embodiment of the invention.
Fig. 9 is a kind of indicative flowchart of equalization methods according to an embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is a part of embodiment of the invention, rather than whole embodiments.Based on this hair
Embodiment in bright, the every other implementation that those of ordinary skill in the art are obtained under the premise of creative work is not made
Example, belongs to the scope of protection of the invention.
, can be by feedback equalization and Trellis-coded modulation for error propagation phenomenon present in above-mentioned equalizing circuit
（Trellis Coded Modulation, TCM）Decoding, which combines, avoids this phenomenon.Specifically, it is possible to use feedback
Equilibrium eliminates the backward intersymbol interference of a part, for example, only need except the later backward intersymbol interference in the second level and the second level, and
The backward intersymbol interference of the first order is eliminated in TCM decodings.The program can avoid error propagation phenomenon, still, due to the program
8 status signals that the output of survivor path unit is decoded to TCM using feedback equalization are filtered to eliminate intersymbol interference, therefore,
Higher to processing requirement, implementation complexity is higher.For example, the selection of survival signal must be completed within the monocycle, for TCM
The timing of decoding loop（timing）It is required that harsh.Further, since needing all to carry out 8 status signals feedback equalization computing, need
Want more hardware so that whole system area and power consumption are larger, influence whole machine cost.
Fig. 1 is a kind of schematic block diagram of equalizing circuit 100 according to an embodiment of the invention.Equalizing circuit 100
Including：Feedback equalizer 130, first adder 140 and decoder 120.
First adder 140 receives the first input data of feedback signal and forward equalizer output, for defeated by first
Enter data to be added with the feedback signal, be equalized output result；Decoder 120 receives the equalization output result, for this
Equalization output result enters row decoding and obtains decoding result；Feedback equalizer 130 receives the decoding result, for based on the first filtering
Coefficient is filtered to the decoding result, obtains the feedback signal, and exports the feedback signal to first adder 140, with
Just intersymbol interference delayed in time is eliminated.
Embodiments in accordance with the present invention, feedback equalizer 130 can be preset equalizer or adaptive equalization
Device, i.e., above-mentioned filter factor can be set in advance or real-time update.Preset equalizer can be in transmission number
According to before, filter factor is determined by test pulse signal, and sef-adapting filter can utilize intersymbol during data are transmitted
Interference information automatically adjusts filter factor.Embodiments in accordance with the present invention are not limited to this, for example, can be by adaptive equalization
Device is used in mixed way with preset equalizer, in training mode, and the coefficient of balanced device is set according to training sequence, and normal
Under mode of operation, the characteristic of channel being continually changing, adjust automatically filter factor are tracked by adaptive algorithm in a balanced way.Feedback is equal
Weighing apparatus 130 can be by nonlinear filter（For example, the wave filter based on decision feedback equalization）To realize.According to the reality of the present invention
Example is applied with the wave filter based on decision feedback equalization to realize equalizing circuit（That is decision feedback equalization circuit）Exemplified by illustrate.
Embodiments in accordance with the present invention, in the receiving terminal of data transmission system, equalizing circuit 100 can receive ADC transmissions
Data.Equalizing circuit 100 can use forward equalizer and feedback equalizer to eliminate intersymbol interference, it is of course also possible to only make
Intersymbol interference is eliminated with feedback equalizer.Specifically, adder 140 can export forward equalizer data or
The data of ADC outputs are added with the feedback signal that feedback equalizer 130 is exported, and are equalized output result, and equilibrium is defeated
Go out result and be output to decoder 120, decoder 120 can enter row decoding to the data of input, obtain decoding result.Feedback equalization
Device 130 is filtered based on the decoding result that filter factor is exported to decoder 120, to estimate that intersymbol delayed in time is done
Disturb, obtain above-mentioned feedback signal, and above-mentioned feedback signal is output to adder 140.
Equalizing circuit can programmable gate array at the scene according to an embodiment of the invention（Field Programmable
Gate Array, FPGA）Realized on platform, embodiments in accordance with the present invention are not limited to this, for example, it is also possible in data signal
Processing（Digital Signal Processing, DSP）Realized on platform.
Embodiments in accordance with the present invention can be filtered to eliminate equilibrium by using feedback equalizer to decoding result
Intersymbol interference in output result, blanking code is carried out due to being no longer filtered by using feedback equalizer to the output of decision device
Between disturb, therefore, in feedback equalizer be not in due to the error propagation that decision device mistake in judgment is caused, so that will not be equal
There is mistake in weighing apparatus output result.
In addition, being filtered to eliminate intersymbol interference with above-mentioned 8 status signals for decoding TCM the output of survivor path unit
Technical scheme compare, implementation complexity is relatively low, and because the hardware used is less, therefore, the power consumption and area of system
It is smaller.
Alternatively, as another embodiment, multiple delay deposits are connected between decoder 120 and feedback equalizer 130
Device.
In order that decoder 120 and feedback equalizer 130 can co-ordination, decoder 120 can exported
Decoding result is input to before feedback equalizer 130, is carried out delay process to decoding result, introduced during logic realization for being adjusted
Path delay.
Embodiments in accordance with the present invention, decoder 120 is Trellis-coded modulation decoder.For example, the Trellis-coded modulation
Decoder is viterbi decoder.
Fig. 2 is a kind of schematic block diagram of equalizing circuit 200 according to another embodiment of the present invention.Equalizing circuit 200
Including：Feedback equalizer 230, first adder 240 and decoder 220, feedback equalizer 130 respectively with Fig. 1, the first addition
Device 140 is similar with decoder 120, and detailed description is suitably omitted herein.
Embodiments in accordance with the present invention, equalizing circuit 200 also includes：Forward equalizer 210, decision device 250, the second addition
Device 270, the first coefficient updating module 260 and the second coefficient updating module 280.
Forward equalizer 210 receives the second input data, for being carried out based on the second filter factor to the second input data
Filtering, to eliminate intersymbol interference advanced in time and obtain the first input data, and exports first to first adder
Input data.Decision device 250 receives the equalization output result, and judgement knot is obtained for carrying out hard decision to the equalization output result
Really.Second adder 270 receives the court verdict and the equalization output result, for by the equalization output result and the judgement knot
Fruit is added and obtains decision error.First coefficient updating module 260, receives the decision error, for being updated according to the decision error
First filter factor, and export the first filter factor to the feedback equalizer.Second coefficient updating module 280, receives this and sentences
Certainly error, for updating the second filter factor according to the decision error, and exports the second filter factor to the forward equalizer.
Embodiments in accordance with the present invention, forward equalizer 110 can be preset equalizer or adaptive equalization
Device, i.e., above-mentioned filter factor can be set in advance or real-time update.Preset equalizer can be in transmission number
According to before, filter factor is determined by test pulse signal, and sef-adapting filter can utilize intersymbol during data are transmitted
Interference information automatically adjusts filter factor.Embodiments in accordance with the present invention are not limited to this, for example, can be by adaptive equalization
Device is used in mixed way with preset equalizer, in training mode, and the coefficient of balanced device is set according to training sequence, and normal
Under mode of operation, the characteristic of channel being continually changing, adjust automatically filter factor are tracked by adaptive algorithm in a balanced way.Before above-mentioned
Can be by linear filter to balanced device（For example, transversal filter）To realize,
Embodiments in accordance with the present invention, in receiving terminal, second input of the forward equalizer 210 based on filter factor to reception
Data are filtered, and to eliminate intersymbol interference advanced in time, i.e. the transmission characteristic to data transmission system is corrected
Or compensation, so as to reduce the bit error rate.The feedback signal that the output data of forward equalizer 210 is exported with feedback equalizer 130 exists
It is added in adder 140, can further eliminates intersymbol interference delayed in time, be equalized output result.For example, working as
, can be using the first coefficient updating module 260 and the when forward equalizer 210 and feedback equalizer 230 are sef-adapting filter
Two coefficient updating modules 280 carry out real-time update to the first filter factor and the second filter factor respectively.Certain forward equalizer
210 and feedback equalizer 230 same coefficient updating module can also be used to be filtered filter factor.
Alternatively, as another embodiment, forward equalizer 210 is additionally operable to based on the second filter factor to the second input number
Intersymbol interference delayed in time is eliminated according to being filtered.
Because the decoding processing of TCM decoders can produce delay, therefore, in the decoding result exported based on TCM decoders
When being filtered, feedback equalizer is possible to that all intersymbol interferences delayed in time can not be eliminated.Translated to make up TCM
The delay that code device is produced, can eliminate part intersymbol interference delayed in time in forward equalizer.
Fig. 3 is a kind of schematic block diagram of equalizing circuit 300 according to still another embodiment of the invention.Equalizing circuit 300
Including：Forward equalizer 310, feedback equalizer 330, first adder 340, decoder 320, decision device 350, second adder
370 and coefficient updating module 360, respectively with Fig. 2 forward equalizer 210, feedback equalizer 230, first adder 240, translate
Code device 220, decision device 250, second adder 270 and coefficient updating module 260, suitably omit detailed description herein.
Embodiments in accordance with the present invention, equalizing circuit 300 also includes：Selector 390.
Embodiments in accordance with the present invention, selector 390 receives above-mentioned court verdict and above-mentioned decoding result, for according to control
Information processed selects the decoding result or the court verdict, and the decoding result of selection or the court verdict are output to
The feedback equalizer is used as above-mentioned feedback signal.
Embodiments in accordance with the present invention, selector 390 is used for choosing whether the decoding result of decoder 320 being output to instead
Present balanced device 330.So, can be as needed or in the case where meeting default condition just by the decoding of decoder 320
As a result it is output to feedback equalizer 330.For example, in the case where selector 390 is only inputted all the way, the control of selector 390
Information represents the input of selector 390 as output that the control information of selector 390 represents not export for 0 for 1.Alternatively,
The control information of selector 390 can be made up of multiple bits, so as to select one in multichannel input according to the value of bit
Road is inputted as output, for example, control information represents the input all the way for selecting selector 390 as output for 0, control information is
1 represents another road input of selection selector 390 as output.
Embodiments in accordance with the present invention, selector 390 selects the decoding knot under the normal mode of operation of equalizing circuit 300
Fruit is output to feedback equalizer 330, and court verdict output is selected under the training mode before the normal work of the equalizing circuit 300
To feedback equalizer 330.
There are erroneous transmissions due to existing in training mode in feedback equalizer and normal data transfer can't be produced
Raw influence, moreover, in training mode, transmission is PAM3 signals, and the PAM3 signals can be encoded without TCM, therefore,
Court verdict of the feedback equalizer based on decision device, which is filtered, under training mode can shorten the time of training, so as to improve
The efficiency of system.
Fig. 4 is the schematic block diagram of forward equalizer 400 according to an embodiment of the invention.Forward equalizer 400
It can be realized by transversal filter.
Forward equalizer 400 can include the first tap portions 411, the tap portions 413 of centre cap 412 and second and add
Musical instruments used in a Buddhist or Taoist mass 414.First tap portions 411, the tap portions 413 of centre cap 412 and second are connected in series.
First tap portions 411 include filter factor C-1And C-2With corresponding delay time register, for eliminate in time
Influence of the advanced intersymbol interference to data transmission system, that is, eliminate the time-domain signal in evening in this cycle to current sign in time
Advanced time interference.Centre cap 412 includes filter factor C0With corresponding delay time register, for eliminating current sign
Intersymbol interference（Current cursor ISI）.Second tap portions 413 include C1、C2、…、CNWith corresponding delay time register,
For eliminating influence of the intersymbol interference delayed in time to data transmission system, that is, the time domain more early than this cycle letter after eliminating
The interference of number time delayed in time to current sign.
First tap portions 411 can receive the data of the outputs of ADC 420 as FFE input datas（ffe_data_in）,
A few delay time register 440 is may also connect between ADC 420 and FFE 410.Above-mentioned data by FFE each
After tap, the output result of each tap is added in adder 414, obtains FFE output datas（ffe_data_out）.
Second tap portions 413 can be least partially overlapped with the tap of feedback equalizer, to lift data transmission system
Signal to noise ratio.
Coefficient updating module 430 can use such as lowest mean square（Least mean square, LMS）Coefficient update is calculated
Method, the coefficient update formula based on LMS can be Ck+1 i=Ck i+ α * sli_e*sgn (ec_data_in), wherein, Ck iRepresent kth
The i-th level number at moment, Ck+1 iThe i-th level number at the moment of kth+1 is represented, α is coefficient update step-length；Sgn, which is represented, takes symbol to grasp
Make, ec_data_in is the input data of balanced device, and sli_e is decision error.
Fig. 5 is the schematic realization figure of forward equalizer 500 according to another embodiment of the present invention.Forward equalizer
500 be the example for the forward equalizer 400 for realizing Fig. 4.
Forward equalizer 500 includes the first tap portions 520, centre cap 530, the second tap portions 530, adder
510 and output processing unit 550.510 pairs of first tap portions 520, centre cap 530, the second tap portions 530 and adder
Should be in Fig. 4 the first tap portions 411, the tap portions 413 of centre cap 412 and second and adder 414.
First tap portions 520 include：First order tap, for by the eq_tap_n1 of 8 bits and 8 bits filtering system
Number eq_coef_n1 are multiplied, and obtained result is output into adder 510, second level tap, for by the eq_ of 8 bits
Tap_n2 is multiplied with the filter factor eq_coef_n2 of 8 bits, and obtained result is output into adder 510.Centre cap,
For the eq_tap_0 of 8 bits to be moved to left into 9 bits（<<9）, and obtained result is output to adder 510.Second tap
Part 530 includes：First order tap, for the eq_tap_1 of 8 bits to be multiplied with the coefficient eq_coef_1 of 10 bits, and will
Obtained result is output to adder 510, second level tap, for by the eq_tap_2 of 8 bits and 9 bits filter factor
Eq_coef_2 is multiplied, and obtained result is output into adder 510 ..., the tenth grade of tap, for by the eq_ of 8 bits
Tap_10 is multiplied with the coefficient eq_coef_10 of 8 bits, and obtained result is output into adder 510, etc..In order to describe
Convenient, Fig. 5 eliminates the corresponding delay time register of each tap.
Adder 510 can be by the results added of above-mentioned tap output, and exports the signal of 23 bits.Alternatively, return
Sound arrester and the signal of noise eliminator generation（ec/nc）Can also be with above-mentioned tap results added.
Processing unit 550 is exported, the signal for 23 bits that adder is exported moves to right 7 bits by shift right operation 551（>>
7）, the signal of 16 bits is obtained, and saturation arithmetic is carried out to the signal of 16 bits（Sat10）552 obtain the signal of 10 bits,
Finally 3D computings are carried out again（I.e. 3 delays clapped）553 obtain the FFE output datas of 10 bits.
It should be understood that the bit number of the signal of each in the present embodiment is only example, and as needed, the bit number of each signal
Can also be other values.
Fig. 6 is the schematic realization figure of decision feedback equalization circuit 600 according to an embodiment of the invention.Judgement is anti-
It is that the feedback equalizer and decision device of the embodiment of the present invention realize an example of equalizing circuit to present equalizing circuit 600, including：
DFE 610, decision device 620, selector 630 and output processing part divide 640.
DFE 610 includes：Multiple delay time registers 611（For example, 30 delay time registers）；With multiple delay time registers
611 corresponding multiple multipliers 612, for the dfe_tap_1 for respectively exporting multiple delay time registers 611（8 bits）、
dfe_tap_2（8 bits）、…、dfe_tap_30（8 bits）With corresponding filter factor eq_coef_1（9 bits）、eq_
coef_2（10 bits）、…、eq_coef_30（8 bits）It is multiplied, and obtained product is output to adder 613, wherein
One delay time register and a multiplier constitute a tap.The output result of each tap is added and obtained by adder 613
The signal of 23 bits.
Output processing part point 640 includes shift operation 641, saturation arithmetic 642, adder 643 and saturation arithmetic 644.Move
7 bits of signal right shift for 23 bits that bit arithmetic 641 exports adder 613（>>7）, obtain the signal of 16 bits.
Saturation arithmetic 642（Sat10）The data for 16 bits that shift operation 641 is exported are limited to the signal of 10 bits.Adder 643
The signal for 10 bits that saturation arithmetic 642 is exported is added with FFE output datas.The signal that adder 643 is exported is through supersaturation
Computing 644（Sat6）Obtain the data of 6 bits.The data of 6 bits of saturation arithmetic output are used as soft decision signal rkIt is input to
In decision device 620, adder 621 is by the court verdict d of decision device 620kWith soft decision signal rkAddition obtains decision error, should
Decision error passes through saturation arithmetic 622（Sat4）Obtain the decision error e of 4 bitsk。
Selector 630 receives the court verdict d that decision device 620 is exportedkThe decoding result va_tent_ exported with decoder
sym.And when control information sym_type_sel is 0, select court verdict dkFeedback equalizer 610 is output to, works as control
When information sym_type_sel processed is 0, decoding result va_tent_sym is output to feedback equalizer 610, that is, is output to feedback
The delay time register 611 of balanced device 610.
In addition, selector 630 can set option for DFF（option）, for example, in physical layer control
System（PHY Control）Stage, the symbol that decision device can be used to export（That is court verdict）As DFE 610 input, and
Into after normal mode of operation, input of the decoding result as DFE 610 of output is decoded using TCM.In decoding result va_
Tent_sym is entered before selector 630, can first pass through multiple delay time registers（ND）Carry out delay process.
It should be understood that the bit number of the signal of each in the present embodiment is only example, and as needed, the bit number of each signal
Can also be other values.
Fig. 7 is the schematic realization figure of equalizing circuit 700 according to another embodiment of the present invention.Equalizing circuit 700 is
One example of the equalizing circuit of the embodiment of the present invention.
Equalizing circuit 700 includes：Four road FFE 710, four adders 720, TCM decoders 730, a four road DFE
740（For the sake of clarity, DFE all the way is illustrate only in Fig. 7）With the first coefficient updating module 750, the second coefficient updating module
760 and selector 770.
TCM decoders 730 include：One-dimensional advanced branch metric unit 731（1D Look Ahead Branch Metric
Unit, 1DLA-BMU）, four-dimensional branch metric unit（4D Branch Metric Unit, 4DBMU）732nd, add-compare-choosing
Select unit 733（Add-Compare-Select Unit,ACSU）And survivor memory unit（Survive path Memory
Unit, SMU）734.
Four road FFE 710（Including FFE1 to FFE4）Input respectively with four road ADC 780（Including ADC1 to ADC4）
Output end be connected, and four road FFE 710 output end is connected with the 1DLA-BMU 731 of TCM decoders 730.Four tunnels
Four road EC/NC790, four road FFE 710 output and four road DFE 740 output are added by adder 720 respectively, are obtained
Weigh output result（That is soft decision signal）Z1(n)、Z2(n)、Z3And Z (n)4(n)。
1DLA-BMU 731 is used in the road soft decision signal of n receptions four, and is found therewith most in one-dimensional subset
Close symbol is as 64 one-dimensional decision values, while obtaining corresponding error.4DBMU 732 is used for basis from 1DLA-BMU
The one-dimensional judgement of 731 64 received and error generate 32 four-dimensional judgements and corresponding error.ACSU 733 is used for according to 4DBMU
732 output obtains the path metric of each state, and records the decoded result and path metric of each state survivor path.
SMU734 is trace unit, after traceback depth is met, find minimal path metric corresponding to state, using this state as
Original state is recalled, and obtains four tunnels and preferably decodes result va_tent_sym, for example, PAM-5 bit signals.Alternatively,
SMU may generate different decoding results according to different traceback depths, and different decoding results is sent respectively into choosing respectively
Select device and exported as final decoding result.
Four tunnels decoding result va_tent_sym that the SMU 734 that four selectors 770 receive TCM decoders 730 is exported and
The court verdict of decision device output（That is hard decision signal）, and respectively according to control information（For example, 0 or 1）Selection output is translated
Code result or court verdict are to four road DFE 740.The decision error pair that first coefficient updating module 750 is exported according to decision device
FFE 710 filter factor is updated, and the decision error that the second coefficient updating module 760 is exported according to decision device is to DFE
740 filter factor is updated.
Fig. 8 is the structural diagram of data transmission system 800 according to an embodiment of the invention.Data transmission system
800, including：Local transmitter 895, local receiver 890, the equalizing circuit of blender 810 and above-described embodiment.
Local transmitter 895 sends data to remote receiver；Local receiver 890 receives data from long-range transmitter；
Blender 810 is connected between the local transmitter 895 and the transmission line of the data transmission system, and is connected to this and is locally connect
Between receipts machine 890 and the transmission line；Any one of above-described embodiment equalizing circuit is connected to the local receiver and 890 should
Between blender 810, the intersymbol interference in data for eliminating the local receiver 890 reception.
Data transmission system 800 can support the communication under 1000BASE-T consensus standards, and data transmission system
Transmission line can be gigabit Ethernet cable.Embodiments of the invention are not limited to this, for example, data transmission system 800 also may be used
To support the agreements such as 100BASE-TX or 10base-T.This emitter/receiver 890 and this emitter/receiver 895 can be implemented as transmitting-receiving
Machine, or independent equipment.Above-mentioned equalizing circuit can be independent circuit, can also be integrated in local receiver
Realized in 890.Above-mentioned transmission line can be twisted-pair feeder, for example, five classes or surpassing five class UTP.
In addition, data transmission system 800 can also include Echo Canceller 885, for being sent based on local transmitter 895
Data estimation transmission line in echo signal, and the echo signal of estimation is added with the output of forward equalizer, so as to
Eliminate the echo in transmission line.
Above-mentioned equalizing circuit can include：Forward equalizer 830, feedback equalizer 870, selector 880, coefficient update mould
Block 860, TCM decoders 840, decision device 850, adder 835 and adder 855.Data transmission system 800 can also include
ADC 820, for the analog signal received from a pair of twisted-pair feeders is converted into data signal.The data signal that ADC 820 is exported
Forward equalizer 830 is transferred to as input data.830 pairs of input datas received of forward equalizer are filtered, with
Eliminate intersymbol interference advanced in time, i.e., it is preceding to intersymbol interference.Adder 855 is used for the judgement for exporting decision device 850
As a result the data inputted with decision device 850, which are added, obtains decision error.Adder 835 is used for the output of forward equalizer 830
Output with feedback equalizer 870, which is added, is equalized output result.Furthermore it is also possible to for by the defeated of forward equalizer 830
Go out and be added with the output of Echo Canceller 885, for eliminating the echo in transmission line.TCM decoders 840 are used for equilibrium output
As a result row decoding is entered, to decode the symbol through grid coding.In addition, TCM decoders 840 can also be received corresponding to other to double
The equalization output result of twisted wire is used as input.Selector 880 is used for the judgement that the output of decision device 850 is selected according to control information
As a result or TCM decoders 840 export decoding result be output to feedback equalizer 870.Feedback equalizer 870 is used for input
Data are filtered, to estimate the intersymbol interference delayed in time in Double-strand transmission cable, i.e., backward intersymbol interference.
Coefficient updating module 860 is used to update forward equalizer 830, feedback equalizer according to the decision error that adder 855 is obtained
870th, the filter factor of Echo Canceller 885.
Fig. 9 is a kind of indicative flowchart of equalization methods according to an embodiment of the invention.
910, the first input data is added with feedback signal, output result is equalized.
920, row decoding is entered to the equalization output result and obtains decoding result.
930, the decoding result is filtered based on the first filter factor, the feedback signal is obtained, so as to eliminate when
Between upper delayed intersymbol interference.
Embodiments in accordance with the present invention can be filtered to eliminate equilibrium by using feedback equalizer to decoding result
Intersymbol interference in output result, blanking code is carried out due to being no longer filtered by using feedback equalizer to the output of decision device
Between disturb, therefore, in feedback equalizer be not in due to the error propagation that decision device mistake in judgment is caused, so that will not be equal
There is mistake in weighing apparatus output result.
Alternatively, as another embodiment, Fig. 9 method also includes：Based on the second filter factor to the second input data
It is filtered, to eliminate intersymbol interference advanced in time and obtain the first input data；The equalization output result is carried out
Hard decision obtains court verdict；The equalization output result is added with the court verdict and obtains decision error；Missed according to the judgement
Difference updates the first filter factor；Second filter factor is updated according to the decision error.
In 930, the decoding result can be selected according to control information, and based on the first filter factor to the decoding knot
Fruit is filtered, and wherein the equalization methods also include：The court verdict is selected according to the control information, and based on the first filtering
Coefficient is filtered to the court verdict, obtains the feedback signal, to eliminate intersymbol interference delayed in time.
In 930, the decoding result can be selected in the case where the control information indicates normal mode of operation, and
In the case where the control information indicates training mode, the court verdict is selected.
Alternatively, as another embodiment, Fig. 9 method also includes：Based on the first filter factor to the feedback equalizer
The data of input are filtered to eliminate intersymbol interference delayed in time.
Alternatively, as another embodiment, Fig. 9 method also includes：Based on the first filter factor to the decoding result
Delay disposal is carried out to the decoding result before being filtered.
In 920, Trellis-coded modulation decoding can be carried out to the equalization output result and obtains decoding result.
Those of ordinary skill in the art are it is to be appreciated that the list of each example described with reference to the embodiments described herein
Member and algorithm steps, can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
Performed with hardware or software mode, depending on the application-specific and design constraint of technical scheme.Professional and technical personnel
Described function can be realized using distinct methods to each specific application, but this realization is it is not considered that exceed
The scope of the present invention.
It is apparent to those skilled in the art that, for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, may be referred to the corresponding process in preceding method embodiment, will not be repeated here.
, can be with several embodiments provided herein, it should be understood that disclosed systems, devices and methods
Realize by another way.For example, device embodiment described above is only schematical, for example, the unit
Divide, only a kind of division of logic function there can be other dividing mode when actually realizing, such as multiple units or component
Another system can be combined or be desirably integrated into, or some features can be ignored, or do not perform.It is another, it is shown or
The coupling each other discussed or direct-coupling or communication connection can be the indirect couplings of device or unit by some interfaces
Close or communicate to connect, can be electrical, machinery or other forms.
The unit illustrated as separating component can be or may not be it is physically separate, it is aobvious as unit
The part shown can be or may not be physical location, you can with positioned at a place, or can also be distributed to multiple
On NE.Some or all of unit therein can be selected to realize the mesh of this embodiment scheme according to the actual needs
's.
In addition, each functional unit in each embodiment of the invention can be integrated in a processing unit, can also
That unit is individually physically present, can also two or more units it is integrated in a unit.
If the function is realized using in the form of SFU software functional unit and is used as independent production marketing or in use, can be with
It is stored in a computer read/write memory medium.Understood based on such, technical scheme is substantially in other words
The part contributed to prior art or the part of the technical scheme can be embodied in the form of software product, the meter
Calculation machine software product is stored in a storage medium, including some instructions are to cause a computer equipment（Can be individual
People's computer, server, or network equipment etc.）Perform all or part of step of each embodiment methods described of the invention.
And foregoing storage medium includes：USB flash disk, mobile hard disk, read-only storage（ROM, Read-Only Memory）, arbitrary access deposits
Reservoir（RAM, Random Access Memory）, magnetic disc or CD etc. are various can be with the medium of store program codes.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those familiar with the art the invention discloses technical scope in, change or replacement can be readily occurred in, should all be contained
Cover within protection scope of the present invention.Therefore, protection scope of the present invention should be defined by scope of the claims.
Claims (11)
1. a kind of equalizing circuit, it is characterised in that including：
Forward equalizer, receives the second input data, for being filtered based on the second filter factor to second input data
Ripple, to eliminate advanced in time intersymbol interference and intersymbol interference delayed in time and obtain the first input data, and
And export first input data to first adder；
The first adder, receives feedback signal and first input data exported by the forward equalizer, is used for
First input data is added with the feedback signal, output result is equalized；
Decoder, receives the equalization output result, obtains decoding result for entering the equalization output result row decoding；
Feedback equalizer, receives the decoding result, for being filtered based on the first filter factor to the decoding result, obtains
The feedback signal is exported to the feedback signal, and to the first adder, to eliminate code delayed in time
Between disturb；
Decision device, receives the equalization output result, and court verdict is obtained for carrying out hard decision to the equalization output result；
Second adder, receives the court verdict and the equalization output result, for by the equalization output result and institute
State court verdict addition and obtain decision error；
First coefficient updating module, receives the decision error, is for updating first filtering according to the decision error
Number, and export first filter factor to the feedback equalizer；
Second coefficient updating module, receives the decision error, is for updating second filtering according to the decision error
Number, and export second filter factor to the forward equalizer.
2. equalizing circuit according to claim 1, it is characterised in that also include：
Selector, receives the court verdict and the decoding result, for according to the control information selection decoding result or
Court verdict described in person, and the decoding result of selection or the court verdict are output to the feedback equalizer work
For the feedback signal.
3. equalizing circuit according to claim 2, it is characterised in that normal work of the selector in the equalizing circuit
The decoding result is selected to be output to the feedback equalizer under operation mode, the training before the normal work of the equalizing circuit
The court verdict is selected to be output to the feedback equalizer under pattern.
4. the equalizing circuit according to any one of claims 1 to 3, it is characterised in that the decoder with it is described anti-
Multiple delay time registers are connected between feedback balanced device.
5. the equalizing circuit according to any one of claims 1 to 3, it is characterised in that the decoder is compiled for grid
Code modulation decoder.
6. a kind of data transmission system, it is characterised in that including：
Local transmitter, for sending data to remote receiver；
Local receiver, for receiving data from long-range transmitter；
Blender, is connected between the local transmitter and the data transmission system transmission line, and be connected to described
Between ground receiver and the transmission line；
Equalizing circuit as described in any one of claim 1 to 5, be connected to the local receiver and the blender it
Between, for eliminating the intersymbol interference in the data that the local receiver is received.
7. a kind of equalization methods, it is characterised in that including：
The second input data is filtered based on the second filter factor, with eliminate advanced in time intersymbol interference and when
Between upper delayed intersymbol interference and obtain the first input data；
First input data is added with feedback signal, output result is equalized；
Enter row decoding to the equalization output result to obtain decoding result；
The decoding result is filtered based on the first filter factor, the feedback signal is obtained, to eliminate in time
Delayed intersymbol interference；
Hard decision is carried out to the equalization output result and obtains court verdict；
The equalization output result is added with the court verdict and obtains decision error；
First filter factor is updated according to the decision error；
Second filter factor is updated according to the decision error.
8. equalization methods according to claim 7, it is characterised in that first filter factor that is based on is tied to the decoding
Fruit is filtered, including：
The decoding result is selected according to control information, and the decoding result filtered based on first filter factor
Ripple,
Wherein the equalization methods also include：
The court verdict is selected according to the control information, and the court verdict entered based on first filter factor
Row filtering, obtains the feedback signal, to eliminate intersymbol interference delayed in time.
9. equalization methods according to claim 8, it is characterised in that described to be tied according to the control information selection decoding
Really, including：
In the case where the control information indicates normal mode of operation, the decoding result is selected,
It is wherein described that the court verdict is selected according to the control information, including：
In the case where the control information indicates training mode, the court verdict is selected.
10. the equalization methods according to any one of claim 7 to 9, it is characterised in that also include：Based on described
First filter factor carries out delay disposal before being filtered to the decoding result to the decoding result.
11. the equalization methods according to any one of claim 7 to 9, it is characterised in that described to the balanced output
As a result enter row decoding to obtain decoding result, including：
Trellis-coded modulation decoding is carried out to the equalization output result to obtain decoding result.
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| US9647799B2 (en) * | 2012-10-16 | 2017-05-09 | Inphi Corporation | FEC coding identification |
| CN103401821B (en) * | 2013-07-22 | 2017-02-22 | 苏州英菲泰尔电子科技有限公司 | Adaptive equalizer of Bluetooth 4.0 low-power receiver and implementation method of adaptive equalizer |
| WO2015036008A1 (en) * | 2013-09-10 | 2015-03-19 | Huawei Technologies Co.,Ltd. | A turbo decoder for decoding an input signal |
| CN107872409A (en) * | 2016-09-23 | 2018-04-03 | 华为技术有限公司 | Balanced device |
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| CN109981500B (en) * | 2017-12-28 | 2023-04-28 | 海思光电子有限公司 | Signal processing method and signal processing device |
| CN110391875B (en) * | 2018-04-23 | 2020-10-09 | 华为技术有限公司 | Error correction method and error correction device |
| CN112567703A (en) | 2018-08-17 | 2021-03-26 | 拉姆伯斯公司 | Multi-stage equalizer for intersymbol interference cancellation |
| CN111107025A (en) * | 2018-10-26 | 2020-05-05 | 上海晟矽微电子股份有限公司 | Adaptive equalizer in GFSK receiver |
| US11528168B2 (en) | 2019-08-02 | 2022-12-13 | Sitrus Technology Corporation | Methods, systems and apparatus for hybrid signal processing for pulse amplitude modulation |
| CN113225277B (en) * | 2020-01-21 | 2023-12-19 | 瑞昱半导体股份有限公司 | Signal processing device and signal processing method |
| CN113346903B (en) * | 2021-06-18 | 2023-07-14 | 重庆吉芯科技有限公司 | On-line self-adaptive direct current offset correction circuit and receiver |
| CN113765833B (en) * | 2021-07-23 | 2023-12-29 | 南方电网数字平台科技(广东)有限公司 | Nonlinear equalization method, device and storage medium based on multipath decision |
| CN113992484A (en) * | 2021-10-19 | 2022-01-28 | 中国人民解放军国防科技大学 | Adaptive equalizer for high-speed serial interface and SerDes transceiver |
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