CN104579574B - Trellis-coded modulation method applied to High speed rear panel chip chamber electric interconnection system - Google Patents
Trellis-coded modulation method applied to High speed rear panel chip chamber electric interconnection system Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
- H04L1/006—Trellis-coded modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
- H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity
- H04L1/0618—Space-time coding
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- H04L1/065—Properties of the code by means of convolutional encoding
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Abstract
The invention discloses a kind of Trellis-coded modulation method applied to High speed rear panel chip chamber electric interconnection system, this method is related to the grid coding modulation technique applied to High speed rear panel chip chamber electric interconnection system, the collaborative design that this method passes through channel coding and signal modulation, channel band width can neither increased, also coding gain is obtained in the case of not reducing effective information transmission rate, improves the performance of the serial single-link of chip chamber.The system transmitting terminal includes data and turns string, Trellis-coded modulation, feed-forward balanced device, the means that wherein Trellis-coded modulation takes convolutional encoding and four level pulse amplitude modulation(PAM)s are combined；Receiving terminal includes continuous time linear equalizer, DFF, clock and data recovery, soft output Viterbi decoding, serial data and turned simultaneously, and wherein the coefficient update of DFF wave filter is based on the error correction signal after soft output Viterbi decoding.
Description
Technical field
The present invention relates to High speed rear panel chip chamber electric interconnection system field, specifically by Trellis-coded modulation (Trellis
Coded Modulation, TCM) technology is used for High speed rear panel chip chamber electric interconnection system, and the error correcting capability for passing through coding obtains
Coding gain, so as to improve the reliability that serial single-link system is electrically interconnected in chip chamber.
Background technology
The performance of high performance parallel computer system is fast-developing, growing day by day to the demand of interconnection I/O bandwidth abilities, high
Fast serializer/de-serializers technology is substituting Traditional parallel bus to turn into the main flow that interfacing is electrically interconnected at a high speed in chip chamber.It is high
Parallel data stream is converted into serial stream by fast serializer/de-serializers technology using internal integrated circuit, it is desirable to which High speed rear panel electricity is mutually
Even the message transmission rate of channel reaches 20~40Gbit/s, and data transfer speed is improved by balanced and clock and data recovery technology
Rate.The raising of chip chamber serial data transmission speed and the increase of channel distance bring to the validity and reliability of transmission and chosen
War, signal are influenceed in transmitting procedure by channel loss, reflection, crosstalk and noise so that the signal that receiving terminal receives
Intersymbol interference is serious, so as to cause high bit-error.In order to meet the low error rate demand of chip chamber high speed serialization link, Wo Menxi
Hope makes system have certain error correction and antijamming capability by introducing error correction controlled coding, improves the reliability of transmission.
Error correcting code is being connect by increasing unnecessary code word to true form word in transmitting terminal to expand the difference between transmission code word
Whether the code word that receiving end receives according to coding rule judgement is wrong, so as to greatly avoid the hair of error code during code stream transmits
It is raw.Error Correction of Coding can reduce the efficiency of transmission of information data, thus in general error correction coding for example Hamming code, convolutional code,
On the basis of improvement of reed-solomon (Reed-Solomon, the RS) code to information transmission performance is built upon bandwidth expansion, so
And in the high speed serialization channel of Bandwidth-Constrained, band resource is valuable, is difficult to improve by traditional error correction coding
Channel utilization is so as to improving systematic function.Error Correction of Coding and modulation are combined together progress entirety by grid coding modulation technique
The optimal design of scheme, it can be obtained in the case where not increasing system bandwidth, do not reduce effective information transmission rate necessarily
Coding gain.With the continuous improvement of high speed serialization link communication data rate requirement, the modulation of system and coding techniques
As the solution alternative of raising message transmission rate, such as four level pulse amplitude modulation(PAM) (Four Pulse
Amplitude Modulation, PAM4) and forward error correction coding (Forward Error Correction, FEC).How
This effective technical scheme of Error Correction of Coding is applied to high speed serialization electric interconnection system, is not changing valid data transmission rate
Meanwhile error rate of system is reduced, improve systematic function and solved the problems, such as compeling to be essential at present.
The content of the invention
The technical problem to be solved in the present invention is to provide one kind to be simply applied to High speed rear panel chip chamber electric interconnection system
Trellis-coded modulation method.
In order to solve the above-mentioned technical problem, the present invention provides a kind of net applied to High speed rear panel chip chamber electric interconnection system
Trellis coded modulation method；This method uses transmitting terminal and receiving terminal；The transmitting terminal includes data and turns string module, grid coding
Modulation module and feed-forward balanced device；The receiving terminal includes continuous time linear equalizer, DFF, clock
Data recovery module, soft output Viterbi decoding module, serial data turns and module；The data simultaneously turn string module by the N of input
Bit parallel data a [1:N] serial binary bits { X is converted to by parallel-to-serial convertern,Xn=0,1 }；The grid coding
Modulation module is by binary bits { Xn,Xn=0,1 } four kinds of level pulse waveform s0 (t) are converted to；The feed-forward balanced device
Pass throughOutput signal s1 (t)；The channel passes throughOutput signal
r0(t)；The continuous time linear equalizer passes throughOutput signal r1 (t)；The decision-feedback
Balanced device passes throughOutput signal r2 (t)；The clock and data recovery module is from consecutive hours
Between linear equalizer output signal r1 (t) extraction clock, obtain the optimum sampling moment be supplied to DFF；It is described
Soft output Viterbi decoding module exports serial binary bit by output signal r2 (t)And feed back mistake
Difference signal e (k) is to DFF；The serial data turns and module is by serial binary bitConversion
For N bit parallel datas
As to the Trellis-coded modulation method of the present invention applied to High speed rear panel chip chamber electric interconnection system
Improve：The Trellis-coded modulation module includes convolution coder and four level pulse modulation circuits；The convolution coder will
Binary bits { Xn,Xn=0,1 } each bit input is passed throughAfter the convolutional encoding of code check, dibit output { Y is obtainedn
(1),Yn(0),Yn=0,1 }；Code word { the Y of the convolution coder outputn(1),Yn(0),Yn=0,1 } four level arteries and veins are mapped to
Rush in the planisphere of amplitude modulation(PAM), coded-bit { Yn(1),Yn(0),Yn=0,1 } obtained after four level pulse amplitude modulation(PAM)s
Four kinds of level pulse waveform s0 (t).
As to the Trellis-coded modulation method of the present invention applied to High speed rear panel chip chamber electric interconnection system
Further improve：The continuous time linear equalizer includes amplifier and comparator；Pass through the electricity to amplifier and comparator
Appearance and resistance adjustment, change the position of zero point and the first limit, and then change frequency response hCTLE(t), finally export
As to the Trellis-coded modulation method of the present invention applied to High speed rear panel chip chamber electric interconnection system
Further improve：The DFF includes the feedback filter and decision device of built-in feedback branch；Feedback branch
Input is judgement output result of the decision device to previous group symbolThe input of continuous time linear equalizer subtracts
The output of feedback filter obtains the input of decision device.
As to the Trellis-coded modulation method of the present invention applied to High speed rear panel chip chamber electric interconnection system
Further improve：It is automatic first to call the adaptive of regulation filter coefficient under adaptive state in DFF
Training step, output signal then is produced using each signal on filter factor weighted delay line, output signal is believed with it is expected
Number compare, the error of gained adjusts weights again by adaptive control algorithm, it is ensured that feedback filter is at one's best.
As to the Trellis-coded modulation method of the present invention applied to High speed rear panel chip chamber electric interconnection system
Further improve：The soft output Viterbi decoding module (24) receives an output symbol r2 of decision-feedback device (22)
(k) metric calculation, is carried out, updates a path, traceback decoding is carried out after having received a frame data, and is exported serial
Binary bitsMeanwhile soft output Viterbi decoding module will decode the desired signal of outputWith sentencing
Certainly the output r2 (k) of ultramagnifier obtains error signal e (k) by subtracter, and error signal e (k) feeds back to decision feedback equalization
The adaptive control algorithm of device is so as to updating its filter coefficient.
It is contemplated that grid coding technology is used for into high speed serialization link, improves High speed rear panel chip chamber and be electrically interconnected serially
The transmission performance of single-link system, reduce the bit error rate.Convolutional encoding is taken mutually to be tied with four level pulse amplitude modulation(PAM)s in transmitting terminal
Close (being represented by TCM-PAM4), receiving terminal takes soft output Viterbi decoding to obtain coding gain, improves the reliability of transmission.
(coding gain is a kind of measurement, reaches the identical bit error rate (Bit for defining the system of uncoded system and coding
Error Rate, BER) needed for minimum signal to noise ratio (Signal-to-Noise Rate, SNR) difference.)
The technology that convolutional encoding and four level pulse amplitude modulation(PAM)s are combined (TCM-PAM4) can obtain following beneficial effect
Fruit：
(1) take convolutional encoding to obtain error-correcting performance in transmitting terminal, make system that there is certain antijamming capability；
(2) there are the four level pulse amplitude modulation(PAM)s for carrying dibit information capability to ensure the redundancy needed for convolutional encoding
Degree, makes the effective transmission speed of system constant；
(3) convolutional encoding and pulse amplitude modulation combine, and modulated signal is obtained maximum Euclidean using Trellis-coded modulation
Distance, soft output Viterbi decoding is used in receiving terminal, Optimum signal detection is realized, obtains maximum coding gain.
The Trellis-coded modulation that high-speed serial link system takes convolutional encoding and four level pulse amplitude modulation(PAM)s are combined,
Using the redundancy of high order modulation signal collection, transmit small bit number with big constellation and obtain error correcting capability.It is this first by a ratio
Spy is encoded into the dibit code word with error correcting capability, re-maps to going on four level constellations, system can obtain 2.55dB volume
Code gain.
Transmitting terminal coded modulation of the present invention includes：
(1) coding module：Input message sequence { the X of a bit will be includedn,Xn=0,1 } carrying out code check isConvolution
Coding, obtains dibit output signal { Yn(1),Yn(0),Yn=0,1 }, wherein n represents the n moment；
(2) modulation module：The subset that signal constellation point is transmitted according to Trellis-coded modulation is split, according to obtained point
Collect mapping relations, the dibit code word { Y that encoder is exportedn(1),Yn(0),Yn=0,1 } it is mapped to four level pulse amplitudes tune
In the planisphere for making (PAM4), the modulated signal of output is taken from one in the signal set of four level pulse amplitude modulation(PAM) constellations
Individual signal.
For the coding gain obtained using Trellis-coded modulation, receiving terminal of the present invention uses soft output Viterbi decoding,
The task of decoding is that a paths are selected in grid chart, makes the distance between corresponding coding sequence and receiving sequence minimum.
Decoding procedure includes carrying out maximum-likelihood sequence estimation according to viterbi algorithm, finds and the immediate code sequence of receiving sequence；
Original information bits stream is recovered according to the code sequence after decoding and transmitting terminal convolution mapping relations.
The present invention proposes Trellis-coded modulation (TCM-PAM4) being used for High speed rear panel chip chamber electric interconnection system, in backboard
The electrical interconnection signal of channel first passes through convolutional encoding and four level amplitude modulations before entering link transmitting terminal balanced device,
Pass through soft output Viterbi decoding in receiving terminal, the system can carry out error correction in receiving terminal because introducing convolutional encoding, use simultaneously
High order modulation makes system bandwidth keep constant, and relative to uncoded two level serial link system, the system can obtain
2.55dB coding gain, improve the antijamming capability of High speed rear panel electric interconnection system.
Brief description of the drawings
The embodiment of the present invention is described in further detail below in conjunction with the accompanying drawings.
Fig. 1 is the High speed rear panel chip chamber electric interconnection system serial link structured flowchart of the present invention；
The convolution coder 121 that Fig. 2 is the present invention realizes block diagram；
Fig. 3 is the diversity mapping graph of the four level pulse amplitude modulation(PAM)s of the present invention；
Fig. 4 is that the module of feed-forward balanced device 13 in transmitting terminal 1 of the invention realizes block diagram；
Fig. 5 is the circuit diagram of continuous time linear equalizer 21 in receiving terminal 2 of the invention；
Fig. 6 is that the module of DFF 22 in receiving terminal 2 of the invention realizes block diagram；
Fig. 7 is the coefficient update block diagram that DFF 22 is sentenced in the receiving terminal 2 of the present invention；
Fig. 8 is Viterbi decoding block diagram in receiving terminal 2 of the invention；
Fig. 9 is the state transition network trrellis diagram of the Trellis-coded modulation of the present invention；
Figure 10 is the Trellis-coded modulation coding gain curve of the present invention.
Embodiment
Embodiment 1, Fig. 1 give a kind of Trellis-coded modulation side applied to High speed rear panel chip chamber electric interconnection system
Method；This method uses transmitting terminal 1 and receiving terminal 2；Transmitting terminal 1 includes data and turns string module 11, Trellis-coded modulation module 12
With feed-forward balanced device 13；Receiving terminal 2 includes continuous time linear equalizer 21, DFF 22, soft-decision dimension
It is special to turn simultaneously module 25 than decoding module 24, serial data.
Data simultaneously turn a string module 11 and are used for the N bit parallel datas a [1 of input:N] be converted to serial binary bits
{Xn,Xn=0,1 }；Trellis-coded modulation module 12 includes the level pulse amplitude modulation circuit of convolution coder 121 and four；Such as Fig. 2
Shown, data simultaneously turn the binary bits { X that string module 11 exportsn,Xn=0,1 } convolution coder 121 is sent into as input, often
One bit input is passed throughAfter the convolutional encoding of code check, dibit output { Y is obtainedn(1),Yn(0),Yn=0,1 }, X is inputtednWith
Export YnRelational expression is as followsSnFor the shift register state of convolutional codeSuch as figure
Shown in 3, four level pulse amplitude modulation circuits are split to obtain mapping relations using the subset of Trellis-coded modulation, convolutional encoding
Code word { the Y that device 121 exportsn(1),Yn(0),Yn=0,1 } it is mapped in the planisphere of four level pulse amplitude modulation(PAM)s (PAM4)；
Trellis-coded modulation obtains maximum coding gain using the means of subset segmentation, according to Fig. 3 mapping relations four kinds of encoders
Export { Yn(1),Yn(0),Yn=0,1 } it is mapped in different constellation points；Coded-bit { Yn(1),Yn(0),Yn=0,1 } pass through
The impulse waveform s0 (t) of four level is obtained after four level pulse amplitude modulation(PAM)s.
The interface standard of high-speed serializer/deserializer application typically requires the bit error rate of link 10-12~10-15, in height
Under message transmission rate, intersymbol interference caused by channel non-ideal characteristic turns into the key issue for restricting link design, therefore line
Road transceiver must design the data recovery circuit for including advanced equalization function, to tackle the number caused by channel width limits
It is lost according to integrality.The transmitting terminal of most of high speed serialization links includes a feed-forward balanced device, and its time domain thought is exactly,
Whenever it a saltus step in data be present, just strengthen the amplitude of high-frequency signal, by the last data bit sent and currently
Data bit is compared, if the two bits are identical, current bit is normally sent；If the two bits are different, when
Sent after preceding bit amplitudes increase certain proportion.Feed-forward balancing technique is mainly to be filtered using the finite impulse response of multi-tap
Ripple device is realized, as shown in figure 4, the feed-forward balanced device 13 of the present invention is by Postponement module, weighting block and accumulator three parts
Form：Square frame represents delay circuit, and T is time delay, takes the mark space of data signal, and W is weight coefficient；Transmitting terminal 1
Sampling s0s (t-nT) of the signal s0 (t) at the kth moment after coding and pulse-shaping is sent into after delay and each tap weight
As final output signal s1 (t), its time-domain expression after the addition of accumulator 133Forward direction is anti-
Feedback the transfer function of balanced device 13 frequency domain representation beBy selecting appropriate filter coefficient W
Carry out balanced.
S1 (t) signals of transmitting terminal 1 obtain output signal by channel 3hchannel(t) it is
The impulse response of channel.
As shown in figure 5, continuous time linear equalizer 21 includes the active circuits such as amplifier and comparator, equivalent to one
The balanced device of disjoint paths, the degeneration resistance R of transistor sourcesEquivalent to one all-pass path, eye diagram CsEquivalent to one
High pass path.By adjusting these variable capacitances and resistance, change the position of zero point and the first limit, and then change high frequency and low
Frequency gain, its transfer function are：Wherein gmFor transistor transconductance, CpAnd RDPoint
Wei not output end load capacitance and resistance.The zero point and limit of continuous time linear equalizer 21 are obtained from transfer function：
Its DC current gain isGain peak point
For gmRD, high-frequency gain is
Continuous time linear equalizer 21 exports
As shown in fig. 6, DFF 22 is a kind of widely used nonlinear equalizer, by feedback filter and
Decision device forms；The input of feedback branch is judgement output result of one group of decision device to previous group symbolIt is balanced
The output that device input subtracts feedback filter just obtains the input of decision device, and it is to detect intersymbol interference according to character estimation that it, which is acted on,
Part, offset the hangover of channel.Because feedback branch be present, DFF 22 can be filtered by constantly updating
Device coefficient carrys out the change of adaptive channel and noise.
As shown in fig. 7, be the block diagram of realizing of adaptive decision feedback equalizer 22, main processes can be with according to function
It is divided into three parts, is broadly divided into filtering, seeks three calculating process of error and right value update.
The signal r1 (t) that continuous time linear equalizer 21 exports is input to DFF 22, in adaptive shape
Under state, the automatic adaptive training step for calling filter coefficient update, then using respectively believing on filter factor weighted delay line
Number produce output signal, the output of DFF 22Wherein wi(k) it is the
The filter coefficient at k moment, N are filter order, and d (k-i) is that judgements of the r2 (t) in i-th of delay cell of k moment is defeated
Go out；The desired signal that output signal r2 (t) and soft output Viterbi decoding module 24 are exportedCompared to (passing through subtracter),
The error e (k) of gained adjusts weights again by certain adaptive control algorithm, to ensure that wave filter is at one's best；
The specific formula of adaptive control algorithm of filter coefficient is as follows：
Wherein μ is the step-length of filter coefficient update, directly
Connect and affect DFF coefficient convergence rate and steady-state error, error signal
For the expectation of output signal, the expectation of output signal can be used as by the signal after its receiving terminal soft output Viterbi decoding.
Clock and data recovery module 23 from serial data r1 (t) (i.e. continuous time linear equalizer 21 export signal r1
(t) recover clock signal in), and the optimum sampling point of data is found by the regulation of circuit, by data when resetting
Recover data, eliminate the shake that data introduce in transmitting procedure, its performance have to whole high speed serial transmission system to
Close important influence.
In order to utilize the coding gain of Trellis-coded modulation, system uses soft output Viterbi decoding module 24 in decoding
Maximum likelihood algorithm carries out receiving terminal soft-decision, and the task of decoding is that a paths are selected in grid chart, make to translate accordingly
Code the distance between sequence and receiving sequence minimum, generally will likely coding sequence and receiving sequence between Euclidean distance claim
For measurement.The selected output of Soft decision decoding is not binary coding symbol, but provides log-likelihood function value as maximum code
Word.Soft output Viterbi decoding can be directly carried out because parallel transfer is not present in the Trellis-coded modulation that system is taken；Such as Fig. 8
It is decoding procedure：Maximum-likelihood sequence estimation is carried out according to viterbi algorithm, found and the immediate code sequence of receiving sequence；Root
Recover original information bits stream according to the code sequence after decoding and bit allocation table.
Usual complete Viterbi decoding, is an output symbol r2 (k) for receiving decision-feedback device 22, is carried out once
Metric calculation, a path is updated, traceback decoding is just carried out after having received a frame data.Before and after soft output Viterbi decoding
The obtained error signal e (k) of signal subtraction feed back to DFF, intrinsic decoding existing for its soft-decision algorithm is prolonged
Shi Buyi is excessive, so needing to carry out truncation decoding.It is in fact, normal in the stateful corresponding retention path of L moment institute
Often it is to overlap before the L-D moment, the probability of the bigger coincidences of D is higher, generally takes the constraint length that D is 3-5 times, system convolution
The constraint length of encoder is 2, therefore takes D=10's to block decoding, and decoding delay can be prevented excessive and what data were overflowed asks
Topic.
Serial data turns the serial binary bit that simultaneously module 25 is used to export soft output Viterbi decoding module 24Be converted to N bit parallel datas
Trellis-coded modulation introduces redundancy in transmitting terminal 1 using convolutional encoding, and letter is maintained using the method for high order modulation
Number bandwidth it is constant, at the same time, system can obtain certain coding gain.Analyze uncoded two level modulation (NRZ)
With four level pulse amplitude modulation(PAM) (TCM-PAM4) systems after Trellis-coded modulation, to reach the identical bit error rate (BER) will
Ask, the minimum signal to noise ratio (SNR) of receiving end signal.System noise is modeled as Gaussian white noise, two level modulations (NRZ) system
The bit error rate (BER) and the relation of signal to noise ratio (SNR) it is as follows：Whereinσ2For system
The variance of Gaussian white noise, d are maximum transmission level.The grid being combined for convolutional encoding and four level pulse amplitude modulation(PAM)s
Coded modulation (TCM-PAM4) system, soft output Viterbi decoding, the coding gain of coded system are taken in receiving terminalWherein PTCMAnd PuncodedThe respectively average transmitting power of net coding system and uncoded system,
dfree 2For the free distance d of Trellis-coded modulation (TCM)free 2=min (dseq 2,dpar 2), dseqRepresent the net of Trellis-coded modulation
Minimum range in trrellis diagram between non-parallel branch, dparRepresent the minimum range between parallel transfer branch.For different grids
Coded modulation (TCM), its free distance is bigger, then the coding gain obtained is bigger.
Fig. 9 is the state transition network trrellis diagram for the Trellis-coded modulation that transmitting terminal uses, and is obtained for calculating its free distance
Coding gain.It is not present in grid chart and shifts parallel, therefore dfree 2=dseq 2, for two non-parallel transfer paths (10,01,
10), (00,00,00) obtains dseq 2=dis (00,10)2+dis(00,01)2+dis(00,10)2, it is assumed that four level signal collection stars
Minimum range △ between each point in seat0, secondary small distance △1(△1=2 △0), ultimate range △2(△2=3 △0=2d), then dpar 2=
2Δ1 2+Δ0 2=9 Δs0 2, free distance：dfree 2=9 Δs0 2=4d2, the mean power of four level pulse amplitude modulation(PAM)s transmission signalThe coding gain of relatively uncoded two level system of four level systems after codingIt is converted into dB thenThe coded system bit error rateAbout equal sign is set up in system low error rate, need to meet that the bit error rate is less than 10-6, high speed serialization chain
The design object on road is generally 10-12~10-15, therefore equation is set up.
Figure 10 is that system noise is modeled as into Gaussian white noise, transmitting terminal using the modulation of uncoded two level (NRZ) and
The bit error rate of Trellis-coded modulation (TCM-PAM4) system and the relation curve of snr of received signal, by the bit error rate and signal to noise ratio
Relation curve is analyzed：Reach same bit error rate, the snr of received signal of Trellis-coded modulation (TCM-PAM4) system requirements is low
In uncoded system, uncoded two level (NRZ) system wants to obtain must just connect with the coded system identical bit error rate
Receive the lifting that 2.55dB is obtained on Signal-to-Noise.
With 10-12Link simulation research is carried out on the basis of the High speed rear panel chip chamber electric interconnection system of the bit error rate, calculating is not compiled
Two level (NRZ) modulation of code and Trellis-coded modulation (TCM-PAM4) system reach 10-12Minimum SNR points needed for the bit error rate
It is not：16.94dB and 14.29dB, using 6 25Gbit/s standard channels of IEEE 802.3bj 100GBASE Organisation recommendations
Carry out link simulation contrast.(noise margin counts the noise margin of Trellis-coded modulation (TCM-PAM4) system for link simulation
Signal to noise ratio and reach 10-12Minimum SNR difference needed for the bit error rate) than uncoded two level (NRZ) system have 1~2.5dB's
Lifting.
The present invention proposes to be used to carry on the back by Trellis-coded modulation to improve the performance of High speed rear panel chip chamber electric interconnection system
Link is electrically interconnected in the high speed serialization of plate channel, uses code check mutually to be tied with four level amplitude modulations for 1/2 convolutional code in transmitting terminal
The means of (TCM-PAM4) are closed, pass through soft output Viterbi decoding in receiving terminal, relative to uncoded two level (NRZ) of tradition
Serial link system, the system can obtain 2.55dB coding gain, while obtain 1 in the system noise allowance of link simulation
~2.5dB lifting.Therefore, grid coding modulation technique, which is used for High speed rear panel chip chamber electric interconnection system, can improve tandem system
Antijamming capability, optimize systematic function.
Finally, it is also necessary to it is noted that listed above is only a specific embodiment of the invention.Obviously, it is of the invention
Above example is not limited to, applies also for the deformation of many Trellis-coded modulations, such as utilizes more complicated convolutional encoding and high-order
Modulation means obtain bigger coding gain.One of ordinary skill in the art can directly be exported from present disclosure or
All deformations associated, are considered as protection scope of the present invention.
Claims (6)
1. the Trellis-coded modulation method applied to High speed rear panel chip chamber electric interconnection system；This method using transmitting terminal (1) and
Receiving terminal (2)；It is characterized in that：The transmitting terminal (1) include data and turn string module (11), Trellis-coded modulation module (12) and
Feed-forward balanced device (13)；
The receiving terminal (2) includes continuous time linear equalizer (21), DFF (22), clock and data recovery mould
Block (23), soft output Viterbi decoding module (24), serial data turns and module (25)；
The data simultaneously turn string module (11) by the N bit parallel datas a [1 of input:N] be converted to by parallel-to-serial converter it is serial
Binary bits { Xn,Xn=0,1 }；
The Trellis-coded modulation module (12) is by binary bits { Xn,Xn=0,1 } four kinds of level pulse waveform s0 are converted to
(t)；
The feed-forward balanced device (13) passes throughOutput signal s1 (t)；
Channel (3) passes throughOutput signal r0 (t)；
The continuous time linear equalizer (21) passes throughOutput signal r1 (t)；
The DFF (22) passes throughOutput signal r2 (t)；
The clock and data recovery module (23) extracts clock from the output signal r1 (t) of continuous time linear equalizer (21),
The acquisition optimum sampling moment is supplied to DFF (22)；
The soft output Viterbi decoding module (24) exports serial binary bit by output signal r2 (t)And feedback error signal e (k) is to DFF (22)；
The serial data turns and module (25) is by serial binary bitBe converted to N bit parallel datas
hchannel(t) it is the impulse response of channel, hCTLE(t) it is the time-domain pulse response of continuous time linear equalizer (21), wn
For the weight coefficient of feed-forward balanced device (13), wi(k) it is the filter coefficient at kth moment, d (k-i) is r2 (t) in k
Carve the judgement output in i-th of delay cell.
2. the Trellis-coded modulation method according to claim 1 applied to High speed rear panel chip chamber electric interconnection system, its
It is characterized in：The Trellis-coded modulation module (12) includes convolution coder (121) and four level pulse modulation circuits；
The convolution coder (121) is by binary bits { Xn,Xn=0,1 } each bit input is passed throughThe volume of code check
After product coding, dibit output { Y is obtainedn(1),Yn(0),Yn=0,1 }；
Code word { the Y of convolution coder (121) outputn(1),Yn(0),Yn=0,1 } four level pulse amplitude modulation(PAM)s are mapped to
Planisphere in, coded-bit { Yn(1),Yn(0),Yn=0,1 } four kinds of level arteries and veins are obtained after four level pulse amplitude modulation(PAM)s
Rush waveform s0 (t).
3. the Trellis-coded modulation method according to claim 1 applied to High speed rear panel chip chamber electric interconnection system, its
It is characterized in：The continuous time linear equalizer (21) includes amplifier and comparator；
By the electric capacity and resistance adjustment to amplifier and comparator, change the position of zero point and the first limit, and then change frequency
Rate responds hCTLE(t), finally export
4. the Trellis-coded modulation method according to claim 1 applied to High speed rear panel chip chamber electric interconnection system, its
It is characterized in：The DFF (22) includes the feedback filter and decision device of built-in feedback branch；
The input of feedback branch is judgement output result of the decision device to previous group symbolContinuous time is linearly equal
The output that the input of weighing apparatus (21) subtracts feedback filter obtains the input of decision device.
5. the Trellis-coded modulation method according to claim 4 applied to High speed rear panel chip chamber electric interconnection system, its
It is characterized in：It is automatic first to call the adaptive of regulation filter coefficient under adaptive state in DFF (22)
Training step, output signal then is produced using each signal on filter factor weighted delay line, output signal is believed with it is expected
Number compare, the error of gained adjusts weights again by adaptive control algorithm, it is ensured that feedback filter is at one's best.
6. the Trellis-coded modulation method according to claim 5 applied to High speed rear panel chip chamber electric interconnection system, its
It is characterized in：The soft output Viterbi decoding module (24) receives an output symbol r2 (k) of decision-feedback device (22), enters
Metric calculation of row, a path is updated, traceback decoding is carried out after having received a frame data, and export serial binary
Bit
Meanwhile soft output Viterbi decoding module (24) will decode the desired signal of outputIt is defeated with decision-feedback device (22)
Go out r2 (k) and error signal e (k) is obtained by subtracter, error signal e (k) feeds back to the adaptive of DFF (22)
Control algolithm is answered so as to update its filter coefficient.
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| CN101841339A (en) * | 2009-03-17 | 2010-09-22 | 大唐移动通信设备有限公司 | Encoder, decoder and encoding and decoding methods |
| CN103117837A (en) * | 2013-01-18 | 2013-05-22 | 北京邮电大学 | Modified time-pulse position modulation (T-PPM) code modulation method |
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| CN101841339A (en) * | 2009-03-17 | 2010-09-22 | 大唐移动通信设备有限公司 | Encoder, decoder and encoding and decoding methods |
| CN103117837A (en) * | 2013-01-18 | 2013-05-22 | 北京邮电大学 | Modified time-pulse position modulation (T-PPM) code modulation method |
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