CN117997683A

CN117997683A - Data receiving circuit and semiconductor device

Info

Publication number: CN117997683A
Application number: CN202211328242.4A
Authority: CN
Inventors: 李思曼; 严允柱
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-27
Filing date: 2022-10-27
Publication date: 2024-05-07
Also published as: WO2024087540A1

Abstract

The embodiment of the disclosure provides a data receiving circuit and a semiconductor device, the data receiving circuit includes: a plurality of data paths; the ith data path includes: an amplifying circuit configured to amplify a voltage difference between a voltage of input data and a reference voltage and output a first signal pair; a sampling circuit configured to receive a corresponding sampling clock, sample the first signal pair and output a second signal pair; the first coding circuit is configured to receive the second signal pairs output by the N data paths, code all the received second signal pairs, and output a first control signal, wherein N is less than or equal to M; a first adjusting circuit is configured to receive the first control signal and adjust the first signal pair in the ith data path in response to the first control signal. The embodiment of the disclosure can reduce power consumption and improve the transmission speed of the input data while performing decision feedback equalization on the multi-bit input data based on the previous transmission.

Description

Data receiving circuit and semiconductor device

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a data receiving circuit and a semiconductor device.

Background

In memory applications, as signal transmission rates increase faster and clock frequencies increase, the impact of input data channel loss on signal quality increases, which is prone to intersymbol interference (ISI, intersymbol Interference). ISI refers to a phenomenon in which previously transmitted input data affects the transmission of currently transmitted input data due to the limitation of the bandwidth of an input data channel. At present, an equalization circuit is generally used to compensate an input data channel in order to reduce adverse effects caused by intersymbol interference, and the equalization circuit may select CTLE (Continuous TIME LINEAR Equalizer) or DFE (Decision Feedback Equalizer ).

However, the equalization circuit adopted at present is relatively complex, and affects the transmission speed of input data.

Disclosure of Invention

The embodiment of the disclosure provides a data receiving circuit and a semiconductor device, which are at least beneficial to reducing the complexity of the circuit and improving the transmission speed of input data while reducing the problem of intersymbol interference.

According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a data receiving circuit, including: a plurality of data paths each receiving input data and a sampling clock, and each of the data paths receiving a different phase of the sampling clock, the plurality of data paths comprising: the 1 st data path to the M data path are numbered according to the increment of the natural number, the i-th data path is any one data path in the plurality of data paths, i is more than or equal to 1 and less than or equal to M, M is more than or equal to 2, and the phase difference between sampling clocks received by any two data paths with continuous numbers is the same in the 1 st data path to the M data path; wherein the i-th data path includes: an amplifying circuit configured to amplify a voltage difference between the voltage of the input data and a reference voltage and output a first signal pair; a sampling circuit configured to receive the respective sampling clocks, sample the first signal pair, and output a second signal pair; the first coding circuit is configured to receive the second signal pairs output by the N data paths, code all the received second signal pairs, and output a first control signal, wherein N is less than or equal to M; a first adjustment circuit configured to receive the first control signal and adjust the first signal pair in the ith data path in response to the first control signal.

In some embodiments, the first encoding circuit of an i-th data path receives the second signal pairs output by at least two of the data paths other than the i-1 st data path, the first encoding circuit of the 1 st data path receives the second signal pairs output by at least two of the data paths other than the M-th data path; wherein i is more than 1 and less than or equal to M, and M is more than or equal to 3.

In some embodiments, the first encoding circuit of an i-1 th data path receives the second signal pair output by the i-1 th data path and the second signal pair output by the i-1 th data path; the first encoding circuit of the mth data path receives the second signal pair output by the 1 st data path and the second signal pair output by the mth data path.

In some embodiments, the first encoding circuit of the mth data path receives the second signal pair output by the 1 st data path and the second signal pair output by the 2 nd data path; the first coding circuit of the ith data path receives the second signal pair output by the ith data path and the second signal pair output by the (i+1) th data path, i+1 < M; the first encoding circuit of an M-1 data path receives the second signal pair output by the 1 st data path and the second signal pair output by the M-1 st data path.

In some embodiments, M is 4 and the phase difference is 90 °.

In some embodiments, the first encoding circuit of an i-th data path receives the second signal pair comprising the i-th data path output, the first encoding circuit of the 1-th data path receives the second signal pair comprising a 1-th data path output; wherein i is more than 1 and less than or equal to M, and M is more than or equal to 3.

In some embodiments, n=m.

In some embodiments, the second signal pair includes a second data signal and a second complementary data signal, the second data signal and the second complementary data signal being mutually inverted signals; the control signal comprises a first sub-control signal and a second sub-control signal; the first encoding circuit includes: the first sub-coding circuit is used for performing OR operation on the received second data signals to obtain the first sub-control signals; and the second sub-coding circuit is used for carrying out OR operation on the received second complementary data signals to obtain the second sub-control signals.

In some embodiments, the first signal pair includes a first data signal and a first reference data signal, the amplifying circuit includes a first node outputting the first data signal and a second node outputting the first reference data signal; the first adjusting circuit includes: the first control circuit is connected between the first node and the ground terminal and is turned on or turned off according to the second sub-control signal; the second control circuit is connected between the second node and the ground terminal and is turned on or turned off according to the first sub-control signal.

In some embodiments, the first control circuit comprises: the grid electrode of the first NMOS tube receives the first sub-control signal, and the first NMOS tube is connected between the first node and the ground terminal; the second control circuit includes: and the grid electrode of the second NMOS tube receives the second sub-control signal, and the second NMOS tube is connected between the second node and the ground terminal.

In some embodiments, the first adjusting circuit further comprises: the first compensation circuit is connected between the first control circuit and the ground terminal and between the second control circuit and the ground terminal, and the first control circuit and the second control circuit are both connected between the first compensation circuit and the first node, and the first compensation circuit is configured to receive a first tap signal and adjust the first signal pair with a first adjustment value corresponding to the first tap signal.

In some embodiments, the first compensation circuit comprises: and the gates of the third NMOS tubes are connected in parallel, each third NMOS tube receives one bit of data in the first tap signal, and each third NMOS tube is connected between the first control circuit and the ground terminal and between the second control circuit and the ground terminal.

In some embodiments, the first tap signal is based on a summation of the first tap sub-signal and the second tap sub-signal.

In some embodiments, the ith data path further comprises: and a second adjusting circuit configured to receive the second signal pair output by the i-1 th data path and adjust a first signal pair in the i-th data path in response to the received second signal pair, wherein the i-1 th data path is the Mth data path if the i-th data path is the 1 st data path.

In some embodiments, the ith data path further comprises: and a third adjusting circuit configured to receive the second signal pair output by the ith data path and adjust the first signal pair in the ith data path in response to the received second signal pair, wherein the ith data path is the Mth data path if the ith data path is the 2 nd data path, and the ith data path is the Mth data path if the ith data path is the 1 st data path.

In some embodiments, M-N is ≡2; the ith data path further includes: a second encoding circuit configured to receive the second signal pairs output from at least two of the data paths, encode all the received second signal pairs, and output a second control signal; wherein the second encoding circuit and the first encoding circuit respectively receive the second signal pairs output by different data paths; a fourth adjustment circuit configured to receive the second control signal and adjust the first signal pair in the ith data path in response to the second control signal.

In some embodiments, the amplifying circuit includes: the grid electrode of the fourth NMOS tube receives the input data, the drain electrode of the fourth NMOS tube is connected with a working power supply through a first resistor, the drain electrode of the fourth NMOS tube outputs a first data signal, and the source electrode of the fourth NMOS tube is coupled with the ground end; and the grid electrode of the fifth NMOS tube receives the reference voltage, the drain electrode of the fifth NMOS tube is connected with the working power supply through a second resistor, the drain electrode of the fifth NMOS tube outputs a first reference data signal, the source electrode of the fifth NMOS tube is coupled with the ground terminal, and the first reference data signal and the first data signal form the first signal pair.

In some embodiments, the amplifying circuit further comprises: and the grid electrode of the sixth NMOS tube receives the bias signal, the drain electrode of the sixth NMOS tube is connected with the conductive source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube, and the source electrode of the sixth NMOS tube is connected with the ground terminal.

According to some embodiments of the present disclosure, there is provided a semiconductor device including: the data receiving circuit provided in any one of the above embodiments.

In some embodiments, a semiconductor device includes a memory chip.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

In the technical scheme of the data receiving circuit provided by the embodiment of the disclosure, a plurality of data paths receive sampling clocks with different phases to transmit input data; any one of the data paths comprises an amplifying circuit, a sampling circuit, a first coding circuit and a first regulating circuit, wherein the first coding circuit receives second signal pairs output by N data paths and carries out coding processing to obtain a first control signal, the first control signal can represent the influence of the second signals output by N data paths on intersymbol interference of currently transmitted input data, and the first regulating circuit responds to the first control signal to regulate the first signal pairs output by the amplifying circuit, namely carries out decision feedback equalization, so as to reduce the influence of the previously transmitted input data on the currently transmitted input data and ensure the accuracy of the transmission of the input data. In addition, compared with the scheme of designing an adjusting circuit for each second signal pair, the first adjusting circuit of the embodiment of the disclosure has lower complexity and the area required by the first adjusting circuit is correspondingly smaller, thereby being beneficial to reducing the load of the data receiving circuit, improving the input data transmission rate, reducing the power consumption and the transmission delay.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings do not depict a proportional limitation unless expressly stated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a functional block diagram of a data receiving circuit including a 4-tap equalization circuit;

FIG. 2 is a schematic diagram corresponding to FIG. 1;

FIG. 3 is a schematic diagram of a circuit configuration of the 4-tap equalization circuit of FIG. 1;

FIG. 4 is a functional block diagram of a data receiving circuit provided by an embodiment of the present disclosure;

FIG. 5 is a functional block diagram of the ith data path of FIG. 4;

FIG. 6 is another functional block diagram of a data path in a data receiving circuit;

FIG. 7 is yet another functional block diagram of a data path in a data receiving circuit;

FIG. 8 is yet another functional block diagram of a data path in a data receiving circuit;

fig. 9-12 are several different functional block diagrams of data receiving circuits;

FIG. 13 is a schematic diagram of a circuit configuration of the amplifying circuit and the first adjusting circuit in any one of the data paths;

FIG. 14 is a schematic diagram of a circuit structure of the first sub-compensation circuit or the second sub-compensation circuit in FIG. 13;

FIG. 15 is a schematic diagram of another circuit configuration of the amplifying circuit and the first adjusting circuit in any one of the data paths;

FIG. 16 is a schematic diagram showing another configuration of the amplifying circuit, the first control circuit, the second control circuit, and the first compensation circuit in any one of the data paths;

fig. 17 is a schematic circuit diagram of a sampling circuit.

Detailed Description

According to the difference of bit numbers of input data participating in the DFE in the previously transmitted input data, an equalization circuit in the data receiving circuit may be divided into 1-tap, 2-tap, 3-tap and 4-tap equalization circuits, and the equalization circuit may even have more (i.e., tap number may be greater than 4) taps, which are taps, it may be understood that the equalization circuit may include a plurality of tap adjusting circuits, each tap adjusting circuit corresponding to a tap signal, one tap signal corresponding to one bit data, and the currently transmitted input data is adjusted according to the tap signal. Wherein, 1-tap refers to the 1-bit data transmitted previously to participate in the DFE;2-tap means that 2 bits of data previously transmitted participate in DFE;3-tap refers to the participation of previously transmitted 3-bit data in the DFE; the 4-tap means that 4 bits of data previously transmitted participate in the DFE.

In general, each tap adjusting circuit in the equalizing circuit needs to be designed into a corresponding circuit, the more taps in the equalizing circuit are, the larger the circuit volume needed by the corresponding equalizing circuit is, the larger the corresponding load of the equalizing circuit is, the feedback speed of the DFE is affected, and the delay of the DFE is also increased. In the following, a 4-tap equalization circuit will be described as an example, fig. 1 is a functional block diagram of a data receiving circuit including the 4-tap equalization circuit, fig. 2 is a schematic diagram corresponding to fig. 1, and fig. 3 is a schematic circuit diagram of the 4-tap equalization circuit in fig. 1.

Referring to fig. 1 and 2, taking an example in which a data receiving circuit sequentially samples and transmits input data based on sampling phases of 0 °,90 °, 180 °, 270 ° of an input data sampling clock DQS, the data receiving circuit includes 4 data paths, each having an amplifying circuit 11, an equalizing circuit 12, and a sampling circuit 13, wherein the amplifying circuit 11 and the equalizing circuit 12 may be integrated in the same module 10, and T1, T2, T3, and T4 represent tap signals of tap adjusting circuits corresponding to previous 1 st bit data, 2 nd bit data, 3 rd bit data, and 4 th bit data, respectively, wherein "previous" herein is with reference to currently transmitted input data. The amplifying circuit 11 receives the input data IN and the reference voltage VREF, and the 4 sampling circuits 13 output out_0, out_90, out_180, and out_270, respectively.

For the first data path, the sampling phases of the sampling clocks DQS are 0 °, and T1, T2, T3 and T4 are out_270, out_180, out_90 and out_0[ n-1], respectively, where out_0[ n-1] refers to the input data output by the sampling circuit 13 in response to the sampling clock with the sampling phase of 0 ° in the previous clock cycle, where the previous clock cycle is the sampling time corresponding to the input data currently transmitted by the first data path; for the second data path, the sampling phase is 90 °, and T1, T2, T3, and T4 are out_0, out_270, out_180, and out_90[ n-1], respectively, and out_90[ n-1] refers to input data output by the sampling circuit 13 at the previous clock cycle in response to the sampling clock having the sampling phase of 90 °. For the third data path, the sampling phase is 180 °, and T1, T2, T3, and T4 are out_90, out_0, out_270, and out_180[ n-1], respectively, and out_180[ n-1] refers to input data output by the sampling circuit 13 in the previous clock cycle in response to the sampling clock having the sampling phase of 180 °. For the fourth data path, the sampling phases are 270 °, T1, T2, T3, and T4 are out_180, out_90, out_0, and out_270[ n-1], respectively, and out_270[ n-1] refers to input data output by the sampling circuit 13 at the previous clock cycle in response to the sampling clock having the sampling phase of 270 °.

Taking the equalization circuit provided in the 4 th data path as an example, referring to fig. 1 to 3 in combination, the amplification circuit 11 has a first node N1 and a second node N2, the equalization circuit 12 includes 4 tap adjustment circuits 14, and each tap adjustment circuit 14 includes: the first NMOS tube and the second NMOS tube respectively receive one of two differential signals in input data output by the sampling circuit 13, and the drain electrodes are respectively connected with the first node N1 and the second node N2; the third NMOS tube group comprises a plurality of third NMOS tubes connected in parallel, the fourth NMOS tube group comprises a plurality of fourth NMOS tubes connected in parallel, the grid electrodes of the third NMOS tubes and the fourth NMOS tubes all receive one bit of data in the tap signal, the third NMOS tube group is connected between the first NMOS tube and the ground end, and the fourth NMOS tube group is connected between the second NMOS tube and the ground end. It will be appreciated that in some examples, the third NMOS nest and the fourth NMOS nest may also be the same NMOS nest.

For the Tap adjusting circuit corresponding to T1, the two differential signals are Tap1_data and Tap1_datab respectively, the Tap signal is Tap1_ coeffi <5:0>, and correspondingly, the Tap signal Tap1_ coeffi <5:0> simultaneously controls the third NMOS tube group and the fourth NMOS tube group; for the Tap adjusting circuit corresponding to T2, the two differential signals are Tap2_data and Tap2_datab respectively, the Tap signal is Tap2_ coeffi <4:0>, and correspondingly, the Tap signal Tap2_ coeffi <4:0> simultaneously controls the third NMOS tube group and the fourth NMOS tube group; for the Tap adjusting circuit corresponding to T3, the two differential signals are Tap3_data and Tap3_datab respectively, the Tap signal is Tap3_ coeffi <4:0>, and correspondingly, the Tap signal Tap3_ coeffi <4:0> simultaneously controls the third NMOS tube group and the fourth NMOS tube group; for the Tap adjusting circuit corresponding to T4, the two differential signals are Tap4_data and Tap4_datab, the Tap signal is Tap4_ coeffi <3:0>, and correspondingly, the Tap signal Tap4_ coeffi <3:0> simultaneously controls the third NMOS tube group and the fourth NMOS tube group.

From the above analysis, it is known that, for any data path, the number of tap adjustment circuits required is the same as the number of bits of the input data participating in the DFE, the greater the number of corresponding tap adjustment circuits, the greater the area size of the corresponding tap adjustment circuits occupying the data receiving circuit, which will affect the transmission speed of the input data, and the speed of DFE feedback will be slower, i.e., the delay of the DFE will also be greater. In addition, the total amount of the third NMOS pipe group and the fourth NMOS pipe group in the corresponding tap adjusting circuit also becomes large, so that the load of the data receiving circuit becomes large, which also affects the transmission speed of the input data of the data receiving circuit.

The embodiment of the disclosure provides a data receiving circuit, which performs coding processing on multi-bit input data in input data transmitted previously to obtain a first control signal, and a first adjusting circuit performs decision feedback equalization on the input data transmitted currently in response to the first control signal so as to reduce the influence of intersymbol interference, and save the complexity of a circuit required for realizing a DFE, thereby reducing the circuit area, reducing the circuit load, further reducing the power consumption of the data receiving circuit, and improving the transmission speed of the input data.

Fig. 4 is a functional block diagram of a data receiving circuit according to an embodiment of the present disclosure, and fig. 5 is a functional block diagram of an i-th data path in fig. 4.

Referring to fig. 4 and 5, in an embodiment of the present disclosure, a data receiving circuit includes: a plurality of data paths 100, each of the plurality of data paths 100 receiving input data IN and a sampling clock CLK, and each of the plurality of data paths 100 receiving a sampling clock CLK having a different phase, the plurality of data paths 100 comprising: the 1 st data path to the M data path are numbered according to the increment of the natural number, the i-th data path is any data path 100 in a plurality of data paths 100, i is not less than 1 and not more than M, M is not less than 2, and the phase difference between sampling clocks CLK received by any two data paths 100 with continuous numbers is the same in the 1 st data path to the M data path; wherein the ith data path includes: an amplifying circuit 101 configured to amplify a voltage difference between a voltage of the input data IN and a reference voltage VREF and output a first signal pair OUT1; a sampling circuit 102 configured to receive a corresponding sampling clock CLK, sample the first signal pair OUT1 and output a second signal pair OUT2; a first encoding circuit 103 configured to receive the second signal pairs OUT2 output by the N data paths, encode all the received second signal pairs OUT2, and output a first control signal TapA, N being equal to or less than M; the first adjusting circuit 104 is configured to receive the first control signal TapA and adjust the first signal pair OUT1 in the ith data path in response to the first control signal TapA.

In the above data receiving circuit, for any one data path 100, the second signal pair OUT2 output by the N data paths 100 is the previously transmitted input data, and the previously transmitted N input data may participate in the adjustment of the first signal pair OUT1 transmitted by the data path 100, so as to reduce the interference of the previously transmitted input data on the data path currently transmitting the input data, and implement the DFE function. And, the first encoding circuit 103 encodes the second signals output by the N data paths 100 to obtain the first control signal TapA, so that the influence of the N input data transmitted previously on the input data transmitted currently is converted into the influence of the first control signal TapA on the input data transmitted currently; accordingly, the first adjusting circuit 104 is responsive to the first control signal TapA to adjust the first signal pair OUT 1in the data path of the currently transmitted input data, thereby reducing the intersymbol interference of the previously transmitted N input data to the data path of the currently transmitted input data and improving the accuracy of the input data transmission. The first adjusting circuit 104 can respond to a plurality of previously transmitted input data to adjust, so that an independent adjusting circuit is not required to be designed for each previously transmitted input data which needs to participate in the DFE function, which is beneficial to reducing the complexity of circuits required by an input data transmission path for realizing the DFE function, reducing the size of the circuits, reducing the load of the first adjusting circuit 104, improving the adjusting speed of the first signal on the OUT1 and reducing the delay of the first signal on the OUT1, and further reducing the load of the data receiving circuit and improving the transmission speed of the input data while ensuring that all previously transmitted multi-bit input data participate in the DFE to improve the transmission accuracy of the input data.

The data receiving circuit provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

The data receiving circuit may be applied to a memory, which may be DRAM (Dynamic Random Access Memory ) or SRAM (Static Random Access Memory, static random access memory). In some embodiments, the Data receiving circuit may be applied to SDRAM (Synchronous Dynamic Random Access Memory ), which may be DDR (Double Data Rate) SDRAM, such as DDR4 memory, DDR5 memory, DDR6 memory, LPDDR4 memory, LPDDR5 memory, or LPDDR6 memory.

Referring to fig. 5, IN some embodiments, the second signal pair OUT2 includes a second data signal OUT2_o and a second complementary data signal OUT2_e, and the second data signal OUT2_o and the second complementary data signal OUT2_e are mutually inverted signals, wherein a level of the second data signal OUT2_o is used to reflect a level of the input data IN, that is, the input data is 0 and the second data signal OUT2_o is 0, and the input data is 1 and the second data signal OUT2_o is 1. Accordingly, the first control signal TapA includes a first sub-control signal TapA1 and a second sub-control signal TapA, wherein the first sub-control signal TapA is obtained by performing the encoding process based on all the received second data signals OUT2_o, and the second sub-control signal TapA2 is obtained by performing the encoding process based on all the received second complementary data signals OUT 2_e. It will be appreciated that the same coding scheme is used for both "coding processes" herein.

Referring to fig. 5, the first encoding circuit 103 may be configured to perform an or operation on OUT2 of all the received second signals, that is, the encoding process performed by the first encoding circuit 103 is an or operation, to obtain the first control signal TapA. The first encoding circuit 103 may include a first sub-encoding circuit 113 and a second sub-encoding circuit 123, where the first sub-encoding circuit 113 is configured to perform an or operation on all received second data signals out2_o to obtain a first sub-control signal TapA, and the second sub-encoding circuit 123 is configured to perform an or operation on all received second complementary data signals out2_e to obtain a second sub-control signal TapA2. The first encoding circuit 103 may be implemented as an or circuit.

It can be appreciated that if all the received second data signals out2_o are 0, the first sub-control signal TapA is also 0 correspondingly; if at least one of the received second data signals OUT 2O is 1, the first sub-control signal TapA is also 1. If all the received second complementary data signals OUT 2E are 0, the second sub-control signals are also 0 correspondingly; if at least one of the received second complementary data signals OUT2_E is 1, the second sub-control signal TapA is also 1.

In some examples, the first signal pair OUT1 may include a first data signal OUT 1O and a first reference data signal OUT 1E, and the amplifying circuit 101 includes a first node net1 and a second node net2, respectively, the first node net1 outputting the first data signal OUT 1O and the second node net2 outputting the first reference data signal OUT 1E. If the input data is 1, the voltage of the input data IN is greater than the reference voltage VREF, the voltage of the first data signal out1_o is less than the voltage of the first reference data signal out1_e, and the voltage of the corresponding second data signal out2_o is greater than the voltage of the second complementary data signal out2_e; if the input data IN is 0, the voltage of the input data IN is smaller than the reference voltage, the voltage of the first data signal out1_o is larger than the voltage of the first reference data signal out1_e, and the voltage of the corresponding second data signal out2_o is smaller than the voltage of the second complementary data signal out2_e. Wherein the first adjusting circuit 104 adjusts the voltage of the second node net2 in response to the first sub-control signal TapA1, i.e., the first adjusting circuit 104 adjusts the first reference data signal OUT 1-E in response to the first sub-control signal TapA 1; the first adjusting circuit 104 adjusts the voltage of the first node net1 in response to the second sub-control signal TapA2, i.e., the first adjusting circuit 104 adjusts the first data signal OUT 1O in response to the second sub-control signal TapA 2.

It is understood that the amplifying circuit 101 may be configured to discharge between the first node net1 and the ground IN response to the input data IN, i.e., the voltage of the first node net1 (the voltage of the first data signal out1_o) is pulled down, and the higher the voltage of the input data IN, the faster the first node net1 is pulled down, i.e., the faster the discharge speed between the first node net1 and the ground; and is further configured to discharge between the second node net2 and the ground terminal in response to the reference voltage VREF, i.e. the voltage of the second node net2 (the voltage of the first reference data signal out1_e) is pulled down, wherein the reference voltage VREF may be a fixed value, and accordingly, the influence of the reference voltage VREF on the discharge speed between the second node net2 and the ground terminal is unchanged on the premise that the first regulating circuit does not regulate the second node net 2.

The principle of the first adjusting circuit 104 adjusting the first signal pair OUT1 will be described below:

Specifically, if all the second data signals out2_o are received and all the second complementary data signals out2_e are received and all the first sub-control signals TapA and TapA are respectively 0 and 1, the first adjusting circuit 104 may be active as a high level signal, and the first adjusting circuit 104 adjusts the voltage of the first node net1 in response to the second sub-control signals TapA 2. On this premise, there are two cases:

The input data IN received by the ith data path is 0, and all the second data signals out2_o received by the first encoding circuit 103 are the same as the currently transmitted input data, but no intersymbol interference is caused, IN which case the first adjusting circuit 104 still adjusts the voltage of the first node net1 IN response to the second sub-control signal TapA to pull down the level of the first data signal out1_o of the first node net 1. Or the input data IN received by the ith data path is 1, that is, the currently transmitted input data is different from all the second data signals out2_o received by the first encoding circuit 103, and when a decision feedback equalization adjustment is needed, the first adjusting circuit 104 adjusts the voltage of the first node net1 IN response to the second sub control signal TapA2, so that the level of the first data signal out1_o becomes lower, that is, the speed at which the voltage of the first node net1 is pulled down becomes faster, thereby further pulling the level difference between the first data signal out1_o and the first reference data signal out1_e, so that the input data "1" is transmitted more accurately.

If all the second data signals out2_o are received as1, all the corresponding received second complementary data signals out2_e are 0, the first sub-control signal TapA is 1, the second sub-control signal TapA is 0, the first adjusting circuit 104 may be active high, and the first adjusting circuit 104 adjusts the voltage of the second node net2 in response to the first sub-control signal TapA 1. On this premise, there are two cases:

The input data IN received by the ith data path is 0, i.e. the currently transmitted input data is different from all the second data signals out2_o received by the first encoding circuit 103, and then decision feedback equalization adjustment is needed, the first adjusting circuit 104 adjusts the voltage of the second node net2 IN response to the first sub-control signal TapA1, so that the level of the first reference data signal out1_e becomes lower, i.e. the speed at which the voltage of the second node net2 is pulled down becomes faster, thereby further pulling the level difference between the first data signal out1_o and the first reference data signal out1_e, so that the input data "0" is transmitted more accurately. Or the i-th data path receives the input data IN of 1, i.e. the currently transmitted input data is identical to all the second data signals out2_o received by the first encoding circuit 103, all the second data signals out2_o received by the first encoding circuit 103 will not cause intersymbol interference, IN which case the first adjusting circuit 104 will still pull down the voltage of the second node net2 IN response to the first sub-control signal TapA 1.

If at least one 1 and at least one 0 are included in all the received second data signals out2_o, at least one 1 and at least one 0 are included in all the received second complementary data signals out2_e, the first sub-control signal TapA is 1, the second sub-control signal TapA2 is 1, the first adjusting circuit 104 may be active high, the first adjusting circuit 104 adjusts the voltage of the second node net2 in response to the first sub-control signal TapA1, and the first adjusting circuit 104 adjusts the voltage of the first node net1 in response to the second sub-control signal TapA. On this premise, there are two cases:

The i-th data path receives input data IN of 0, i.e. the currently transmitted input data is different from at least one of all the second data signals out2_o received by the first encoding circuit 103, the first adjusting circuit 104 adjusts the voltage of the second node net2 IN response to the first sub control signal TapA so that the speed at which the voltage of the second node net2 is pulled down becomes fast, and the first adjusting circuit 104 adjusts the voltage of the first node net1 IN response to the second sub control signal TapA so that the speed at which the voltage of the first node net1 is pulled down also becomes fast; the control may be performed by adding the first compensation circuit operating in response to the first tap signal, increasing the difference in speed on the premise of ensuring that the speed at which the first node net1 is pulled down is less than the speed at which the second node net2 is pulled down, thereby pulling the voltage difference between the first data signal OUT1_ O and the first reference data signal OUT1_ E while ensuring that the level of the first data signal OUT1_ O is greater than the level of the first reference data signal OUT1_ E, so that the input data "0" is more accurately transmitted.

Or the input data IN received by the ith data path is 1, that is, the currently transmitted input data is different from at least one signal of all the second data signals out2_o received by the first encoding circuit 103, the first adjusting circuit 104 adjusts the voltage of the second node net2 IN response to the first sub control signal TapA so that the speed at which the voltage of the second node net2 is pulled down becomes fast, and the first adjusting circuit 104 adjusts the voltage of the first node net1 IN response to the second sub control signal TapA so that the speed at which the voltage of the first node net1 is pulled down becomes fast; the control can be performed by increasing the first tap signal, and the difference between the speeds is increased on the premise of ensuring that the speed at which the first node net1 is pulled down is greater than the speed at which the second node net2 is pulled down, so that the voltage difference between the first data signal OUT1_ O and the first reference data signal OUT1_ E is pulled apart while the level of the first data signal OUT1_ O is ensured to be less than the level of the first reference data signal OUT1_ E, so that the input data "1" is more accurately transmitted.

It can be appreciated that if the first sub-control signal TapA and the second sub-control signal TapA are both 1, the speed at which the voltage of the first node net1 and the voltage of the second node net2 are pulled down becomes faster, which is beneficial to increasing the speed of the input data transmission, i.e. reducing the time required for the sampling circuit to output the second signal pair OUT 2.

The "0" refers to the level of the corresponding signal being low, i.e., defined as logic "0", and the "1" refers to the level of the corresponding signal being high, i.e., defined as logic "1"; the "low level" and "high level" are the level values with respect to the reference level, and are higher than the reference level, i.e., high level, and lower than the reference level, i.e., low level.

Based on the above analysis, at least one of the first sub-control signal TapA and the second sub-control signal TapA is 1, the first adjusting circuit 104 pulls the level of the second node net2 low when the first sub-control signal TapA is 1, such that the first data signal OUT1_o is further greater than the first reference data signal OUT1_e, and the first adjusting circuit 104 pulls the level of the first node net1 when the second sub-control signal TapA is 1, such that the first data signal OUT1_o is further less than the first reference data signal OUT1_e, that is, the first adjusting circuit 104 pulls the level of the first node net1 and/or the level of the second node net2 low. When the input data IN received by the ith data path is 1, the first adjusting circuit 104 of the ith data path further pulls down the level of the first node net1, so that the first data signal out1_o is further smaller than the first reference data signal out1_e, which is beneficial to further increasing the accuracy of the transmission of the input data IN by the ith data path; when the input data IN received by the ith data path is 0, the first adjusting circuit 104 pulls the level of the second node net2 low, so that the first data signal out1_o is further greater than the first reference data signal out1_e, which is beneficial to further increasing the accuracy of the transmission of the input data IN by the ith data path. In some embodiments, the data receiving circuit may be a dual-ended transmission circuit, that is, the second signal pair OUT2 output by the data receiving circuit includes a second data signal OUT2_o and a second complementary data signal OUT2_e that are opposite to each other. It will be appreciated that in other embodiments, the data receiving circuit may be a single-ended transmission circuit, and accordingly, the second signal pair may also include a second data signal and a second complementary data signal, where the second data signal is a signal actually output by the sampling circuit, and the second complementary data signal is a signal obtained by performing inversion processing based on the output second data signal, and accordingly, the ith data path may also include: and the inverting circuit is used for generating a second complementary data signal according to the second data signal.

The data receiving circuit includes M data paths, where M is greater than or equal to 2, and may include, for example, 2 data paths each having 2 sampling clocks with different phases, 3 data paths each having 3 sampling clocks with different phases, 4 data paths each having 4 sampling clocks with different phases, and 6 or 8 data paths each having 6 or 8 sampling clocks with different phases.

In some embodiments, the first encoding circuit 103 of the ith data path 100 may receive the second signal pair OUT2 output by at least two data paths 100 other than the ith data path 100, and the first encoding circuit 103 of the 1 st data path 100 may receive the second signal pair OUT2 output by at least two data paths 100 other than the mth data path 100; wherein i is more than 1 and less than or equal to M, and M is more than or equal to 3. Because the second signal pair OUT2 output by the i-1 data path 100 is the input data signal that is closest IN time to the currently transmitted input data, the intersymbol interference caused by the second signal pair OUT2 output by the i-1 data path 100 to the input data IN that needs to be transmitted by the i-1 data path 100 is the most serious, and therefore, an independent second adjusting circuit can be designed for the second signal pair OUT2 output by the i-1 data path 100, so that the second adjusting circuit responds to the second signal pair OUT2 output by the i-1 data path 100 to adjust the first signal pair OUT1 of the i-1 data path 100, which is beneficial to further improve the effect of eliminating the intersymbol interference.

In a specific example, m=3, the first encoding circuit 103 of the 2 nd data path 100 may receive the second signal pair OUT2 output by the 2 nd data path 100 and the 3 rd data path 100, respectively, and the first encoding circuit 103 of the 3 rd data path 100 may receive the second signal pair OUT2 output by the 1 st data path 100 and the 3 rd data path 100, respectively. It will be appreciated that the first encoding circuit 103 of the 3 rd data path 100 may receive the input data signal at the current time from the 1 st data path 100 and the second signal pair OUT2 output by the 3 rd data path 100, and the first encoding circuit 103 receives the second signal pair OUT2 output by the 3 rd data path 100 in the previous clock cycle. For example, the 3 rd data path 100 receives the input data IN to be sampled and output IN the sampling phase of the second clock cycle, and the first encoding circuit 103 of the 3 rd data path 100 receives the second signal pair OUT2 of the sampling phase sampling output of the first clock cycle. It should be noted that, the following similar descriptions may refer to the descriptions herein, and will not be repeated.

In some examples, M.gtoreq.4, the first encoding circuit 103 of the ith data path 100 receives the second signal pair OUT2 output by all data paths 100 except the ith-1 data path 100, and the first encoding circuit 103 of the 1 st data path 100 receives the second signal pair OUT2 output by all data paths 100 except the Mth data path 100. That is, the second signal pairs OUT2 output by all of the data paths 100 except the second signal pair OUT2 output by the i-1 th data path 100 are used to generate the first control signal TapA corresponding to the i-th data path 100; the second signal pairs OUT2 output by all of the data paths 100 except the second signal pair OUT2 output by the mth data path 100 are used to generate the first control signal TapA corresponding to the 1 st data path 100. In a specific example, m=4, the first encoding circuit 103 of the 2 nd data path 100 may receive three second signals respectively output by the 2 nd data path 100, the 3 rd data path 100, and the 4 th data path 100; the first encoding circuit 103 of the 3 rd data path 100 may receive the second signal pair OUT2 output by the 1 st data path 100, the 3 rd data path 100, and the 4 th data path 100, respectively; the first encoding circuit 103 of the 4 th data path 100 may receive the second signal pair OUT2 output from the 1 st data path 100, the 2 nd data path 100, and the 4 th data path 100, respectively.

In other examples, the first encoding circuit 103 of the i-1 data path 100 receives the second signal pair OUT2 output by the i-1 data path 100 and the second signal pair OUT2 output by the i-1 data path 100; the first encoding circuit 103 of the mth data path 100 receives the second signal pair OUT2 output by the 1 st data path 100 and the second signal pair OUT2 output by the mth data path 100. Benefits of such an arrangement include: for the i-1 data path 100, the i-1 data path 100 and the second signal pair OUT2 output by the i-1 data path 100 cause less intersymbol interference to the i-1 data path 100 than the remaining data paths 100, so that selecting two second signals with less intersymbol interference to encode OUT2 to obtain the first control signal TapA is beneficial for further ensuring the capability of further improving the intersymbol interference while reducing the complexity of the equalization circuit, while for the i-1 data path 100, an independent adjusting circuit can be designed for OUT2 for the remaining data paths 100 other than the i-1 data path 100 and the i-1 data path 100, which adjusts OUT1 for the first signal pair OUT1 of the i-1 data path 100 in response to the received second signal pair OUT2.

For example, m=4, the first encoding circuit 103 of the 2 nd data path 100 may receive the second signal pair OUT2 output by the 2 nd data path 100 and the 3 rd data path 100, respectively. Benefits of such an arrangement include: compared to the 4 th data path 100, the second signal pair OUT2 output by the 2 nd data path 100 and the 3 rd data path 100 causes less intersymbol interference to the 2 nd data path 100, so that the two second signal pairs OUT2 with less intersymbol interference are selected to be encoded to obtain the first control signal TapA, which is beneficial to further ensure the capability of further improving the intersymbol interference while reducing the complexity of the equalization circuit, while for the 2 nd data path 100, an independent second adjusting circuit can be designed for the second signal pair OUT2 output by the 1 st data path 100, an independent third adjusting circuit can be designed for the second signal pair OUT2 output by the 4 th data path 100, the second adjusting circuit adjusts the first signal pair OUT1 of the 2 nd data path 100 in response to the second signal pair OUT2 output by the 1 st data path 100, and the third adjusting circuit adjusts the first signal pair OUT1 of the 2 nd data path 100 in response to the second signal pair OUT2 output by the 4 th data path 100. It is understood that the first encoding circuit 103 of the 2 nd data path 100 may receive any 2 of the three second signal pairs OUT2 output by the 2 nd data path 100, the 3 rd data path 100, and the 4 th data path 100, respectively, for example, the first encoding circuit 103 of the 2 nd data path 100 may also receive the second signal pair OUT2 output by the 2 nd data path 100 and the 4 th data path 100, respectively, or receive the second signal pair OUT2 output by the 3 rd data path 100 and the 4 th data path 100, respectively, or receive the second signal pair OUT2 output by the 2 nd data path 100 and the 3 rd data path 100, respectively.

M=4, the first encoding circuit 103 of the 3rd data path 100 may receive any 2 second signal pairs OUT2 of the three second signal pairs OUT2 output by the 1 st data path 100, the 3rd data path 100, and the 4 th data path 100, respectively, for example, may receive the second signal pairs OUT2 output by the 3rd data path 100 and the 4 th data path 100, respectively; the first encoding circuit 103 of the 4 th data path 100 may receive any 2 second signal pairs OUT2 of the second signal pairs OUT2 output by the 1 st data path 100, the 2 nd data path 100, and the 4 th data path 100, respectively, for example, may receive the second signal pairs OUT2 output by the 1 st data path 100 and the 4 th data path 100, respectively; the first encoding circuit 103 of the 1 st data path 100 may receive any 2 second signal pairs OUT2 of the three second signal pairs OUT2 output by the 1 st data path 100, the 2 nd data path 100, and the 3rd data path 100, respectively, for example, may receive the second signal pairs OUT2 output by the 1 st data path 100 and the 2 nd data path 100, respectively. Regarding the effects of such an arrangement, reference is made to the corresponding description in the previous paragraph, and no further description is given here.

It will be appreciated that in the above example, for any of the data paths 100, the previously transmitted 4-bit data may all participate in decision feedback equalization for the currently transmitted input data, i.e., the data receiving circuit has a 4-tap equalization circuit. In other examples, for any data path 100, it may be also set that the previously transmitted 3-bit data participates in the decision feedback equalization of the currently transmitted input data, that is, the data receiving circuit has a 3-tap equalization circuit, and accordingly, the first encoding circuit 103 of the ith data path 100 may receive the second signal pair OUT2 output by two data paths 100 except for the ith data path 100 and the ith data path 100, and the first encoding circuit 103 of the 1 st data path 100 may receive the second signal pair OUT2 output by two data paths 100 except for the 1 st data path 100 and the mth data path 100.

In some embodiments, the first encoding circuit 103 of the mth data path 100 may receive the second signal pair OUT2 output by the 2 nd data path 100 and the second signal pair OUT2 output by the 3 rd data path 100; the first encoding circuit 103 of the i-1 data path 100 receives the second signal pair OUT2 output by the i-1 data path 100 and the second signal pair OUT2, i+1 < M output by the i+1 data path 100; the first encoding circuit 103 of the M-1 data path 100 receives the second signal pair OUT2 output by the 1 st data path 100 and the second signal pair OUT2 output by the M-1 st data path 100. The sampling clock CLK may still have 4 different phases, i.e. M may be 4.

For a scheme in which the data receiving circuit has a 3-tap equalization circuit and has 4 data paths 100, in a specific example, the first encoding circuit 103 of the 1 st data path 100 may receive the second signal pair OUT2 output by the 2 nd data path 100 and the 3 rd data path 100 respectively, the 1 st data path 100 may further include a second adjusting circuit, and the second adjusting circuit may receive the second signal pair OUT2 output by the 4 th data path 100 to adjust the first signal pair OUT1 output by the 1 st data path 100; the first encoding circuit 103 of the 2 nd data path 100 receives the second signal pair OUT2 output by the 3 rd data path 100 and the 4 th data path 100 respectively, and the 2 nd data path 100 may further include a second adjusting circuit that receives the second signal pair OUT2 output by the 1 st data path 100 to adjust the first signal pair OUT1 output by the 2 nd data path 100; the first encoding circuit 103 of the 3 rd data path 100 may receive the second signal pair OUT2 output by the 1 st data path 100 and the 4 th data path 100, respectively, and the 3 rd data path 100 may further include a second adjusting circuit that receives the second signal pair OUT2 output by the 2 nd data path 100 to adjust the first signal pair OUT1 output by the 1 st data path 100; the first encoding circuit 103 of the 4 th data path 100 receives the second signal pair OUT2 output by the 2 nd data path 100 and the 3 rd data path 100, respectively; the 4 th data path 100 may further include a second adjusting circuit that receives the second signal pair OUT2 output by the 3 rd data path 100 to adjust the first signal pair OUT1 output by the 4 th data path 100.

It will be appreciated that in some embodiments, N may be equal to M, that is, the first encoding circuit 103 of the ith data path 100 may receive the second signal pairs OUT2 output by all the data paths 100 to obtain the first control signal TapA, so that the equalization circuit required by the data receiving circuit may be further simplified without considering the high capability of resisting intersymbol interference, further reducing the load, and further improving the input data transmission speed.

As analyzed above, M may be 4 in some embodiments, the phase difference between the sampling clocks received by any two numbered consecutive data paths is 90 °, e.g., the phase of the sampling clock received by the 1 st data path is 0 °, the phase of the sampling clock received by the 2 nd data path is 90 °, the phase of the sampling clock received by the 3 rd data path is 180 °, and the phase of the sampling clock received by the 4 th data path is 270 °. In other embodiments, the phase difference between the sampling clocks received by any two consecutive numbered data paths may also be 45 °, for example, the phase of the sampling clock received by the 1 st data path is 0 °, the phase of the sampling clock received by the 2 nd data path is 45 °, the phase of the sampling clock received by the 3 rd data path is 90 °, the phase of the sampling clock received by the 4 th data path is 135 °, and the phase of the sampling clock received by the 5 th data path is 180 °.

The first encoding circuit 103 of the ith data path 100 may receive the second signal pair OUT2 including the output of the ith data path 100, and the first encoding circuit 103 of the 1 st data path 100 receives the second signal pair OUT2 including the output of the 1 st data path 100, wherein 1 < i.ltoreq.M, M.gtoreq.3. It will be appreciated that the i-th data path 100 receives input data at the current time, and the first encoding circuit 103 of the i-th data path 100 receives the output second signal pair OUT2 which is the output second signal pair OUT2 of the i-th data path for a previous time period compared to the current time. For example, the i-th data path 100 receives input data in the 4 th clock cycle, that is, the current time is in the 4 th clock cycle (or, the i-th data path 100 receives input data to be sampled and output in the sampling phase of the 4 th clock cycle), and the first encoding circuit 103 of the i-th data path 100 receives the second signal pair OUT2 sampled and output by the i-th data path 100 in the sampling phase of the 3 rd clock cycle. It will be appreciated that, for the ith data path 100, the time interval between the time of the previous transmission of the input data by the ith data path 100 and the time of the current transmission of the input data by the ith data path 100 is longer than the interval between the time of the transmission of the input data by the rest of the data paths 100 and the time of the current transmission of the input data by the ith data path 100, that is, the influence of the previous transmission of the input data by the ith data path 100 on the intersymbol interference caused by the current transmission of the input data is relatively smaller, and the input data of the previous transmission of the ith data path 100 is taken as one of the input data for acquiring the first control signal TapA, which not only ensures that the input data with the least influence on the intersymbol interference can participate in the decision feedback equalization to adjust the first signal pair OUT1, but also reduces the complexity of the circuits required for participating in the decision feedback equalization.

In some embodiments, the first encoding circuit 103 of the ith data path 100 receives the second signal pair OUT2 output by at least two data paths 100 other than the ith-1 data path 100, and the first encoding circuit 103 of the 1 st data path 100 receives the second signal pair OUT2 output by at least two data paths 100 other than the mth data path 100; in addition, the first encoding circuit 103 of the ith data path 100 may receive the second signal pair OUT2 including the output of the ith data path 100, and the first encoding circuit 103 of the 1 st data path 100 receives the second signal pair OUT2 including the output of the 1 st data path 100, wherein 1 < i.ltoreq.M, M.gtoreq.3.

Fig. 6 is another functional block diagram of a data path in a data receiving circuit. Referring to fig. 6, the i-th data path 100 may further include: the second adjusting circuit 105 is configured to receive the second signal pair OUT2 output by the i-1 th data path 100 and adjust the first signal pair OUT1 in the i-1 th data path 100 in response to the received second signal pair OUT2, wherein the i-1 th data path 100 is the M-th data path 100 if the i-1 th data path 100 is the 1 st data path 100. As can be seen from the foregoing analysis, the second signal pair OUT2 output by the i-1 data path 100 is the input data having the greatest influence on the input data currently transmitted by the i-1 data path 100, that is, the 1 st bit data previously transmitted has the greatest influence on the intersymbol interference caused by the input data currently transmitted, so that the independent second adjusting circuit 105 may be configured such that the second adjusting circuit 105 responds to the second signal pair OUT2 output by the i-1 data path 100 to adjust the first signal pair OUT1 of the i-1 data path 100, thereby reducing the influence of the intersymbol interference caused by the previous bit data on the input data currently transmitted and further improving the accuracy of the input data transmission.

In a specific example, taking a 4-tap equalization circuit as an example, the second adjusting circuit of the 1 st data path 100 receives the second signal pair OUT2 output by the 4 th data path 100, the second adjusting circuit of the 2 nd data path 100 receives the second signal pair OUT2 output by the 1 st data path 100, the second adjusting circuit of the 3 rd data path 100 receives the second signal pair OUT2 output by the 2 nd data path 100, and the second adjusting circuit of the 4 th data path 100 receives the second signal pair OUT2 output by the 3 rd data path 100.

Fig. 7 is a further functional block diagram of a data path in a data receiving circuit, and referring to fig. 7, the i-th data path 100 may further include: the third adjusting circuit 106 is configured to receive the second signal pair OUT2 output by the i-2 th data path 100, and adjust the first signal pair OUT1 in the i-2 th data path 100 in response to the received second signal pair OUT2, wherein the i-2 th data path 100 is the mth data path 100 if the i-2 nd data path 100 is the 2 nd data path 100, and the i-2 th data path 100 is the mth-1 data path 100 if the i-2 th data path 100 is the 1 st data path 100. For the currently transmitted input data, the influence of the intersymbol interference caused by the previously transmitted 2 nd bit data is also larger, so that an independent third adjusting circuit 106 may be set, so that the third adjusting circuit 106 responds to the second signal pair OUT2 output by the i-2 th data path 100 to adjust the first signal pair OUT1 of the i-2 th data path 100, thereby reducing the influence of the intersymbol interference caused by the previously transmitted 2 nd bit data on the currently transmitted input data, and further improving the accuracy of the transmission of the input data.

In a specific example, taking a 4-tap equalization circuit as an example, the third adjusting circuit of the 1 st data path 100 receives the second signal pair OUT2 output by the 3 rd data path 100, the third adjusting circuit of the 2 nd data path 100 receives the second signal pair OUT2 output by the 4 th data path 100, the third adjusting circuit of the 3 rd data path 100 receives the second signal pair OUT2 output by the 1 st data path 100, and the third adjusting circuit of the 4 th data path 100 receives the second signal pair OUT2 output by the 2 nd data path 100.

It will be appreciated that in one particular example, the ith data path 100 may include both the second conditioning circuitry described above and the third conditioning circuitry described above. In another specific example, the ith data path 100 may include one of the second and third conditioning circuits described above.

Fig. 8 is a further functional block diagram of a data path in a data receiving circuit. Referring to FIG. 8, in other embodiments M-N+.2; the i-th data path 100 may further include: a second encoding circuit 107 configured to receive the second signal pairs OUT2 output by the at least two data paths 100, encode all the received second signal pairs OUT2, and output a second control signal; wherein the second encoding circuit and the first encoding circuit 103 respectively receive the second signal pair OUT2 output by different data paths 100; the fourth adjusting circuit 108 is configured to receive the second control signal and adjust the first signal pair OUT1 in the ith data path 100 in response to the second control signal. Therefore, the circuit complexity is further reduced, the circuit size is reduced, and the load of the data receiving circuit is reduced, so that the input data transmission speed is further improved, and the input data transmission delay is further reduced.

The manner in which the second encoding circuit 107 performs the encoding process and the principle in which the fourth adjusting circuit adjusts the first signal pair OUT1 can refer to the foregoing specific description of the first encoding circuit 103 and the first adjusting circuit 104, which are not repeated herein. In a specific example, the second encoding circuit of the 1 st data path 100 may receive the second signal pair OUT2 output by the 4 th data path 100 and the 3 rd data path 100, the second encoding circuit of the 2 nd data path 100 may receive the second signal pair OUT2 output by the 1 st data path 100 and the 4 th data path 100, the second encoding circuit of the 3 rd data path 100 may receive the second signal pair OUT2 output by the 2 nd data path 100 and the 1 st data path 100, and the second encoding circuit of the 4 th data path 100 may receive the second signal pair OUT2 output by the 3 rd data path 100 and the 2 nd data path 100.

Fig. 9 to 12 are different functional block diagrams of the data receiving circuit, taking m=4 as an example, the sampling clocks CLK corresponding to the 1 st data path 100 to the 4 th data path 100 are respectively defined as dqs_0, dqs_90, dqs_180 and dqs_270, the second signal pair OUT2 output by the 1 st data path 100 to the 4 th data path 100 is respectively defined as out_0, out_90, out_180 and out_270, out_0[ n-1] is the second signal pair output by the 1 st data path in the previous clock cycle, out_90[ n-1] is the second signal pair output by the 2 nd data path in the previous clock cycle, out_180[ n-1] is the second signal pair output by the 3 rd data path in the previous clock cycle, and out_270 n-1] is the second signal pair output by the 4 th data path in the previous clock cycle; the amplifying circuit, the first encoding circuit and the first adjusting circuit are indicated together with 20, and T1, T2, T3 and T4 respectively represent control signals involved in the DFE, the control signals being the first control signal TapA for the first adjusting circuit 104 and the corresponding received second signal pair OUT2 for the second adjusting circuit and the third adjusting circuit. Several different implementations of the data receiving circuit will be described below with reference to the accompanying drawings, the following "+" referring to performing an or operation:

Referring to fig. 4, 5, 7 and 9 in combination, in one example, for the data path 100 with the sampling clock dqs_0, i.e. 1 st, out_270 is the control signal T1 of the second regulator circuit 105, out_180 is the control signal T2 of the third regulator circuit 106, out_90+out_0[ n-1] is the first control signal TapA of the first regulator circuit 104, i.e. t3+t4 is the first control signal TapA. For the data path 100 with the sampling clock DQS_90, i.e., 2 nd, OUT_0 is the control signal T1 of the second regulator circuit 105, OUT_270 is the control signal T2 of the third regulator circuit 106, OUT_180+OUT_90[ n-1] is the first control signal TapA of the first regulator circuit 104, i.e., T3+T4 is the first control signal TapA. For the 3rd data path 100, which is DQS_180, the sampling clock OUT_90 is the control signal T1 of the second regulator circuit 105, OUT_0 is the control signal T2 of the third regulator circuit 106, OUT_270+OUT_180[ n-1] is the first control signal TapA of the first regulator circuit 104, i.e., T3+T4 is the first control signal TapA. For the DQS_270, i.e., the 4 th data path 100, OUT_180 is the control signal T1 of the second regulator circuit 105, OUT_90 is the control signal T2 of the third regulator circuit 106, OUT_0+OUT_270[ n-1] is the first control signal TapA of the first regulator circuit 104, i.e., T3+T4 is the first control signal TapA.

Referring to fig. 4 to 6 and 10 in combination, in another example, for the 1 st data path 100, out_270 is the control signal T1 of the second adjusting circuit 105, out_90+out_180+out_0[ n-1] is the first control signal TapA of the first adjusting circuit 104, i.e., t2+t3+t4 is the first control signal TapA. For the 2 nd data path 100, OUT_0 is the control signal T1 of the second adjusting circuit 105, OUT_270+OUT_180+OUT_90[ n-1] is the first control signal TapA of the first adjusting circuit 104, i.e. T2+T3+T4 is the first control signal TapA. For the 3 rd data path 100, OUT_90 is the control signal T1 of the second adjusting circuit 105, OUT_0+OUT_270+OUT_180[ n-1] is the first control signal TapA of the first adjusting circuit 104, i.e. T2+T3+T4 is the first control signal TapA. For the 4 th data path 100, OUT_180 is the control signal T1 of the second adjusting circuit 105, OUT_90+OUT_0+OUT_270[ n-1] is the first control signal TapA of the first adjusting circuit 104, i.e. T2+T3+T4 is the first control signal TapA.

Referring to fig. 4,5 and 11 in combination, in yet another example, for the 1 st data path 100, out_270+out_180+out_90+out_0[ n-1] is used as the first control signal TapA of the first adjusting circuit 104, i.e., t1+t2+t3+t4 is used as the first control signal TapA. For the 2 nd data path 100, OUT_0+OUT_270+OUT_180+OUT_90[ n-1] is the first control signal TapA of the first adjusting circuit 104, i.e. T1+T2+T3+T4 is the first control signal TapA. For the 3 rd data path 100, OUT_90+OUT_0+OUT_270+OUT_180[ n-1] is the first control signal TapA of the first adjusting circuit 104, i.e. T1+T2+T3+T4 is the first control signal TapA. For the 4 th data path 100, OUT_180+OUT_90+OUT_0+OUT_270[ n-1] is the first control signal TapA of the first adjusting circuit 104, i.e. T1+T2+T3+T4 is the first control signal TapA.

Referring to fig. 4, 5 and 12 in combination, in still another example, for the 1 st data path 100, out_90+out_0[ n-1] is used as the first control signal TapA of the first adjusting circuit 104, i.e., t3+t4 is used as the first control signal TapA, out_270+out_180 is used as the second control signal of the fourth adjusting circuit, i.e., t1+t2 is used as the second control signal; for the 2 nd data path 100, OUT_180+OUT_90[ n-1] is the first control signal TapA of the first adjusting circuit 104, i.e. T3+T4 is the first control signal TapA, OUT_0+OUT_270 is the second control signal of the fourth adjusting circuit, i.e. T1+T2 is the second control signal; for the 3 rd data path 100, OUT_270+OUT_180[ n-1] is the first control signal TapA of the first adjusting circuit 104, namely T3+T4 is the first control signal TapA, OUT_90+OUT_0 is the second control signal of the fourth adjusting circuit, and T1+T2 is the second control signal; for the 4 th data path 100, OUT_0+OUT_270[ n-1] is used as the first control signal TapA of the first adjusting circuit 104, i.e. T3+T4 is used as the first control signal TapA, OUT_180+OUT_90 is used as the second control signal of the fourth adjusting circuit, i.e. T1+T2 is used as the second control signal.

Fig. 13 is a schematic circuit diagram of an amplifying circuit and a first adjusting circuit 104 in any one of the data paths 100, fig. 14 is a schematic circuit diagram of a first sub-compensating circuit or a second sub-compensating circuit in fig. 13, and fig. 15 is a schematic circuit diagram of another one of the amplifying circuit and the first adjusting circuit 104 in any one of the data paths 100.

Referring to fig. 13, the first signal pair OUT1 includes a first data signal out1_o and a first reference data signal out1_e, the amplifying circuit includes a first node net1 and a second node net2, the first node net1 outputs the first data signal out1_o, and the second node net2 outputs the first reference data signal out1_e; the first adjusting circuit 104 includes: the first control circuit 114 is connected between the first node net1 and the ground, and is turned on or off according to the second sub-control signal TapA; the second control circuit 124 is connected between the second node net2 and the ground, and is turned on or off according to the first sub-control signal TapA.

The first control circuit 114 is turned on when the second sub-control signal TapA is 1, such that the transmission path between the first node net1 and the ground is turned on, the first control circuit 114 is turned off when the second sub-control signal TapA is 0, such that the transmission path between the first node net1 and the ground is turned off, the second control circuit 124 is turned on when the first sub-control signal TapA is 1, such that the transmission path between the second node net2 and the ground is turned on, and the second control circuit 124 is turned off when the first sub-control signal TapA is 0, such that the transmission path between the second node net2 and the ground is turned off via the second control circuit 124.

Wherein the first control circuit 114 may include: the first NMOS transistor MN1, wherein a grid electrode of the first NMOS transistor MN1 receives a second sub-control signal TapA, and the first NMOS transistor MN1 is connected between a first node net1 and a ground terminal; the second control circuit 124 may include: the gate of the second NMOS transistor MN2 receives the first sub-control signal TapA1, and the second NMOS transistor MN2 is connected between the second node net2 and the ground. The drain electrode of the first NMOS tube MN1 is connected with a first node net1, and the source electrode is connected with the ground terminal; the drain of the second NMOS transistor MMN2 is connected to the second node net2, and the source is connected to the ground.

The second sub-control signal TapA is 1, and the first NMOS transistor MN1 is turned on; the second sub-control signal TapA is 0, and the first NMOS transistor MN1 is turned off. The first sub-control signal TapA is 1, and the second NMOS transistor MN2 is turned on; the first sub-control signal TapA is 0, and the second NMOS transistor MN2 is turned off.

Referring to fig. 13, the first adjusting circuit 104 may further include: the first compensation circuit 134 is connected between the first control circuit 114 and the ground terminal and between the second control circuit 124 and the ground terminal, and the first control circuit 114 and the second control circuit 124 are both connected between the first compensation circuit 134 and the first node net1, and the first compensation circuit 134 is configured to receive the first tap signal TapC and adjust the first signal pair OUT1 with a first adjustment value corresponding to the first tap signal TapC. Specifically, the equivalent resistance of the first compensation circuit 134 is adjustable, so that the equivalent resistance between the first node net1 and the ground is variable, and the equivalent resistance between the second node net2 and the ground is variable, which affects the ability to adjust the first signal to the OUT1, so that the DFE function of the i-th data path 100 has a plurality of different adjusting abilities.

The first compensation circuit 134 is connected between the source of the first NMOS MN1 and the ground, and is also connected between the source of the second NMOS MN2 and the ground.

Referring to fig. 13 to 15, the first compensation circuit 134 may include: the gates of the third NMOS transistors MN3 receive one bit of data in the first tap signal TapC, and each third NMOS transistor MN3 is connected between the first control circuit 114 and the ground terminal and between the second control circuit 124 and the ground terminal. The larger the number of the turned-on third NMOS transistors MN3 in the first compensation circuit 134, the smaller the equivalent resistance value of the first compensation circuit 134. It should be noted that, for convenience of illustration, the third NMOS transistors MN3 are not illustrated in fig. 13 in parallel, and in fact, the first compensation circuit 134 includes a plurality of third NMOS transistors MN3 connected in parallel, a drain electrode of each third NMOS transistor MN3 is connected to a source electrode of the first NMOS transistor MN1 and/or a source electrode of the second NMOS transistor MN2, and a source electrode of each third NMOS transistor MN3 is connected to a ground terminal.

In some examples, referring to fig. 13 and 14, the first compensation circuit 134 may include a first sub-compensation circuit and a second sub-compensation circuit, the first sub-compensation circuit is connected between the first control circuit 114 and the ground, the second sub-compensation circuit is connected between the second control circuit 124 and the ground, wherein the first sub-compensation circuit and the second sub-compensation circuit each include a plurality of third NMOS transistors MN3 connected in parallel, the third NMOS transistors MN3 of the first sub-compensation circuit and the third NMOS transistors MN3 of the second sub-compensation circuit are the same and correspond in number, and the gates of the third NMOS transistors MN3 of the first sub-compensation circuit and the corresponding third NMOS transistors MN3 of the second sub-compensation circuit each receive one bit of data in the first tap signal TapC. That is, the first control circuit 114 and the second control circuit 124 are respectively connected to different third NMOS tube groups, which include a plurality of third NMOS tubes MN3 connected in parallel. It should be noted that, for convenience of illustration, fig. 13 illustrates a plurality of third NMOS transistors MN3 connected in parallel by using a single third NMOS transistor MN3, and taking the bit number of the first tap signal TapC as a as an example, fig. 14 illustrates that the gate of each third NMOS transistor MN3 in the plurality of third NMOS transistors MN3 connected in parallel is controlled by TapC [ a-1] to TapC [0], where TapC [ a-1] to TapC [0] are respectively corresponding to the highest bit data to the lowest bit data of the first tap signal TapC, in other words, fig. 14 illustrates a schematic circuit structure of the first sub compensation circuit or the second sub compensation circuit. Referring to fig. 13 and 14, the drains of the third NMOS transistors MN3 of the first sub-compensation circuit are all connected to the source of the first NMOS transistor MN1, and the drains of the third NMOS transistors MN2 of the second sub-compensation circuit are all connected to the source of the second NMOS transistor MN 2.

In addition, the channel width to length ratio of the third NMOS transistor MN3 controlled by different bit data of the first tap signal TapC may be different. For the third NMOS MN3, the equivalent resistance is inversely related to the channel width-to-length ratio, that is, the larger the channel width-to-length ratio is, the smaller the equivalent resistance is, and by setting the channel width-to-length ratio of each third NMOS MN3, the equivalent resistance values of different third NMOS MN3 can be set, so as to adjust the amplitude of the first compensation circuit to adjust the level of the first signal pair. Generally, the smaller the equivalent resistance value of the third NMOS transistor MN3, the stronger the adjusting capability of the branch where the third NMOS transistor MN3 is located to adjust the level of the first signal to OUT 1. Therefore, the channel width to length ratio of different third NMOS transistors MN3 can be set reasonably according to the requirement. In some examples, the channel width to length ratio of the third NMOS transistor MN3 controlled by the high bit data in the first tap signal TapC is a first width to length ratio, the channel width to length ratio of the third NMOS transistor MN3 controlled by the low bit data is a second width to length ratio, and the first width to length ratio may be greater than the first width to length ratio.

In other examples, referring to fig. 15, each third NMOS transistor MN3 in the first compensation circuit 134 is connected between both the first control circuit 114 and ground and the second control circuit 124 and ground. That is, the first control circuit 114 is connected to the same set of third NMOS tube sets including a plurality of third NMOS tubes MN3 connected in parallel with the second control circuit 124. The first control circuit 114 and the second control circuit 1124 may be connected to the same third NMOS tube group that includes a plurality of third NMOS tubes MN3 in parallel.

The first tap signal TapC is multi-bit data, and it is understood that the number of the third NMOS transistors MN3 connected to the first control circuit 114 may be greater than or equal to the number of bits of the first tap signal TapC, and the number of the third NMOS transistors MN3 connected to the second control circuit 124 may be greater than or equal to the number of bits of the first tap signal TapC.

The first tap signal TapC may be obtained by adding a first tap sub signal and a second tap sub signal, where the first tap sub signal and the second tap sub signal are multi-bit data, and the first tap sub signal and the second tap sub signal are added in a binary addition manner to obtain a first tap signal TapC. Taking the first tap sub-signal as 5-bit data and the second tap sub-signal as 4-bit data as an example, the first tap sub-signal and the second tap sub-signal can be added to obtain 5-bit data. In one example, the first tap sub-signal and the second tap sub-signal may be stored in a mode Register 115 (MR 115, model Register 115) and a mode Register 116 (MR 116, model Register 116), respectively.

In another example, the first tap signal TapC may also be multi-bit data registered within a mode register.

Regarding the specific circuit implementation of the second adjusting circuit 105 and the third adjusting circuit 106, reference may be made to the specific circuit of the first adjusting circuit 104 described above. Specifically, referring to fig. 13 and 15, the second adjusting circuit 105 may include: in the second adjusting circuit 105 of the ith+1th data path, the eleventh NMOS transistor MN11, the gate of the eleventh NMOS transistor MN11 receives the second data signal out2_o in the second signal pair OUT2 output by the ith data path, and the eleventh NMOS transistor MN11 is connected between the second node net2 and the ground terminal; in the twelfth NMOS transistor MN12, in the second adjusting circuit 105 of the i+1th data path, the gate of the twelfth NMOS transistor MN12 receives the second complementary data signal out2_e in the second signal pair OUT2 output by the ith data path, and the twelfth NMOS transistor MN12 is connected between the first node net1 and the ground terminal.

Referring to fig. 13 and 15, the third adjusting circuit 106 may include: in the third adjusting circuit 106 of the ith+1th data path, the thirteenth NMOS transistor MN13, the gate of the thirteenth NMOS transistor MN13 receives the second data signal out2_o in the second signal pair OUT2 output by the ith-1 th data path, and the thirteenth NMOS transistor MN13 is connected between the second node net2 and the ground terminal; in the third adjusting circuit 106 of the ith+1th data path of the fourteenth NMOS transistor MN14, the gate of the fourteenth NMOS transistor MN14 receives the second complementary data signal out2_e in the second signal pair OUT2 output by the ith data path, and the fourteenth NMOS transistor MN14 is connected between the first node net1 and the ground terminal.

Correspondingly, referring to fig. 13 and 15, the second adjusting circuit 105 and the third adjusting circuit 106 may also be correspondingly provided with a second compensating circuit 115 and a third compensating circuit 116, respectively, where the second compensating circuit 115 is connected between the second adjusting circuit 105 and the ground, and the third compensating circuit 116 is connected between the third adjusting circuit 106 and the ground. The second compensation circuit 115 includes a plurality of parallel NMOS transistors, and each NMOS transistor receives one bit of data in the second Tap signal Tap1, which is turned on or off, so that an equivalent resistance value of the second compensation circuit 115 is adjustable; the third compensation circuit 116 includes a plurality of parallel NMOS transistors, and each NMOS transistor receives one bit of data in the third Tap signal Tap2, which is turned on or off, so that the equivalent resistance value of the third compensation circuit 116 is adjustable. For the description of the second compensation circuit 115 and the third compensation circuit 116, reference is made to the corresponding description of the first compensation circuit 134, which is not repeated here.

Referring to fig. 9 and 13 in combination, for the 1 st data path, OUT 2O and OUT 2E in the second adjusting circuit 105 are two differential signals in OUT 270, OUT 2O and OUT 2E in the third adjusting circuit 106 are two differential signals in OUT 180, respectively, and OUT 90+out 0 n-1 (i.e., the result of the or operation) are two differential signals in the first sub-control signal TapA1 and the second sub-control signal TapA 2; for the 2 nd data path, the OUT2_o and OUT2_e in the second adjusting circuit 105 are two differential signals in out_0, respectively, the OUT2_o and OUT2_e in the third adjusting circuit 106 are two differential signals in out_270, respectively, and the first sub-control signal TapA and the second sub-control signal TapA2 are two differential signals in out_180+out_90[ n-1] (i.e., the result of the OR operation); for the 3 rd data path, the OUT2_o and OUT2_e in the second adjusting circuit 105 are two differential signals in out_90, respectively, the OUT2_o and OUT2_e in the third adjusting circuit 106 are two differential signals in out_0, respectively, and the first sub-control signal TapA and the second sub-control signal TapA2 are two differential signals in out_270+out_180[ n-1] (i.e., the result of the OR operation); for the 4 th data path, the OUT2_o and OUT2_e in the second adjusting circuit 105 are two differential signals in out_180, respectively, the OUT2_o and OUT2_e in the third adjusting circuit 106 are two differential signals in out_90, respectively, and the first sub-control signal TapA and the second sub-control signal TapA2 are two differential signals in out_0+out_270[ n-1] (i.e., the result of the OR operation).

With continued reference to fig. 13, the amplifying circuit 101 may include: the grid electrode of the fourth NMOS tube MN4 receives input data IN, the drain electrode of the fourth NMOS tube MN4 is connected with a working power supply VDD through a first resistor R1, the drain electrode of the fourth NMOS tube MN4 is connected with a first node net1 and outputs a first data signal OUT 1O, and the source electrode is coupled with a grounding end; the fifth NMOS transistor MN5, the gate of the fifth NMOS transistor MN5 receives the reference voltage VREF, the drain is connected to the working power supply VDD through the second resistor R2, and the drain of the fifth NMOS transistor MN5 is connected to the second node net2 and outputs the first reference data signal out1_e, the source is coupled to the ground, and the first reference data signal out1_e and the first data signal out1_o form the first signal pair OUT1. Wherein, the resistance values of the first resistor R1 and the second resistor R2 are the same or close to the same.

With continued reference to fig. 13, the amplifying circuit 101 may further include: the sixth NMOS transistor MN6, the grid electrode of the sixth NMOS transistor MN6 receives the Bias signal Bias, the drain electrode is connected with the conductive source electrode of the fourth NMOS transistor MN4 and the source electrode of the fifth NMOS transistor MN5, and the source electrode of the sixth NMOS transistor MN6 is connected with the ground terminal. During the operation of the amplifying circuit 101, the Bias signal Bias is a high level signal, i.e. the sixth NMOS transistor MN6 is turned on.

Fig. 16 is a schematic diagram showing another configuration of the amplifying circuit, the first control circuit, the second control circuit, and the first compensation circuit in any one of the data paths. Referring to fig. 16, in other embodiments, the amplifying circuit 101 may include: one end of the current source I0 is connected with the working power supply VDD; the third PMOS tube MP3 is connected between the other end of the current source I0 and the first node net1, and the grid electrode of the third PMOS tube MP3 receives input data IN; the fourth PMOS MP4 is connected between the other end of the current source I0 and the second node net2, and the gate of the fourth PMOS MP4 receives the reference voltage VREF. That is, the drain electrode of the third PMOS transistor MP3 is connected to the first node net1, and the drain electrode of the fourth PMOS transistor MP4 is connected to the second node net2.

It should be noted that, the level values of the input data IN and the reference voltage VREF are different, so that the turn-on time of the third PMOS transistor MP3 receiving the input data IN is different from the turn-on time of the fourth PMOS transistor MP4 receiving the reference voltage VREF, and the turn-on degree of the third PMOS transistor MP3 is different from the turn-on degree of the fourth PMOS transistor MP4 at the same time. It can be understood that, based on the conduction degree of the third PMOS transistor MP3 being different from the conduction degree of the fourth PMOS transistor MP4, the current splitting capability of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 to the current source I0 is also different, so that the level at the first node net1 is different from the level at the second node net 2.

IN one example, when the level value of the input data IN is lower than the level value of the reference voltage VREF, the conduction degree of the third PMOS transistor MP3 is greater than the conduction degree of the fourth PMOS transistor MP4, so that the current provided by the current source I0 flows into the path where the third PMOS transistor MP3 is located, so that the current at the first node net1 is greater than the current at the second node net2, and further, the level of the first data signal output by the first node net1 is high, the level of the first reference data signal output by the second node net2 is low, IN other words, the level of the input data IN is less than the level of the reference voltage VREF, and the level of the first data signal is greater than the level of the first reference data signal. IN another example, the level of the input data IN is greater than the level of the reference voltage VREF, and the level of the first data signal is less than the level of the first reference data signal.

Correspondingly, the first control circuit 114, the second control circuit 124 and the first compensation circuit 134 may also be all configured by PMOS transistors, and the working principles of the first control circuit 114, the second control circuit 124 and the first compensation circuit 134 are substantially the same as those of the related circuits configured by NMOS transistors, and the main difference is that the gates of the PMOS transistors are turned on in response to the low-level signals and the gates of the NMOS transistors are turned on in response to the high-level signals.

It will be appreciated that an appropriate amplifying circuit may be selected according to the maximum level of the input data IN, for example, if the maximum level of the input data IN is relatively large, an amplifying circuit is used as shown IN fig. 13, i.e. the gate of the NMOS transistor receives the input data IN, and if the maximum level of the input data IN is relatively small, an amplifying circuit is used as shown IN fig. 16, i.e. the gate of the PMOS transistor receives the input data IN.

Fig. 17 is a schematic circuit diagram of a sampling circuit, and referring to fig. 17, the sampling circuit 102 may include: the seventh NMOS transistor MN7 has a gate connected to the first node net1 and a source connected to the ground; an eighth NMOS transistor MN8, wherein a grid electrode is connected with a second node net2, and a source electrode is connected with a ground terminal; the latch is composed of a first PMOS tube MP1, a second PMOS tube MP2, a ninth NMOS tube MN9 and a tenth NMOS tube MN10, wherein the drain electrode of the seventh NMOS tube MN7 is connected with the source electrode of the ninth NMOS tube MN9 and the drain electrode of the ninth NMOS tube MN9 outputs a second data signal OUT2_O, the drain electrode of the eighth NMOS tube MN8 is connected with the source electrode of the tenth NMOS tube MN10 and the drain electrode of the tenth NMOS tube MN10 outputs a second complementary data signal OUT2_E; the two reset PMOS tubes MP0, wherein the grid electrodes of the reset PMOS tubes MP0 receive the sampling clock CLK, the source electrodes are connected with the working power supply VDD, and the drain electrodes of the reset PMOS tubes MP0 are connected with the drain electrodes of the ninth NMOS tube MN9 and the tenth NMOS tube MN 10.

During the period when the sampling signal CLK is a high level signal, the sampling circuit 102 outputs the valid second data signal out2_o and the second complementary data signal out2_e; during the period when the sampling signal CLK is a low level signal, both the second data signal out2_o and the second complementary data signal out2_e are reset to high level signals.

The operation principle of the amplifying circuit and the sampling circuit will be described below with reference to fig. 13 and 17:

The input data IN of the 4 th data path 100 is 0, i.e. a low level signal, the voltage of the input data IN is smaller than the reference voltage VREF, and the conduction degree of the fourth NMOS transistor MN4 is smaller than the conduction degree of the fifth NMOS transistor MN 5; the first node net1 discharges via the fourth NMOS transistor MN4, that is, the voltage of the first node net1 is pulled down, the second node net2 discharges via the fifth NMOS transistor MN5, and the voltage of the second node net2 is also pulled down; since the conduction degree of the fourth NMOS transistor MN4 is smaller than that of the fifth NMOS transistor MN5, the discharging speed of the first node net1 is smaller than that of the second node net2, that is, the speed at which the first node net1 is pulled down is smaller than that at which the second node net2 is pulled down, and thus the voltage of the first data signal out1_o output by the first node net1 is greater than that of the first reference data signal out1_e output by the second node net 2. Correspondingly, the conduction degree of the seventh NMOS tube is larger than that of the eighth NMOS tube, so that the ninth NMOS tube is conducted before the tenth NMOS tube, the drain electrode of the ninth NMOS tube outputs a low-level signal, the drain electrode of the tenth NMOS tube outputs a high-level signal, finally, the drain electrode of the ninth NMOS tube outputs a second data signal OUT2_O, the drain electrode of the tenth NMOS tube outputs a second complementary data signal OUT2_E, the second data signal OUT2_O is 0, and the second complementary data signal OUT2_E is 1.

The input data IN of the 4 th data path 100 is 1, i.e. a high level signal, the voltage of the input data IN is greater than the reference voltage VREF, and the conduction degree of the fourth NMOS transistor MN4 is greater than the conduction degree of the fifth NMOS transistor MN 5; the first node net1 discharges via the fourth NMOS transistor MN4, that is, the voltage of the first node net1 is pulled down, the second node net2 discharges via the fifth NMOS transistor MN5, and the voltage of the second node net2 is also pulled down; since the conduction degree of the fourth NMOS transistor MN4 is greater than that of the fifth NMOS transistor MN5, the discharging speed of the first node net1 is greater than that of the second node net2, that is, the first node net1 is pulled down more than that of the second node net2, and thus the voltage of the first data signal out1_o output by the first node net1 is less than that of the first reference data signal out1_e output by the second node net 2. Correspondingly, the conduction degree of the seventh NMOS tube is smaller than that of the eighth NMOS tube, so that the ninth NMOS tube is conducted later than the tenth NMOS tube, the drain electrode of the tenth NMOS tube outputs a low-level signal, the drain electrode of the ninth NMOS tube outputs a high-level signal, finally, the drain electrode of the ninth NMOS tube outputs a second data signal OUT2_O, the drain electrode of the tenth NMOS tube outputs a second complementary data signal OUT2_E, the second data signal OUT2_O is 1, and the second complementary data signal OUT2_E is 0.

For the principle of decision feedback equalization by the first adjusting circuit 104, reference should be made to the foregoing corresponding description, and details are not repeated here.

The data receiving circuit provided in the above embodiment can compensate the currently transmitted input data based on the previously transmitted multiple input data, so as to realize decision feedback equalization and improve the problem of intersymbol interference. And to achieve this, the number of conditioning circuits required is less than the number of input data participating in the DFE, compared to a scheme in which the conditioning circuits are in one-to-one correspondence with each bit of data participating in the DFE, embodiments of the present disclosure may reduce the complexity of the conditioning circuits, thereby reducing the load of the data receiving circuit, increasing the speed of transmission of the input data, reducing the power consumption of the data receiving circuit, and reducing the DFE delay, for example, in some examples, may save more reaction time for 1-tap, so that the 1-tap compensates better for the currently transmitted input data, further improving the accuracy of transmission of the input data. Here, 1-tap refers to that input data of a previous bit of input data currently transmitted participates in the DFE process. It will be appreciated that in some embodiments the conditioning circuit may comprise only a first conditioning circuit, and in other embodiments the conditioning circuit may comprise any one or any combination of the aforementioned second, third and fourth conditioning circuits in addition to the first conditioning circuit.

Accordingly, the embodiment of the present disclosure further provides a semiconductor device including the data receiving circuit provided in the above embodiment.

The semiconductor device may be a wafer, a chip, a system, or the like. The semiconductor device may be a memory device, and the memory device may be a DRAM or an SRAM. The DRAM may be SDRAM, which may be DDR SDRAM, such as DDR4, DDR5, DDR6, LPDDR4, LPDDR5, or LPDDR6. In some embodiments, the semiconductor device may be a memory chip, which may be a DRAM chip or an SRAM chip. In addition, the input data may be DQ input data.

From the above analysis, the semiconductor device can reduce the complexity of the circuit, save the area required by the circuit, reduce the load caused by the circuit and improve the transmission speed of input data while improving the problem of intersymbol interference.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the disclosure, and the scope of the embodiments of the disclosure should be assessed accordingly to that of the appended claims.

Claims

1. A data receiving circuit, comprising:

A plurality of data paths each receiving input data and a sampling clock, and each of the data paths receiving a different phase of the sampling clock, the plurality of data paths comprising: the 1 st data path to the M data path are numbered according to the increment of the natural number, the i-th data path is any one data path in the plurality of data paths, i is more than or equal to 1 and less than or equal to M, M is more than or equal to 2, and the phase difference between sampling clocks received by any two data paths with continuous numbers is the same in the 1 st data path to the M data path; wherein the i-th data path includes:

An amplifying circuit configured to amplify a voltage difference between the voltage of the input data and a reference voltage and output a first signal pair;

a sampling circuit configured to receive the respective sampling clocks, sample the first signal pair, and output a second signal pair;

the first coding circuit is configured to receive the second signal pairs output by the N data paths, code all the received second signal pairs, and output a first control signal, wherein N is less than or equal to M;

A first adjustment circuit configured to receive the first control signal and adjust the first signal pair in the ith data path in response to the first control signal.

2. The data receiving circuit of claim 1, wherein the first encoding circuit of the ith data path receives the second signal pairs output by at least two of the data paths other than the ith-1 data path, and wherein the first encoding circuit of the 1 st data path receives the second signal pairs output by at least two of the data paths other than the mth data path; wherein i is more than 1 and less than or equal to M, and M is more than or equal to 3.

3. The data receiving circuit of claim 2, wherein the first encoding circuit of an i-1 data path receives the second signal pair output by the i-1 data path and the second signal pair output by the i-1 data path; the first encoding circuit of the mth data path receives the second signal pair output by the 1 st data path and the second signal pair output by the mth data path.

4. The data receiving circuit of claim 2, wherein the first encoding circuit of the mth data path receives the second signal pair output by the 1 st data path and the second signal pair output by the 2 nd data path; the first coding circuit of the ith data path receives the second signal pair output by the ith data path and the second signal pair output by the (i+1) th data path, i+1 < M; the first encoding circuit of an M-1 data path receives the second signal pair output by the 1 st data path and the second signal pair output by the M-1 st data path.

5. A data receiving circuit as claimed in claim 3 or 4, wherein M is 4 and the phase difference is 90 °.

6. The data receiving circuit of claim 1, wherein the first encoding circuit of the ith data path receives the second signal pair including the ith data path output, and the first encoding circuit of the 1 st data path receives the second signal pair including the 1 st data path output; wherein i is more than 1 and less than or equal to M, and M is more than or equal to 3.

7. The data receiving circuit of claim 1, wherein N = M.

8. The data receiving circuit of claim 1, wherein the second signal pair comprises a second data signal and a second complementary data signal, the second data signal and the second complementary data signal being mutually inverted signals; the control signal comprises a first sub-control signal and a second sub-control signal; the first encoding circuit includes:

the first sub-coding circuit is used for performing OR operation on the received second data signals to obtain the first sub-control signals;

And the second sub-coding circuit is used for carrying out OR operation on the received second complementary data signals to obtain the second sub-control signals.

9. The data receiving circuit of claim 8, wherein the first signal pair comprises a first data signal and a first reference data signal, the amplifying circuit comprising a first node that outputs the first data signal and a second node that outputs the first reference data signal; the first adjusting circuit includes:

The first control circuit is connected between the first node and the ground terminal and is turned on or turned off according to the second sub-control signal;

The second control circuit is connected between the second node and the ground terminal and is turned on or turned off according to the first sub-control signal.

10. The data receiving circuit of claim 9, wherein the first control circuit comprises:

The grid electrode of the first NMOS tube receives the second sub-control signal, and the first NMOS tube is connected between the first node and the ground terminal;

The second control circuit includes:

and the grid electrode of the second NMOS tube receives the first sub-control signal, and the second NMOS tube is connected between the second node and the ground terminal.

11. The data receiving circuit of claim 9, wherein the first adjusting circuit further comprises:

The first compensation circuit is connected between the first control circuit and the ground terminal and between the second control circuit and the ground terminal, and the first control circuit and the second control circuit are both connected between the first compensation circuit and the first node, and the first compensation circuit is configured to receive a first tap signal and adjust the first signal pair with a first adjustment value corresponding to the first tap signal.

12. The data receiving circuit of claim 11, wherein the first compensation circuit comprises:

And the gates of the third NMOS tubes are connected in parallel, each third NMOS tube receives one bit of data in the first tap signal, and each third NMOS tube is connected between the first control circuit and the ground terminal and between the second control circuit and the ground terminal.

13. The data receiving circuit of claim 11, wherein the first tap signal is based on an addition of a first tap sub-signal and a second tap sub-signal.

14. The data receiving circuit of claim 1, wherein the ith data path further comprises:

And a second adjusting circuit configured to receive the second signal pair output by the i-1 th data path and adjust the first signal pair in the i-th data path in response to the received second signal pair, wherein the i-1 th data path is the Mth data path if the i-th data path is the 1 st data path.

15. The data receiving circuit of claim 14, wherein the ith data path further comprises:

And a third adjusting circuit configured to receive the second signal pair output by the ith data path and adjust the first signal pair in the ith data path in response to the received second signal pair, wherein the ith data path is the Mth data path if the ith data path is the 2 nd data path, and the ith data path is the Mth data path if the ith data path is the 1 st data path.

16. The data receiving circuit of claim 1, wherein M-N is ≡2; the ith data path further includes:

A second encoding circuit configured to receive the second signal pairs output from at least two of the data paths, encode all the received second signal pairs, and output a second control signal; wherein the second encoding circuit and the first encoding circuit respectively receive the second signal pairs output by different data paths;

a fourth adjustment circuit configured to receive the second control signal and adjust the first signal pair in the ith data path in response to the second control signal.

17. The data receiving circuit of claim 1, wherein the amplifying circuit comprises:

The grid electrode of the fourth NMOS tube receives the input data, the drain electrode of the fourth NMOS tube is connected with a working power supply through a first resistor, the drain electrode of the fourth NMOS tube outputs a first data signal, and the source electrode of the fourth NMOS tube is coupled with the ground end;

and the grid electrode of the fifth NMOS tube receives the reference voltage, the drain electrode of the fifth NMOS tube is connected with the working power supply through a second resistor, the drain electrode of the fifth NMOS tube outputs a first reference data signal, the source electrode of the fifth NMOS tube is coupled with the ground terminal, and the first reference data signal and the first data signal form the first signal pair.

18. The data receiving circuit of claim 17, wherein the amplifying circuit further comprises:

and the grid electrode of the sixth NMOS tube receives the bias signal, the drain electrode of the sixth NMOS tube is connected with the conductive source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube, and the source electrode of the sixth NMOS tube is connected with the ground terminal.

19. A semiconductor device, comprising: a data receiving circuit as claimed in any one of claims 1 to 18.

20. The semiconductor device according to claim 19, wherein the semiconductor device comprises a memory chip.