JP4932305B2 - Method for producing group III nitride compound semiconductor device - Google Patents

Description

The present invention relates to a device comprising a group III nitride compound semiconductor represented by the general formula Al _x Ga _y In _1-xy N and a method for producing the same. The present invention is particularly effective for a field effect transistor made of a group III nitride compound semiconductor.

  FIG. 4 is a cross-sectional view showing the configuration of the heterobipolar transistor 900. The heterobipolar transistor 900 includes a collector layer 91p made of p-type GaN doped with magnesium and a base layer 92n made of n-type GaN doped with silicon on an arbitrary substrate 90 via a buffer layer (not shown) if necessary. A second emitter layer 93p made of p-type AlGaN doped with magnesium and a first emitter layer 94p made of p-type GaN doped with magnesium are sequentially formed. Further, a step is formed by dry etching, and the surfaces of the collector layer 91p made of p-type GaN and the base layer 92n made of n-type GaN are partially exposed. A collector electrode C, a base electrode B, and an emitter electrode E are formed on the collector layer 91p made of p-type GaN, the base layer 92n made of n-type GaN, and the first emitter layer 94p made of p-type GaN, respectively. A pnp type heterobipolar transistor 900 having such a configuration is described in Non-Patent Document 1 and the like.

Incidentally, as described in Non-Patent Document 2, the group III nitride compound semiconductor is difficult to perform so-called wet etching, and dry etching is commonly used. However, as described in Non-Patent Document 3, the p-type layer doped with an acceptor mainly using a valence element has a remarkable surface roughness due to dry etching as compared with an undoped layer or an n-type layer. It is difficult to form an electrode with good ohmic properties.
AP Zhang et al., Appl. Phys. Lett., Vol. 76, p. 2943 (2000) SJ Peraton et al., J. Appl. Phys., Vol. 86, p. 1 (1999) SH Su et al., J. Vac. Sci. Technol., B22 (3), p. 971 (2004)

  Based on the above, it can be understood that the potential of the channel formation layer 96 is not stable even when the field effect transistor (FET) or the high electron mobility transistor (HEMT) having the configuration shown in the cross-sectional view of FIG. That is, the FET 950 in FIG. 5 includes an arbitrary substrate 90, a p body layer 95p made of p-type GaN doped with magnesium, a channel forming layer 96i made of undoped GaN, via a buffer layer (not shown) if necessary. It has a strained layer 97i made of undoped AlGaN. Further, the body electrode Bd is formed by partially exposing the p body layer 95p by etching. A source electrode S and a drain electrode D are formed on the strained layer 97i, and a gate electrode G is formed between them via an insulating film 98 (gate insulating film). Here, for example, a ground potential is connected to the body electrode Bd, and the channel forming layer 96i is kept at the ground potential via the p body layer 95p. Thus, the current between the source electrode S and the drain electrode D is controlled by the potential change of the gate electrode G using the two-dimensional electron gas (2DEG) formed at the interface between the channel forming layer 96i and the strained layer 97i. It is. In this regard, if the body electrode Bd is formed on the p body layer 95p made of p-type GaN exposed by etching, an electrode having good ohmic properties cannot be formed, and therefore the channel forming layer 96i cannot be stably maintained at the ground potential. Then, the device characteristics of the FET 950 are not stable and are difficult to use.

  Accordingly, an object of the present invention is to connect to a field effect transistor (FET) or a high electron mobility transistor (HEMT) made of a group III nitride compound semiconductor so that the potential of the i-type channel forming layer can be stabilized. The p-type region is formed in a state where an ohmic electrode can be easily formed.

  According to a first aspect of the present invention, there is provided a method for manufacturing a group III nitride compound semiconductor device, wherein the composition is different on a part of the surface of the first group III nitride compound semiconductor layer doped with the acceptor, A step of forming a mask made of a second group III nitride compound semiconductor layer which is difficult to diffuse, an exposed surface of the first group III nitride compound semiconductor layer, and a second group III nitride compound semiconductor layer And a step of epitaxially growing a third group III nitride compound semiconductor layer without supplying a dopant to the surface of the mask comprising: a step of epitaxially growing the third group III nitride compound semiconductor layer. Diffusing acceptors in the first group III nitride compound semiconductor layer into the third group III nitride compound semiconductor layer on the exposed surface of the first group III nitride compound semiconductor layer, Second Group III Nitrogen A group III nitride characterized in that the acceptor in the first group III nitride compound semiconductor layer is not diffused into the third group III nitride compound semiconductor layer on the mask made of the compound compound semiconductor layer. This is a method for manufacturing a semiconductor compound semiconductor device.

  The invention according to claim 2 is characterized in that an electrode is formed on the uppermost layer where the acceptor is diffused, above the exposed surface of the first group III nitride compound semiconductor layer. According to a third aspect of the present invention, a total of at least two electrodes are formed on any group III nitride compound semiconductor layer formed above the mask composed of the second group III nitride compound semiconductor layer. It is characterized by.

The invention according to claim 4 is characterized in that the second group III nitride compound semiconductor layer has a composition of aluminum in the group III element of 50% or more. In addition, the composition of aluminum in the group III element being 50% or more means that the aluminum composition x is 0.5 or more in the general formula Al _x Ga _y In _1-xy N.

  In the invention according to claim 5, the step of forming the mask made of the second group III nitride compound semiconductor layer forms the second group III nitride compound semiconductor layer by epitaxial growth at a temperature of 700 ° C. or lower. A step of forming an etching mask, a step of removing the second group III nitride compound semiconductor layer not covered with the etching mask by wet etching, and the second group III nitride compound semiconductor by heating. The method includes a step of crystallizing a mask made of layers and a step of removing the etching mask. The invention according to claim 6 is characterized in that the acceptor is magnesium.

  When a group III nitride compound semiconductor is epitaxially grown on the first group III nitride compound semiconductor layer containing an acceptor without supplying a dopant, the group III nitride compound semiconductor layer exists in the first group III nitride compound semiconductor layer. It is known that acceptors diffuse into the upper “undoped” layer. Even if the contamination inside the MOCVD apparatus, which is due to the so-called acceptor memory effect, is completely removed, or after the surface of the first group III nitride compound semiconductor layer is acid-treated, the acceptor-free MOCVD apparatus is used. Even if an upper “undoped layer” is to be formed, the acceptor present in the first group III nitride compound semiconductor layer diffuses into the upper “undoped” layer (H. Xing et al., Jpn. J. Appl. Phys., Vol. 42 (2003) Pt. 1, No. 1, pp. 50-53).

  On the other hand, the present inventors have found out that the diffusion of the acceptor upward can be prevented through the aluminum nitride layer (Japanese Patent Application No. 2005-280485).

  Therefore, according to the present invention, by forming a mask that can prevent diffusion to the upper layer of the acceptor, an i-type region is formed on the upper part of the mask, and a p-type region is formed on a portion where the mask is not formed. Is used to form a semiconductor device having a desired configuration. That is, a mask made of the second group III nitride compound semiconductor in which the acceptor is difficult to diffuse from an adjacent layer is formed on a part of the surface of the first group III nitride compound semiconductor layer containing the acceptor. Thereafter, when the third group III nitride compound semiconductor is epitaxially grown without supplying the acceptor raw material, the acceptor is not diffused from the first group III nitride compound semiconductor layer above the mask, so that the undoped third group III Since the acceptor diffuses from the first group III nitride compound semiconductor layer to the portion where the group nitride compound semiconductor is not formed with the mask, the third group III nitride compound semiconductor containing the acceptor is formed. Is done. By this new method, a configuration in which the p-type region and the i-type region are arranged side by side can be easily achieved without using etching. As a result, the degree of freedom of the configuration of the semiconductor device is dramatically increased, and a semiconductor device having a configuration that has been difficult in the past can be easily manufactured.

  In order to form a mask made of a group III nitride compound semiconductor that prevents acceptor diffusion, an amorphous or polycrystalline semiconductor layer is first formed by low-temperature growth, patterned by etching, and then heated and crystallized. Good to take. In this case, simple wet etching can be used for etching for patterning. After crystallization, the etching mask can be easily removed because it is resistant to acid treatment and the like.

  It has been found that a group III nitride compound semiconductor for forming a mask has a high aluminum composition, it is difficult for an acceptor to diffuse. Practical is that aluminum is 50% or more.

  When forming a layer made of the second group III nitride compound semiconductor serving as a mask to prevent acceptor diffusion, the layer is preferably grown at 400 ° C. or higher and lower than 800 ° C. in order to form an amorphous or polycrystalline semiconductor layer. If it is grown below 400 ° C., crystallization cannot be expected even when it is heated later, and the acceptor diffuses during growth of the layer above 800 ° C. This growth temperature is more preferably 500 ° C. or higher and 700 ° C. or lower.

  The heating after forming the mask made of the second group III nitride compound semiconductor for preventing the diffusion of the acceptor by patterning is 800 ° C. or higher and lower than 1300 ° C. If it is less than 800 ° C., the layer grown at a low temperature does not crystallize, and the crystallinity of the third group III nitride compound semiconductor formed on the mask is not improved. Further, when the temperature is 1300 ° C. or higher, thermal decomposition or the like of the first group III nitride compound semiconductor containing the acceptor or the second group III nitride compound semiconductor that prevents the diffusion of the acceptor occurs. A good semiconductor element cannot be formed. The heating temperature is more preferably 900 ° C. or higher and 1200 ° C. or lower, and further preferably 1000 ° C. or higher and 1150 ° C. or lower. As described above, since the second group III nitride compound semiconductor is not sufficiently crystallized before patterning, simple wet etching can be used for etching for patterning.

  The first group III nitride compound semiconductor containing an acceptor may be, for example, an independent substrate or a layer epitaxially grown on another substrate or the like. The acceptor may be a method of introducing a raw material during the epitaxial growth, or a method of introducing the acceptor into the layer or the substrate later by ion implantation or other methods. It goes without saying that other configurations of the present application can be arbitrarily selected from known techniques.

  For example, in the invention according to claim 3, “a total of at least two electrodes are formed on any of the group III nitride compound semiconductor layers formed above the mask formed of the second group III nitride compound semiconductor layer” For example, in the case of a field effect transistor, a source electrode and a drain electrode are formed on the same layer. At this time, the gate electrode may be formed directly on the layer provided with the source electrode and the drain electrode, or may be formed via an insulating layer or other layers.

  Hereinafter, embodiments of the present invention will be described with reference to cross-sectional views. In addition, this invention is not limited to a following example.

  FIG. A to FIG. F is a cross-sectional view showing a manufacturing process of the HEMT 100 according to the first specific example of the present invention. FIG. As shown in F, the HEMT 100 as the final product is configured as follows. A p-type layer 1p (first group III nitride compound semiconductor layer) made of p-type GaN doped with magnesium as an acceptor, if necessary, via a buffer layer (not shown) if necessary, A mask layer 2m (second group III nitride compound semiconductor layer) made of undoped AlN having a thickness of 20 nm or less is formed at the center. On the part of the p-type layer 1p where the mask layer 2m is not formed, a p body layer 4p (p-type region of the third group III nitride compound semiconductor layer) in which magnesium is diffused from the p-type layer 1p, An undoped channel formation layer 4i (i-type region of the third group III nitride compound semiconductor layer) is formed on the mask layer 2m. The uppermost surfaces of the p body layer 4p and the undoped channel forming layer 4i are the same height (third group III nitride compound semiconductor layer). A p-AlGaN layer 5p in which magnesium is further diffused from the p body layer 4p is formed on the p body layer 4p, and an undoped AlGaN layer 5i is formed on the undoped channel forming layer 4i. The aluminum compositions of the p-AlGaN layer 5p and the undoped AlGaN layer 5i are equal and 30% or less.

  Thus, the source electrode S and the drain electrode D are formed on the undoped AlGaN layer 5i, and the gate is interposed between them via the insulating film 6 made of silicon dioxide on the undoped AlGaN layer 5i. An electrode G is formed. A body electrode Bd is formed on the p-AlGaN layer 5p. Thus, by making the source electrode S and the body electrode Bd ground potential, applying a positive potential to the drain electrode, and changing the gate electrode G, the HEMT 100 can act as a switching element or an amplifying element. The two-dimensional electron gas (2DEG) is formed at the interface between the undoped channel forming layer 4i and the undoped AlGaN layer 5i and below the gate electrode G. The body electrode Bd has a function of maintaining the potential of the undoped channel formation layer 4i at the ground potential via the p-AlGaN layer 5p and the p body layer 4p. Thus, the potential of the undoped channel formation layer 4i becomes a stable ground potential, and the element characteristics of the HEMT 100 are stabilized.

  FIG. The F HEMT 100 is formed as follows. In addition, the layer containing magnesium by doping or diffusion is “high resistance and cannot be said to be p-type” before thermal annealing for reducing resistance, but for convenience of explanation, the layer containing magnesium is also That is, even if the resistance is not low, it is expressed as p-type.

  A p-type layer 1p composed of p-type GaN doped with magnesium and a layer 2 composed of undoped AlN having a thickness of 20 nm or less are epitaxially grown in order on an arbitrary substrate 10 through a buffer layer (not shown) if necessary. At this time, the p-type layer 1p is epitaxially grown at, for example, about 1000 to 1150 ° C., and the layer 2 made of undoped AlN is formed at 700 ° C. or less, for example, 600 ° C. (FIG. 1.A).

  Next, an etching mask 3 is formed with silicon dioxide (FIG. 1.B), and a portion of the silicon dioxide not covered with the etching mask 3 is wet-etched with a KOH solution. At this time, since the layer 2 made of undoped AlN is grown at a low temperature and is amorphous or polycrystalline, the layer 2 made of undoped AlN not covered with the silicon dioxide etching mask 3 is completely etched by wet etching. Can be removed. Further, the p-type layer 1p made of p-type GaN doped with magnesium can be controlled so as to be hardly etched.

  Next, the mask layer 2m formed by patterning the layer 2 made of undoped AlN by etching is heated for crystallization. The heating temperature is 800 ° C. or higher. Before this heating, the mask layer 2m can be eroded when the silicon dioxide etching mask 3 is removed by the acid treatment, but it has corrosion resistance against the acid treatment by the heating. Thus, the silicon dioxide etching mask 3 on the mask layer 2m, which has become corrosion resistant by heating, is removed by acid treatment (FIG. 1.C).

  Next, the GaN layer and the AlGaN layer are epitaxially grown in order without introducing a magnesium raw material into a magnesium-free clean MOCVD apparatus. These may have a total thickness of 100 nm or less. When epitaxial growth is performed to form a GaN layer without introducing a magnesium raw material, magnesium diffuses from the p-type layer 1p and forms a p body layer 4p at a portion in contact with the lower p-type layer 1p. The On the other hand, the upper portion of the mask layer 2m made of undoped AlN is not in contact with the p-type layer 1p, and the mask layer 2m made of undoped AlN is a layer that hardly diffuses acceptor (magnesium). Layer 4i is formed. The p body layer 4p and the channel forming layer 4i are finally formed so that their uppermost surfaces are at the same height. That is, the p body layer 4p and the channel forming layer 4i are formed in a state where the p-type region and the i-type region are in contact with each other in the lateral direction. Next, for example, trimethylaluminum is added to the introduced raw material, so that the AlGaN layer is epitaxially grown without introducing the magnesium raw material. The Al composition is preferably 5% or more and 30% or less. On the upper portion of the p body layer 4p, magnesium is diffused from the p body layer 4p to form a p-AlGaN layer 5p. On the other hand, an undoped AlGaN layer 5i is formed on the channel forming layer 4i. The p-AlGaN layer 5p and the undoped AlGaN layer 5i are finally formed so that the uppermost surfaces thereof are at the same height. The p-AlGaN layer 5p and the undoped AlGaN layer 5i have a p-type region and an i-type region. It is formed as a state in contact with the horizontal direction. After the epitaxial growth is completed, heat annealing is performed to remove hydrogen that hinders activation of the acceptor-containing layer (FIG. 1.D).

  Thereafter, an insulating film 6 made of silicon dioxide is formed (FIG. 1.E). The insulating film 6 is patterned to insulate the body electrode Bd on the exposed p-AlGaN layer 5p surface, the source electrode S and the drain electrode D on the exposed undoped AlGaN layer 5i surface, and the insulation between the source electrode S and the drain electrode D. The gate electrode G is formed on the film 6 to obtain the HEMT 100 (FIG. 1.F). FIG. The HEMT 100 of F has a good ohmic property because the surface of the p-AlGaN layer 5p on which the body electrode Bd is formed is not etched, and the body electrode Bd passes through the p-AlGaN layer 5p and the p body layer 4p. For example, the channel forming layer 4i can be stably maintained at the ground potential. As a result, FIG. The HEMT 100 of F is a field effect transistor having stable element characteristics.

  FIG. 2 is a cross-sectional view showing the configuration of the HEMT 200 according to the second embodiment of the present invention. Whereas the gate electrode G of the HEMT 100 in FIG. 1 is formed through an insulating film 6 (gate insulating film) between the HEMT 100 and the undoped AlGaN layer 5i, the HEMT 200 in FIG. 5i is formed directly. Other configurations and manufacturing methods are the same as those of the HEMT 100 in FIG. Like the HEMT 100 of FIG. 1, the HEMT 200 of FIG. 2 also has the body electrode Bd formed on the p-AlGaN layer 5p with good ohmic properties, and can stably maintain the potential of the channel formation layer 4i, and the device characteristics can be improved. It becomes a stable field effect transistor.

  FIG. 3 is a cross-sectional view showing the configuration of a power FET 300 according to the third embodiment of the present invention. 1 is formed close to both ends of a two-dimensional electron gas (2DEG) in which the source electrode S and the drain electrode D are formed by the gate electrode G, the power FET 300 in FIG. The n-type GaN substrate 20 is used and the drain electrode D is provided on the back surface of the n-type GaN substrate 20. Further, in order to provide a current path from the two-dimensional electron gas (2DEG) through the n-type GaN substrate 20 to the drain electrode D, the p-type layer 1p and the mask layer 2m made of undoped AlN are formed at the center of the gate electrode G. It has a hole, and the hole is filled with the channel forming layer 4i. Further, before the p-type layer 1p is formed, an n-type GaN layer 21n doped with silicon is formed on the surface of the n-type GaN substrate 20 by epitaxial growth via a buffer layer (not shown) if necessary.

  In the power FET 300 of FIG. 3, after the n-type GaN substrate 20 is doped with silicon to form an n-type GaN layer 21n by epitaxial growth, FIG. A to FIG. Similarly to C, a p-type layer 1p and a mask layer 2m made of undoped AlN are formed, then a hole is formed in the center of the p-type layer 1p and the mask layer 2m by dry etching, and an n-type is formed at the bottom thereof The GaN layer 21n is exposed. After this, FIG. D to FIG. Similarly to F, without introducing a magnesium raw material, the GaN layer and the AlGaN layer can be epitaxially grown, and the resistance of the acceptor-containing layer can be reduced by heating annealing to form the insulating film and each electrode. Similar to the HEMT 100 of FIG. 1 and the HEMT 200 of FIG. 2, the power FET 300 of FIG. 3 also has the body electrode Bd formed on the p-AlGaN layer 5p with good ohmic properties, and stably maintains the potential of the channel formation layer 4i. Thus, a field effect transistor with stable element characteristics can be obtained.

Sectional drawing which shows the manufacturing process of HEMT100 which concerns on the specific 1st Example of this invention. Sectional drawing which shows the manufacturing process of HEMT100 which concerns on the specific 1st Example of this invention. Sectional drawing which shows the manufacturing process of HEMT100 which concerns on the specific 1st Example of this invention. Sectional drawing which shows the manufacturing process of HEMT100 which concerns on the specific 1st Example of this invention. Sectional drawing which shows the manufacturing process of HEMT100 which concerns on the specific 1st Example of this invention. Sectional drawing which shows the manufacturing process of HEMT100 which concerns on the specific 1st Example of this invention. Sectional drawing which shows the structure of HEMT200 which concerns on the specific 2nd Example of this invention. Sectional drawing which shows the structure of power FET300 which concerns on the specific 3rd Example of this invention. Sectional drawing which shows the structure of pnp type HBPT900. Sectional drawing which shows the structure of the conventional HEMT950.

Explanation of symbols

100, 200: HEMT
300: Power FET
10: Substrate (arbitrary material)
20: n-type GaN substrate 1: p-type GaN layer 2: undoped AlN layer 2m: mask layer made of undoped AlN 3: etching mask made of silicon dioxide 4p: p body layer made of p-type GaN in which magnesium is diffused from the lower layer 4i : Channel forming layer made of undoped GaN 5p: p-type AlGaN layer in which magnesium is diffused from the lower layer 5i: undoped AlGaN layer 6: insulating layer 21: n-type GaN layer doped with silicon

Claims (6)

In the method for producing a group III nitride compound semiconductor device,
A step of forming a mask made of a second group III nitride compound semiconductor layer having a different composition and difficult to diffuse an acceptor on part of the surface of the first group III nitride compound semiconductor layer doped with an acceptor When,
The third group III nitride without supplying dopant to the exposed surface of the first group III nitride compound semiconductor layer and the surface of the mask made of the second group III nitride compound semiconductor layer. And a step of epitaxially growing a system compound semiconductor layer,
In the step of epitaxially growing the third group III nitride compound semiconductor layer,
The acceptor in the first group III nitride compound semiconductor layer is diffused in the third group III nitride compound semiconductor layer on the exposed surface of the first group III nitride compound semiconductor layer. Let
The acceptor in the first group III nitride compound semiconductor layer is diffused in the third group III nitride compound semiconductor layer on the mask made of the second group III nitride compound semiconductor layer. A method for producing a group III nitride compound semiconductor device, characterized in that the method is not performed. 2. The group III nitride compound semiconductor device according to claim 1, wherein an electrode is formed on the uppermost layer where the acceptor is diffused, above the exposed surface of the first group III nitride compound semiconductor layer. 3. Production method. 2. A total of at least two electrodes are formed on any of the group III nitride compound semiconductor layers formed above the mask composed of the second group III nitride compound semiconductor layer. Or the manufacturing method of the group III nitride compound semiconductor element of Claim 2. 4. The group III according to claim 1, wherein the second group III nitride compound semiconductor layer has a composition of aluminum in the group III element of 50% or more. 5. A method for manufacturing a nitride compound semiconductor device. Forming a mask comprising the second group III nitride compound semiconductor layer,
Forming the second group III nitride compound semiconductor layer by epitaxial growth at a temperature of 700 ° C. or lower;
Forming an etching mask;
Removing the second group III nitride compound semiconductor layer not covered by the etching mask by wet etching;
Crystallization of the mask made of the second group III nitride compound semiconductor layer by heating; and
The method for producing a group III nitride compound semiconductor device according to any one of claims 1 to 4, further comprising a step of removing the etching mask. The method of manufacturing a group III nitride compound semiconductor device according to any one of claims 1 to 5, wherein the acceptor is magnesium.

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