JP2007281086A - Insulated gate bipolar transistor, and fabrication method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an insulated gate bipolar transistor using a p-type nitride gallium semiconductor. <P>SOLUTION: A nanocolumn region 13 has a plurality of nanocolumns 31 each made of a first p-type nitride gallium semiconductor. A collector layer 15 is so formed as to connect together each one end 31a of the nanocolumns 31 in the nanocolumn region 13, and is made of a second p-type nitride gallium semiconductor. A drift layer 17 is formed on a collector layer 15, and is made of a first n-type nitride gallium semiconductor. An emitter region 19 is made of a second n-type nitride gallium semiconductor. A well region 21 is made of a third p-type nitride gallium semiconductor. A gate electrode 25 is formed on a gate insulating film 23. A collector electrode 29 is formed on a second face 27b of a board 27, and the nanocolumn region 13 is formed on a first face 27a of the board 27. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to insulated gate bipolar transistors and methods for making insulated gate bipolar transistors.

  Non-Patent Document 1 describes growing a free-standing gallium nitride film on a (0001) sapphire substrate. This gallium nitride is grown on nanocolumns grown by RF molecular beam epitaxy. The residual stress is estimated by evaluating the lattice constant in the c-axis direction, and it is clarified that the stress is low.

Non-Patent Document 2 describes an insulated gate bipolar transistor. Insulated gate bipolar transistors are used as power devices. The insulated gate bipolar transistor has a structure in which the drain of a metal-oxide-semiconductor structure n-type transistor is replaced with a p-type semiconductor.
Jap. J. Appl. Phys. Vol. 40, (2001), pp.L192-L194 Power Electronics Handbook, issued February 20, 2992, R & D Planning, pp.94-99

  According to Non-Patent Document 1, a gallium nitride film is grown so as to cover a nanocolumn region on a (0001) sapphire substrate. On the other hand, gallium nitride based semiconductor electronic devices require a conductive substrate. Gallium nitride substrates have begun to be used for gallium nitride based semiconductor electronic devices. The size of the gallium nitride substrate is smaller than the size of the Si substrate or GaAs substrate. There is a demand to produce a gallium nitride based semiconductor electronic device using a substrate having a larger size. Further, although the crystal quality of the gallium nitride substrate is improved, it is required to be further improved as compared with the crystal quality of the Si substrate or the GaAs substrate.

  Among the gallium nitride semiconductor electronic devices, the insulated gate bipolar transistor requires a collector made of a p-type gallium nitride semiconductor as described in Non-Patent Document 2, but as far as the inventors know, it is still p. A type gallium nitride substrate has not been developed.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide an insulated gate bipolar transistor using a p-type gallium nitride semiconductor, and to produce an insulated gate bipolar transistor using a gallium nitride semiconductor. It aims to provide a way to do.

  According to one aspect of the present invention, an insulated gate bipolar transistor includes: (a) a nanocolumn region having a plurality of nanocolumns made of a first p-type gallium nitride semiconductor; and (b) a plurality of nanocolumns in the nanocolumn region. A collector layer made of a second p-type gallium nitride semiconductor and provided with one end coupled to each other; and (c) a drift made of the first n-type gallium nitride semiconductor provided on the collector layer. A layer, (d) an emitter region provided on the drift layer and made of a second n-type gallium nitride semiconductor, and (e) a third region provided between the drift layer and the emitter region. A well region made of a p-type gallium nitride based semiconductor, (f) a gate insulating film provided on the well region, and (g) provided on the gate insulating film. Including a gate electrode for controlling conduction between the drift layer and the emitter region, and (h) a support base made of a p-type semiconductor different from the gallium nitride based semiconductor. And (i) a collector electrode provided on the second surface of the substrate, and the nanocolumn region is provided on the first surface of the substrate.

  According to the insulated gate bipolar transistor, a vertical semiconductor electronic device using a p-type gallium nitride semiconductor is provided. Since the nanocolumn region is made of a p-type gallium nitride semiconductor and the collector layer is made of a p-type gallium nitride semiconductor, a junction between the p-type semiconductor and the n-type gallium nitride semiconductor different from the gallium nitride semiconductor is not formed. In addition, since a low-dislocation nanocolumn region is used, the insulated gate bipolar transistor is formed using a gallium nitride-based semiconductor having good crystal quality. Furthermore, since the drift layer of the insulated gate bipolar transistor is made of a gallium nitride based semiconductor formed on the nanocolumn region, the leakage current is reduced and the withstand voltage is improved. In addition, since the conductive support is used, the heat dissipation characteristics of the insulated gate bipolar transistor are good.

  According to another aspect of the present invention, an insulated gate bipolar transistor includes: (a) a nanocolumn region having a plurality of nanocolumns made of a first p-type gallium nitride based semiconductor; and (b) the plurality of nanocolumns in the nanocolumn region. And a collector layer made of a second p-type gallium nitride semiconductor and (c) a collector layer made on the collector layer and made of a first n-type gallium nitride semiconductor. A drift layer; (d) an emitter region provided on the drift layer and made of a second n-type gallium nitride semiconductor; and (e) a first layer provided between the drift layer and the emitter region. 3 a well region made of a p-type gallium nitride semiconductor, (f) a gate insulating film provided on the well region, and (g) provided on the gate insulating film. A gate electrode for controlling conduction between the drift layer and the emitter region, and (h) a collector electrode connected to the nanocolumn region, wherein the nanocolumn region includes the collector electrode and the collector layer. Between.

  According to the insulated gate bipolar transistor, a vertical semiconductor electronic device using a p-type gallium nitride semiconductor is provided. Since the low dislocation nanocolumn region is made of a p-type gallium nitride semiconductor and the collector layer is made of a second p-type gallium nitride semiconductor, a p-type semiconductor different from the gallium nitride semiconductor and an n-type gallium nitride semiconductor can be used. Bonding is not formed. In addition, since the nanocolumn region is used, the insulated gate bipolar transistor is configured using a gallium nitride based semiconductor having good crystal quality. Furthermore, since the drift layer of the insulated gate bipolar transistor is made of a gallium nitride based semiconductor formed on the nanocolumn region, the leakage current is reduced and the withstand voltage is improved. In addition, since the insulated gate bipolar transistor does not include a substrate, the insulated gate bipolar transistor exhibits excellent heat dissipation characteristics.

  In the insulated gate bipolar transistor according to the present invention, the support base is preferably made of p-type Si or p-type GaAs. According to this insulated gate bipolar transistor, a p-type semiconductor region capable of forming a nanocolumn region is provided.

In the insulated gate bipolar transistor according to the present invention, the first p-type gallium nitride based semiconductor is made of Al _X1 Ga _Y1 In _1-X1-Y1 N, and the second p-type gallium nitride based semiconductor is Al _X2 The first n-type gallium nitride based semiconductor is made of Al _X3 Ga _Y3 In _1-X3-Y3 N, and the second n-type gallium nitride based semiconductor is made of Ga _Y2 In _1-X2-Y2 N It is preferable that the third p-type gallium nitride semiconductor is made of Al _X4 Ga _Y4 In _1-X4-Y4 N, and the third p-type gallium nitride based semiconductor is preferably made of Al _X5 Ga _Y5 In _1-X5-Y5 N.

  This insulated gate bipolar transistor can use various gallium nitride based semiconductors grown on a nanocolumn region made of a gallium nitride based semiconductor.

  In the insulated gate bipolar transistor according to the present invention, the first p-type gallium nitride semiconductor is gallium nitride, the second p-type gallium nitride semiconductor is gallium nitride, and the first n-type gallium nitride is used. The system semiconductor is preferably gallium nitride. According to this insulated gate bipolar transistor, gallium nitride has excellent crystal quality.

  Yet another aspect of the invention is a method of making an insulated gate bipolar transistor. This method includes: (a) a nanocolumn region having a plurality of nanocolumns made of a first p-type gallium nitride semiconductor on a first surface of a substrate including a conductive support made of a material different from a gallium nitride semiconductor. (B) growing a gallium nitride based semiconductor film so that one ends of the plurality of nanocolumns in the nanocolumn region are coupled to each other; and (c) after growing the gallium nitride based semiconductor film, A step of growing a semiconductor film for the collector layer made of a second p-type gallium nitride semiconductor; and (d) a first n-type gallium nitride system provided on the semiconductor film for the collector layer. And a step of growing a semiconductor film made of a semiconductor for the drift layer.

  According to this method, a vertical semiconductor electronic device using a p-type gallium nitride semiconductor can be manufactured. Since the nanocolumn region is used, a low-dislocation p-type gallium nitride semiconductor can be formed. In addition, since a high-quality crystalline p-type gallium nitride semiconductor film is provided on the nanocolumn region, a junction between the p-type semiconductor and the n-type gallium nitride semiconductor different from the gallium nitride semiconductor is not formed. Furthermore, since the collector layer and the drift layer are made of a low-dislocation gallium nitride semiconductor formed on the nanocolumn region, the leakage current of the insulated gate bipolar transistor is reduced and the dielectric breakdown voltage is improved. In addition, since the substrate includes a support made of a semiconductor material different from that of the gallium nitride semiconductor, an insulated gate bipolar transistor using the gallium nitride semiconductor can be manufactured without using the gallium nitride substrate.

  The method according to the present invention includes: (e) forming a well region and an emitter region for the insulated gate bipolar transistor after growing a semiconductor film for the drift layer; and (f) the well region and the emitter. Forming a gate insulating film, a gate electrode and an emitter electrode for the insulated gate bipolar transistor after forming the region; and (g) after forming the well region and the emitter region, the first region of the substrate. Forming a collector electrode on the second surface opposite to the surface, and the band gap of the semiconductor material of the conductive support is preferably smaller than the band gap of gallium nitride.

  According to this method, an insulated gate bipolar transistor using a gallium nitride based semiconductor can be manufactured without using a gallium nitride based substrate.

  The method according to the present invention includes (h) forming a well region and an emitter region for the insulated gate bipolar transistor after growing a semiconductor film for the drift layer, and (i) forming the well region and the emitter. Forming a gate insulating film, a gate electrode and an emitter electrode for the insulated gate bipolar transistor after forming the region; and (j) forming the gate insulating film, the gate electrode and the emitter electrode, A step of removing the support can be further provided. According to this method, since the support is removed, resistance due to the support disappears, and a junction between the p-type semiconductor and the p-type gallium nitride semiconductor different from the gallium nitride semiconductor is not formed.

  According to this method, since a conductive support is not used, there is no resistance due to the support.

  In the method according to the present invention, the conductive support is preferably made of p-type silicon or p-type GaAs. According to this method, an insulated gate using a gallium nitride based semiconductor on a support base that is easier to obtain than a gallium nitride substrate, larger in diameter than a gallium nitride substrate, and lower in cost than a gallium nitride substrate. Bipolar transistors can be created. Silicon or GaAs is easier to remove by etching than gallium nitride.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, an insulated gate bipolar transistor using a p-type gallium nitride semiconductor is provided. In addition, according to the present invention, a method for manufacturing an insulated gate bipolar transistor using a gallium nitride based semiconductor is provided.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the insulated gate bipolar transistor and the method of manufacturing the insulated gate bipolar transistor of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

(First embodiment)
FIG. 1A is a perspective view schematically showing an insulated gate bipolar transistor according to the present embodiment. FIG. 1B is a schematic diagram showing an insulated gate bipolar transistor according to this embodiment. The insulated gate bipolar transistor 11a includes a nanocolumn region 13, a collector layer 15, a drift layer 17, an emitter region 19, a well region 21, a gate insulating film 23, a gate electrode 25, a substrate 27, and a collector electrode 29. With. As shown in FIG. 1B, the nanocolumn region 13 has a plurality of nanocolumns 31 made of a first p-type gallium nitride semiconductor. The collector layer 15 is provided so that the ends 31a of the plurality of nanocolumns 31 in the nanocolumn region 13 are coupled to each other, and is made of a second p-type gallium nitride semiconductor. The drift layer 17 is provided on the collector layer 15 and is made of a first n-type gallium nitride semiconductor. The emitter region 19 is provided on the drift layer 17 and is made of a second n-type gallium nitride semiconductor. The well region 21 is provided between the drift layer 17 and the emitter region 19 and is made of a third p-type gallium nitride based semiconductor. The gate insulating film 23 is provided on the well region 21. The gate electrode 25 is provided on the gate insulating film 23, and is provided so as to control conduction between the drift layer 17 and the emitter region 19. The substrate 27 has a first surface 27a and a second surface 27b, and can include a support base 27a made of a p-type semiconductor different from a gallium nitride based semiconductor. The collector electrode 29 is provided on the second surface 27 b of the substrate 27. The nanocolumn region 13 is provided on the first surface 27 a of the substrate 27.

In this insulated gate bipolar transistor 11a, a vertical semiconductor electronic device using a p-type gallium nitride semiconductor is provided. Since the nanocolumn region 13 is made of a p-type gallium nitride semiconductor and the collector layer 15 is made of a second p-type gallium nitride semiconductor, a junction between a p-type semiconductor and an n-type gallium nitride semiconductor that is different from the gallium nitride semiconductor. Is not formed. Further, since the nanocolumn region 13 is used, the insulated gate bipolar transistor 11a is configured using a gallium nitride based semiconductor having a good crystal quality. Furthermore, since the drift layer 17 of the insulated gate bipolar transistor 11a is made of a gallium nitride based semiconductor formed on the low-dislocation nanocolumn region 13, the leakage current is reduced and the withstand voltage is improved. In addition, since the conductive substrate 27 made of a p-type semiconductor is used, the heat dissipation characteristics of the insulated gate bipolar transistor 11a are good. As a material of the gate insulating film 23 may be, for example, _{SiO 2, SiNx, SiON, Ga} 2 O 3, Sc 2 O 3, Gd 2 O 3, Al 2 O 3, AlN, AlGaN, and MgO and the like. As the material of the gate electrode 25, for example, Ni, Pt, polysilicon, Al, Ti, W, Ir, or transition metal silicide can be used.

  The collector layer 15 and the drift layer 17 form a pn junction 33a. The emitter region 19 and the well region 21 form a pn junction 33b. The well region 21 and the drift region 17 form a pn junction 33c. The gate insulating film 23 is provided on the surface layer of the well region 21, and the conductivity of the surface layer of the well region 21 is modulated according to the electric field from the gate electrode 25. When the electric field at the interface between the gate insulating film 23 and the well region 21 is increased, an inversion layer is formed on the surface layer of the well region 21, and channels CH1 and CH2 connecting the emitter region 19 and the drift region 17 are formed. Channels CH <b> 1 and CH <b> 2 flow electrons E from the emitter electrode 35 that form an ohmic junction with the emitter region 19 to the drift layer 17. The emitter electrode 35 is also connected to the well region 21.

  In the insulated gate bipolar transistor 11a, the substrate 27 can include a support base 27a and a buffer layer 27b provided on the support base 27a. The support base 27a is preferably made of p-type Si or p-type GaAs. According to this, a p-type semiconductor substrate capable of forming the nanocolumn region 13 is provided. The silicon substrate has a main surface made of, for example, a (111) plane. The buffer film 27b includes, for example, an AlN film. The AlN film has a wurtzite crystal structure.

In the insulated gate bipolar transistor 11a, the first p-type gallium nitride semiconductor in the nanocolumn region 13 is made of Al _X1 Ga _Y1 In _1-X1-Y1 N, and the second p-type gallium nitride semiconductor in the collector layer 15 is used. The semiconductor is made of Al _X2 Ga _Y2 In _1-X2-Y2 N, the first n-type gallium nitride semiconductor of the drift layer 17 is made of Al _X3 Ga _Y3 In _1-X3-Y3 N, and the emitter region 19 The second n-type gallium nitride based semiconductor is made of Al _X4 Ga _Y4 In _1-X4-Y4 N, and the third p-type gallium nitride based semiconductor in the well region 21 is Al _X5 Ga _Y5 In _1-X5-Y5. Preferably it consists of N. Specifically, these gallium nitride based semiconductors are GaN, InGaN, AlGaN, and InAlGaN. The insulated gate bipolar transistor 11a can use various gallium nitride based semiconductors grown on a nanocolumn region made of a gallium nitride based semiconductor.

  In the preferred embodiment, the first p-type gallium nitride based semiconductor in the nanocolumn region 13 is p-type GaN, the second p-type gallium nitride based semiconductor in the collector layer 15 is p-type GaN, and the drift layer 17 first The n-type gallium nitride based semiconductor is preferably n-type GaN. The second n-type gallium nitride semiconductor in the emitter region 19 can be made of n-type GaN, and the third p-type gallium nitride semiconductor in the well region 21 can be made of p-type GaN. Gallium nitride provided on the nanocolumn region 13 has excellent crystal quality.

  When the thickness L1 of the nanocolumn region 13 is, for example, 0.05 micrometers or more, a high-quality crystal without an initial growth defect layer can be obtained. If the thickness L1 of the nanocolumn region 13 is, for example, 2 micrometers or less, the on-resistance becomes low. If the thickness L2 of the collector layer 15 is 0.2 micrometers or more, for example, the collector layer surface becomes a flat continuous film. If the thickness L2 of the collector layer 15 is, for example, 3 micrometers or less, the on-resistance becomes low.

When the dopant concentration N13 of the nanocolumn region 13 is, for example, 10 ¹⁷ cm ⁻³ or more, the on-resistance is lowered. If the dopant concentration N13 in the nanocolumn region 13 is, for example, 10 ²¹ cm ⁻³ or less, the crystallinity is good, and the crystallinity of the collector layer grown thereon is also good. When the dopant concentration N15 of the collector layer 15 is, for example, 10 ¹⁷ cm ⁻³ or more, the on-resistance becomes low. If the dopant concentration N15 of the collector layer 15 is, for example, 10 ²¹ cm ⁻³ or less, there is an advantage that the crystallinity is good.

There are almost no threading dislocations in the nanocolumn region 13. When the threading dislocation density D2 of the collector layer 15 is, for example, 10 ⁷ cm ⁻² or less, the reverse breakdown voltage is improved.

  As described above, according to the present embodiment, an insulated gate bipolar transistor using a p-type gallium nitride semiconductor is provided.

(Second Embodiment)
FIG. 2A is a perspective view schematically showing an insulated gate bipolar transistor according to the present embodiment. FIG. 2B is a schematic diagram showing an insulated gate bipolar transistor according to this embodiment. The insulated gate bipolar transistor 11b includes a collector layer 15, a drift layer 17, an emitter region 19, a well region 21, a gate insulating film 23, and a gate electrode 25. The insulated gate bipolar transistor 11b includes a nanocolumn. A nanocolumn region 43 is included instead of the region 13, and a collector electrode 39 is included instead of the collector electrode 29. The nanocolumn region 43 includes a plurality of nanocolumns 41 made of the first p-type gallium nitride semiconductor. The collector layer 15 is provided so as to couple the ends 41a of the plurality of nanocolumns 41 in the nanocolumn region 43 to each other, and is made of a second p-type gallium nitride based semiconductor. The collector electrode 39 is electrically connected to the other ends of the plurality of nanocolumns 41. The nanocolumn region 43 is provided on the collector electrode 29. The nanocolumn region 43 is provided between the collector electrode 39 and the collector layer 15.

  In this insulated gate bipolar transistor 11b, a vertical semiconductor electronic device using a p-type gallium nitride semiconductor is provided. Since the nanocolumn region 43 is made of a p-type gallium nitride semiconductor and the collector layer 15 is made of a second p-type gallium nitride semiconductor, a junction between a p-type semiconductor and an n-type gallium nitride semiconductor that is different from the gallium nitride semiconductor. Is not formed. Further, since the nanocolumn region 43 is used, the insulated gate bipolar transistor 11b is configured using a gallium nitride based semiconductor having good crystal quality. Furthermore, since the drift layer 17 of the insulated gate bipolar transistor 11b is made of a gallium nitride based semiconductor formed on the low-dislocation nanocolumn region 43, the leakage current is reduced and the dielectric breakdown voltage is improved. In addition, since the insulated gate bipolar transistor 11b does not include a substrate, the insulated gate bipolar transistor 11b exhibits excellent heat dissipation characteristics. Since there is no substrate, there is no stress from the substrate.

If the thickness L3 of the nanocolumn region 43 is, for example, 0.05 micrometers or more, a high-quality crystal without an initial growth defect layer can be obtained. When the thickness L3 of the nanocolumn region 43 is, for example, 2 micrometers or less, the on-resistance becomes low. On the other hand, when the dopant concentration N43 in the nanocolumn region 43 is, for example, 10 ¹⁷ cm ⁻³ or more, the on-resistance is lowered. If the dopant concentration N43 in the nanocolumn region 43 is, for example, 10 ²¹ cm ⁻³ or less, the crystallinity is good, and the crystallinity of the collector layer grown thereon is also good.

  In the first and second embodiments, the individual nanocolumns 13 and 43 extend along an axis orthogonal to the major surface 15a of the collector layer 15 made of a gallium nitride semiconductor. 41 are connected to the gallium nitride semiconductor layer 15, and the other ends 29b of the nanocolumns 13 and 43 are open. Each of the nanocolumns 31 and 41 is made of a gallium nitride single crystal, and its growth axis is defined by the plane orientation of the underlying growth substrate. In addition, the gallium nitride semiconductor film 15 has a region that transitions from the individual nanocolumns 31 and 41 to an integral gallium nitride single crystal.

  As described above, according to the present embodiment, an insulated gate bipolar transistor using a p-type gallium nitride semiconductor is provided.

(Third embodiment)
A method for manufacturing an insulated gate bipolar transistor will be described with reference to FIGS. 3A, 3B, 3C, 4A, 4B, and 4C. To do.

  As shown in FIG. 3A, a substrate 51 for growing a gallium nitride based semiconductor is prepared. The substrate 51 can include a support 47 made of a material different from that of the gallium nitride semiconductor and a buffer film 49 formed on the support 47. The substrate 51 is prepared as follows, for example. The support 47 is disposed in the crystal growth apparatus. In this embodiment, for example, an RF-MBE apparatus is used as the crystal growth apparatus, but the present invention is not limited to this, and OMVPE, HVPE, or the like can also be used. As the support 47, for example, a (111) plane p-type silicon wafer or p-type GaAs can be used. A buffer film 49 is deposited on the support 47. When the (111) plane silicon substrate is used, the buffer film 49 can include, for example, a GaN film or an AlN film. In this case, the thickness of the buffer film 35 is preferably several nm or more, for example. The buffer layer forms initial growth nuclei that become the nuclei of nanocolumn growth. If necessary, the surface of the support 47 can be thermally cleaned prior to the growth of the buffer film. The band gap of the semiconductor material of the conductive support 47 is smaller than that of gallium nitride.

As shown in FIG. 3B, a p-type nanocolumn region 53 is formed on the substrate 51. The nanocolumn region 53 has a plurality of nanocolumns made of a gallium nitride based semiconductor, as shown in FIGS. 1B and 2B. The shape of the nanocolumn changes depending on the ratio (hereinafter referred to as “V / III”) of the number of moles of supply of the group V raw material and the number of moles of supply of the group III raw material. Nanocolumns are grown under nitrogen-rich conditions. The nanocolumn is formed on the wurtzite structure buffer film and extends in the direction of the (0001) axis of gallium nitride. The nanocolumn density in the nanocolumn region 53 varies depending on, for example, the type of the buffer layer material, its film thickness, and its growth conditions. The nanocolumn density can be changed, for example, in the range of about 1 × 10 ⁹ cm ^{−2 to} 5 × 10 ¹⁰ cm ⁻² . Under nitrogen-rich conditions, gallium nucleation and gallium migration are limited, so that columnar crystals grow rather than crystal film formation.

  Next, a p-type gallium nitride based semiconductor film 55 for the collector layer is grown. As shown in FIG. 3B, a p-type gallium nitride based semiconductor film 55 is grown so that a plurality of nanocolumns in the nanocolumn region 53 are coupled to each other. First, a gallium nitride based semiconductor region is grown so that a plurality of nanocolumns in the nanocolumn region 53 are coupled to each other. For this purpose, a gallium material larger than the gallium supply amount under the growth conditions of the nanocolumn region 53 is supplied. Increased gallium source promotes gallium nucleation and gallium migration. As a result, the plurality of nanocolumns 57 are coupled to each other, and a transition region 59 is formed. Next, a gallium nitride single crystal region 61 is deposited on the transition region 59 of the gallium nitride semiconductor. Thereby, the gallium nitride based semiconductor film 55 is obtained. The conductivity type of the gallium nitride semiconductor in the nanocolumn region 53 is the same as the conductivity type of the gallium nitride semiconductor film 55.

  According to this method, since the nanocolumn region 53 is made of a crystal having a very low dislocation density, the gallium nitride based semiconductor film 55 grown on the nanocolumn region 53 is also made of a crystal having a very low dislocation density. Since the substrate 51 includes the support 47 made of a material different from that of the gallium nitride semiconductor, the p-type gallium nitride semiconductor film 55 can be obtained without using the p-type gallium nitride semiconductor substrate. Further, the size of the gallium nitride based semiconductor film 55 can be made substantially the same as the size of the substrate 51. Thereby, the epitaxial substrate E1 was obtained. The epitaxial substrate E1 includes a substrate 51, a nanocolumn region 53, and a gallium nitride semiconductor-based film 55.

(Example)
An example of GaN nanocolumn growth uses an MBE growth apparatus. A K cell is used to provide a 7N gallium source and a 7N aluminum source, and an RF radical gun is used to provide a 6N N ₂ gas and a nitrogen source. The growth temperature of the buffer layer (initial nucleation) is in the range of 500 to 550 degrees Celsius, and the growth temperature of the nanocolumn formation is in the range of 850 to 900 degrees Celsius. Supply gallium source and active nitrogen.
Example V / III ratio: nanocolumn growth (nitrogen rich condition rather than GaN film growth)
It is. The distortion of the nanocolumn is relaxed, and the nanocolumn region is a very high quality crystal. The growth surface includes a facet plane, and the dislocations are bent with the growth. As a result, the nanocolumn region is almost dislocation free. The diameter of the nanocolumn varies depending on the growth temperature, growth rate, and V / III ratio, and is controlled, for example, in the range of about 30 nm to 200 nm. In particular, the diameter of the nanocolumn is highly dependent on the gallium supply. This is due to the fact that nanocolumn growth regulates gallium migration under nitrogen-rich conditions. The nanocolumn region is grown in the C-axis direction of the gallium nitride based semiconductor. A p-type gallium nitride based semiconductor film for the collector layer is continuously grown from the nanocolumn region. The carrier concentration of the nanocolumn is preferably 1 × 10 ¹⁷ cm ⁻³ or more. In this example, the carrier concentration p is about 3 × 10 ¹⁷ cm ⁻³ . The carrier concentration of the p-type gallium nitride based semiconductor film is preferably 1 × 10 ¹⁷ cm ⁻³ or more.

Subsequently, as shown in FIG. 3C, an n-type gallium nitride semiconductor film 63 for the drift layer is grown. The thickness of the gallium nitride based semiconductor film 63 is preferably, for example, 3 micrometers or more. The dopant concentration of the gallium nitride based semiconductor film 63 is smaller than the dopant concentration of the gallium nitride based semiconductor film 55, for example, preferably 10 ¹⁵ cm ⁻³ or more, and preferably 10 ¹⁷ cm ⁻³ or less. Thereby, an epitaxial substrate E2 was obtained. Epitaxial substrate E <b> 2 includes substrate 51, nanocolumn region 53, p-type gallium nitride semiconductor film 55, and n-type gallium nitride semiconductor film 63.

  As shown in FIG. 4A, after the n-type gallium nitride based semiconductor film 63 is grown, the n-type gallium nitride based semiconductor film 63 is processed using an etching method, a photolithography method, and an epitaxial growth method to obtain an insulated gate. A well region 65 and an emitter region 67 for the bipolar transistor are formed. For example, the n-type gallium nitride based semiconductor film 63 can be etched using a mask, and a gallium nitride based semiconductor for the well region can be selectively grown using this mask. In addition, the gallium nitride semiconductor for the well region can be etched using the mask, and the gallium nitride semiconductor for the emitter region can be selectively grown using the mask.

  As shown in FIG. 4B, a gate insulating film 69, a gate electrode 71, and an emitter electrode 73 for an insulated gate bipolar transistor are formed. Thereby, the substrate product E3 is obtained.

  As shown in FIG. 4C, a collector electrode 75 for an insulated gate bipolar transistor is formed. The collector electrode 75 is formed on the second surface 51 b opposite to the first surface 51 a of the substrate 51.

  These are the main steps of the method of making an insulated gate bipolar transistor. Through these steps, the substrate product E4 is produced.

  When the support 47 of the substrate 51 is made of silicon, the size of the substrate product is the size of a silicon wafer distributed in the market, for example, about 2 inches to 12 inches.

  As described above, according to this embodiment, a method for manufacturing an insulated gate bipolar transistor using a gallium nitride based semiconductor is provided.

(Fourth embodiment)
A method for manufacturing an insulated gate bipolar transistor will be described with reference to FIGS. 5 (A), 5 (B), and 5 (C).

  According to the steps shown in FIGS. 3A to 4B, the substrate product E3 is manufactured by performing the steps of the method of manufacturing the insulated gate bipolar transistor. Subsequently, the support 47 is removed. In the method of this embodiment, the substrate 51 can include a semi-insulating or insulating support as well as a conductive support.

  As shown in FIG. 5A, a mask 76 is formed on the surface of the substrate product E3 without forming a collector electrode on the second surface 51b of the substrate 51, and a gate electrode 71 and an emitter electrode 73 are formed. Etc. The mask 76 is a resist mask, for example.

  As shown in FIG. 5B, the substrate 51 is etched to remove the substrate from the substrate product E3, thereby producing the substrate product E5. When the substrate 51 includes a silicon support, the nanocolumn region 53a can be formed by wet-etching silicon selectively using a mixed solution of hydrofluoric acid and nitric acid. Further, when the substrate 51 includes a GaAs support, for example, GaAs can be selectively wet-etched using a mixed solution of sulfuric acid and hydrogen peroxide solution. Removal of the substrate 51 eliminates stress from the substrate.

  Thereafter, when the mask 76 is removed and the collector electrode 77 connected to the nanocolumn region 53 is produced, a substrate product E6 is obtained.

  According to this method, since the support is removed, resistance due to the support disappears and a junction between the p-type semiconductor and the n-type gallium nitride semiconductor different from the gallium nitride semiconductor is not formed.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. In this embodiment, an insulated gate bipolar transistor using a nanocolumn made of a p-type gallium nitride semiconductor has been described as an example, but a nanocolumn made of an n-type gallium nitride semiconductor can also be used. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

FIG. 1A is a cross-sectional view schematically showing an insulated gate bipolar transistor according to the first embodiment. FIG. 1B is a schematic diagram showing an insulated gate bipolar transistor according to the first embodiment. FIG. 2A is a cross-sectional view schematically showing an insulated gate bipolar transistor according to the second embodiment. FIG. 2B is a schematic diagram showing an insulated gate bipolar transistor according to the second embodiment. 3A, 3B, and 3C are drawings showing main steps of a method for manufacturing an insulated gate bipolar transistor. 4A, 4B, and 4C are drawings showing main steps of a method for manufacturing an insulated gate bipolar transistor. 5A, 5B, and 5C are drawings showing main steps of a method for manufacturing an insulated gate bipolar transistor.

Explanation of symbols

11a, 11b ... insulated gate bipolar transistor, 13 ... nanocolumn region, 15 ... collector layer, 17 ... drift layer, 19 ... emitter region, 21 ... well region, 23 ... gate insulating film, 25 ... gate electrode, 27 ... substrate, 27a DESCRIPTION OF SYMBOLS ... Supporting base, 27b ... Buffer layer, 29 ... Collector electrode, 31 ... Nanocolumn, 31a ... One end of nanocolumn, CH1, CH2 ... Channel, 33a, 33b, 33c ... Pn junction, 35 ... Emitter electrode, 39 ... Collector electrode, 41 ... nanocolumn, 41a ... one end of nanocolumn, 43 ... nanocolumn region, L1, L3 ... thickness of nanocolumn region, L2 ... thickness of collector layer, 47 ... support, 49 ... buffer film, 51 ... substrate, 53 ... nanocolumn region , 55... Gallium nitride based semiconductor film, 59... Gallium nitride based semiconductor transition region, 61. Single crystal region, E1, E2 ... epitaxial substrate, 63 ... gallium nitride based semiconductor film, 65 ... well region, 67 ... emitter region, 69 ... gate insulating film, 71 ... gate electrode, 73 ... emitter electrode, E3, E4, E5, E6 ... substrate product, 75 ... collector electrode, 76 ... mask, 77 ... collector electrode

Claims (9)

A nanocolumn region having a plurality of nanocolumns made of a first p-type gallium nitride based semiconductor;
A collector layer made of a second p-type gallium nitride based semiconductor, provided so as to couple one end of the plurality of nanocolumns of the nanocolumn region to each other;
A drift layer provided on the collector layer and made of a first n-type gallium nitride semiconductor;
An emitter region provided on the drift layer and made of a second n-type gallium nitride semiconductor;
A well region made of a third p-type gallium nitride based semiconductor and provided between the drift layer and the emitter region;
A gate insulating film provided on the well region;
A gate electrode provided on the gate insulating film for controlling conduction between the drift layer and the emitter region;
A substrate including a support base made of a p-type semiconductor different from a gallium nitride based semiconductor and having a first surface and a second surface;
A collector electrode provided on the second surface of the substrate,
The insulated gate bipolar transistor, wherein the nanocolumn region is provided on the first surface of the substrate. A nanocolumn region having a plurality of nanocolumns made of a first p-type gallium nitride based semiconductor;
A collector layer made of a second p-type gallium nitride based semiconductor, provided so as to couple one end of the plurality of nanocolumns of the nanocolumn region to each other;
A drift layer provided on the collector layer and made of a first n-type gallium nitride semiconductor;
An emitter region provided on the drift layer and made of a second n-type gallium nitride semiconductor;
A well region made of a third p-type gallium nitride based semiconductor and provided between the drift layer and the emitter region;
A gate insulating film provided on the well region;
A gate electrode provided on the gate insulating film for controlling conduction between the drift layer and the emitter region;
A collector electrode electrically connected to the nanocolumn region,
The insulated gate bipolar transistor, wherein the nanocolumn region is provided between the collector electrode and the collector layer.   2. The insulated gate bipolar transistor according to claim 1, wherein the support base is made of p-type Si or p-type GaAs. The first p-type gallium nitride based semiconductor is made of Al _X1 Ga _Y1 In _1-X1-Y1 N,
The second p-type gallium nitride based semiconductor is made of Al _X2 Ga _Y2 In _1-X2-Y2 N,
The first n-type gallium nitride based semiconductor is made of Al _X3 Ga _Y3 In _1-X3-Y3 N,
The second n-type gallium nitride based semiconductor is made of Al _X4 Ga _Y4 In _1-X4-Y4 N,
4. The insulated gate bipolar device according to claim 1, wherein the third p-type gallium nitride based semiconductor is made of Al _X5 Ga _Y5 In _1-X5-Y5 N. _5. Transistor. The first p-type gallium nitride based semiconductor is gallium nitride;
The second p-type gallium nitride based semiconductor is gallium nitride,
The insulated gate bipolar transistor according to any one of claims 1 to 4, wherein the first n-type gallium nitride based semiconductor is gallium nitride. A method for fabricating an insulated gate bipolar transistor comprising:
Forming a nanocolumn region having a plurality of nanocolumns made of a first p-type gallium nitride semiconductor on a first surface of a substrate including a conductive support made of a material different from a gallium nitride semiconductor;
Growing a gallium nitride based semiconductor film so as to bond one ends of the plurality of nanocolumns of the nanocolumn region to each other;
Growing a semiconductor film for the collector layer made of a second p-type gallium nitride based semiconductor after growing the gallium nitride based semiconductor film;
A step of growing a semiconductor film for the drift layer, which is provided on the semiconductor film for the collector layer and is made of a first n-type gallium nitride semiconductor;
A method characterized by comprising: Forming a well region and an emitter region for the insulated gate bipolar transistor after growing a semiconductor film for the drift layer;
Forming a gate insulating film and a gate electrode and an emitter electrode for the insulated gate bipolar transistor after forming the well region and the emitter region;
Forming a collector electrode on a second surface opposite to the first surface of the substrate after forming the well region and the emitter region;
The method of claim 6, wherein the band gap of the semiconductor material of the conductive support is smaller than the band gap of gallium nitride. Forming a well region and an emitter region for the insulated gate bipolar transistor after growing a semiconductor film for the drift layer;
Forming a gate insulating film and a gate electrode and an emitter electrode for the insulated gate bipolar transistor after forming the well region and the emitter region;
The method according to claim 7, further comprising removing the conductive support after forming the gate insulating film, the gate electrode, and the emitter electrode.   9. The method according to claim 6, wherein the conductive support is made of p-type silicon or p-type GaAs.

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