JP4922877B2 - Signal serial transmission system - Google Patents

Description

  The present invention relates to a signal serial transmission system in which a plurality of stages of signal transmission units are connected in a stackable manner, and signals are serially transmitted through the signal transmission units through a serial bus.

  For example, a PLC (programmable controller) is available as a system capable of serially transmitting the signal. In addition, in the building block type in the PLC, in addition to the CPU unit, various expansion units such as an I / O unit are provided according to a user's request or the like (see Patent Document 1). This building block type is not a base unit type or base unit type in which a fixed number of CPU units and expansion units are mounted in the base unit, but can be expanded by connecting expansion units to the CPU unit with connectors on the respective outer surfaces. There are stackable connection types.

  In the stackable connection type, unlike the base unit type, the CPU unit transmits signals such as a clock and data for controlling the expansion unit through a serial bus. With this stackable connection type programmable controller, if the number of expansion units connected to the CPU unit increases due to the expansion of its application scale, the bus wiring length from the CPU unit becomes longer, the bus capacitive load, noise mixing, etc. As a result, the waveform quality of the signal deteriorates. For this reason, there is a restriction on the number of expansion units of the expansion unit.

Therefore, it is conceivable to improve the signal quality by inserting a buffer for signal waveform shaping into the serial bus in order to eliminate this restriction. However, if the number of buffers increases due to an increase in the number of expansion units of the expansion unit, even if the signal waveform quality is improved, the signal propagation is significantly delayed and the communication speed is significantly reduced. Furthermore, coexistence of communication quality and communication speed, such as an expansion unit with a buffer inserted and an expansion unit without a buffer mixed, reduces the overall balance of communication quality and communication speed of the entire signal. It becomes difficult.
JP 2002-108422 A

  Therefore, the problem to be solved by the present invention is that signals can be transmitted according to required bus specifications such as communication speed or communication quality, and balance between communication quality and communication speed, and those in a signal serial transmission system. It is possible to achieve both.

  In the signal serial transmission system according to the present invention, signal transmission units are connected in a plurality of stages and in a stackable manner, and a plurality of serial buses that transmit the same signal are wired in parallel in each signal transmission unit, and the number of wirings of the serial buses The number of connection stages of signal transmission units within one cycle is set so that a buffer is inserted into one serial bus that is different for each signal transmission unit within the cycle, so that a buffer is inserted into the same serial bus every cycle. Thus, the above-mentioned control of the number of serial buses enables the required bus specification to be supported.

  According to the present invention, even if the bus wiring length increases due to an increase in the number of connection stages of the signal transmission unit, the signal waveform shaping into one serial bus that is periodically different in the connection order of the signal transmission units within each signal transmission unit. Since a buffer is connected to the same serial bus so that the buffer is inserted every cycle, control of the number of wirings of the serial bus can suppress signal delay and degrade signal waveform quality. Compatibility can be easily controlled.

  For example, if the number of serial buses is reduced, the number of buffer connections for the same serial bus line length increases, and signal waveform quality deterioration can be suppressed. On the other hand, if the number of serial buses is increased, the same serial bus line length Since the number of buffers connected to the network can be reduced and the signal delay can be suppressed to improve the communication speed, the user should select which bus specification to prioritize according to the application of the signal serial transmission system. Will be able to.

  In particular, in the present invention, unlike the conventional case, a signal with unbalanced signal quality or signal transmission speed is transmitted in each signal transmission unit by controlling the number of inserted buffers in the same serial bus, Within one cycle, one buffer can be inserted into any serial bus, and signals are transmitted in a balanced manner with equal signal quality and equal signal transmission speed for each signal transmission unit. Will be able to. As a result, even if a signal transmission unit is added for system use, the bus specifications required for the use can be easily accommodated.

  According to the present invention, it is possible to comply with required bus specifications such as emphasizing communication speed or emphasizing communication quality simply by controlling the number of serial bus lines.

  Hereinafter, a signal serial transmission system according to an embodiment of the present invention will be described with reference to the accompanying drawings. In the embodiment, the signal serial transmission system is applied to a PLC (programmable controller). The PLC can be used as a control device for factory automation (FA) installed in a production factory, for example. In the PLC, the building block type is composed of a plurality of units. Examples of the plurality of units include a power supply unit, a CPU unit, an I / O unit, and a communication unit. The CPU unit includes a CPU, an I / O memory, a program memory, and the like. The CPU performs an IN refresh process for fetching a signal input from the I / O unit into the I / O memory, and a sequence in the program memory. Performs the operation based on the program, writes the result of the operation execution to the I / O memory and sends it to the I / O unit, then performs the OUT refresh process, and then sends / receives data to / from other PLCs on the communication network via the communication unit Or a series of processes for performing peripheral processing such as data transmission / reception with an external PC or the like via a communication port provided in the CPU unit is cyclically repeated. Sensors and actuators are connected to the I / O unit. The sensor or the like senses the state of the control machine or device and inputs the information to the I / O unit, and the actuator or the like drives the control device in response to the output from the I / O unit.

  In the embodiment, the CPU unit and other units in the above-described PLC will be described as expansion units. Further, the expansion unit is applied to an I / O unit, but is not limited to this.

  1 and 2 show a CPU unit and a plurality of extension units in the PLC, and shows a case where signals are transmitted from the CPU unit to the extension unit via two serial buses. FIG. FIG. 2 shows a state where the CPU unit as an element is not connected to the expansion unit, and FIG. 2 shows a state where the CPU unit and the expansion unit are connected.

  1 and 2, reference numeral 10 denotes a CPU unit, and 11 denotes an expansion unit such as an I / O unit. However, when the expansion unit 11 is an odd-numbered stage or an even-numbered stage, it is indicated by 11-1, 11-3... For the odd-numbered stage and 11-2, 11-4 for the even-numbered stage for convenience of explanation. The CPU unit 10 includes a connector C0 on one outer surface, and the serial bus 12 is branched into two from the signal transmission / reception unit 10a. The branched serial buses 13a and 13b are connected to the first and second output terminals c1 and c1 of the connector C0. connected to c2. It should be noted that the connector C0 of the CPU unit 10 shows only terminals for serially transmitting signals for convenience of explanation, and is not limited to the illustration.

  Each expansion unit 11 includes input and output side connectors C1 and C2 on both outer surfaces, and includes first and second input terminals ci1 and ci2, and first and second output terminals co1 and co2, respectively. The connectors C1 and C2 are also shown for convenience of explanation and are not limited to the illustration. Further, in the case of the I / O unit, the expansion unit 11 may transmit a signal from the control machine or device side to the CPU unit 10 when the signal from the CPU unit 10 is output and transmitted. Now, only the former will be described.

  In the odd-numbered expansion units 11-1, 11-3, 11-5,..., The serial bus 15a is passed between the first input terminal ci1 and the first output terminal co1 in both connectors C1, C2, and the serial bus. A buffer 16 is inserted into 15 a and the serial bus 15 a is connected to the internal circuit 17 via the buffer 16. A serial bus 15b is passed between the second input terminal ci2 and the second output terminal co2.

  Similarly, the serial bus 15a is passed between the first input terminal ci1 and the first output terminal co1 at both connectors C1, C2 to the expansion units 11-2, 11-4, 11-6. However, the buffer 16 is not inserted into the serial bus 15a, the serial bus 15b is passed between the second input terminal ci2 and the second output terminal co2, and the buffer 16 is inserted into the serial bus 15b. The serial bus 15 b is connected to the internal circuit 17 via the buffer 16.

  In the above embodiment, as shown in FIG. 2, when the CPU unit 10 is connected in the order of the expansion units 11-1, 11-2, 11-3, 11-4,. The expansion units 11-1, 11-2, 11-3, 11-4,... Are inserted into serial buses 15a, 15b that are periodically different in the connection order of the expansion units 11-1, 11-2, 11-3, 11-4. Since the buffers 16 are periodically and alternately connected to one serial bus 15a or 15b with two stages of −3, 11-4... As one period, for example, two-stage expansion units 11-1, 11- 2, 11-3, 11-4..., The signal waveform is shaped by only one buffer 16 to ensure the signal quality, while the signal delay due to the insertion of the buffer 16 is reduced.

  With reference to FIG. 3, the internal configuration of the expansion unit 11 will be described. In the expansion unit 11, the second input terminal ci2 (connection point P2) of the input side connector C1 and the first output terminal co1 (connection of the output side connector C2). The point P3) is directly connected to the serial bus 19, and the first input terminal ci1 (connection point P1) of the input side connector C1 and the second output terminal co2 (connection point P4) of the output side connector C2 are connected to the serial bus 18. And a buffer 20 is inserted in the serial bus 18.

  In this extension unit 11, no matter where it is connected to the CPU unit 10, buffers 20 are periodically and alternately connected to one serial bus 18 with two stages as one cycle. While the signal waveform is shaped at 20 to ensure the signal quality, the number of insertions of the buffer 20 can be reduced by one in the above-mentioned period, and the delay of the signal is reduced accordingly. That is, one buffer 16 can be inserted into any of the serial buses 15a and 15b within one period, and signal quality deterioration is equally suppressed for each expansion unit 11 within one period and the signal signal is balanced. Signals can be transmitted evenly at the transmission speed. As a result, even if the expansion unit 11 is added for system use, it is possible to easily cope with the bus specifications required for the use.

  The signal is transmitted from the CPU unit 10 to the expansion units 11-1, 11-2,..., But the signal is transmitted from the expansion units 11-1, 11-2,. In addition, the buffers 20a are periodically and alternately connected to one serial bus 18a with two stages as one period. In this case, for example, in the case of the expansion unit 11-1, the connection point P3a of the input side connector (not shown) and the connection point P2a of the output side connector are directly connected to the serial bus 19a. The connection point P4a and the connection point P1a of the output side connector are connected to the serial bus 18a, and the buffer 20a is inserted into the serial bus 18a. The serial buses 14a and 14b are processed by the receiving side OR gate 23 and received by the signal transmitting / receiving unit 10a and the like. The OR gate 23 is shown for convenience of explanation, and is not limited to the illustration.

  4 (a) and 4 (b), the expansion unit 11 is provided with bus connection control units 21 and 22 between both the input side and output side connectors C1 and C2. In FIG. 4 (a), the serial bus 15a is provided. Are connected to the buffer 16 by bus connection control indicated by solid lines in the bus connection control units 21 and 22, and the buffer 16 is not connected to the serial bus 15b as indicated by dotted lines. In FIG. 4B, the buffer 16 is inserted and connected to the serial bus 15a by the bus connection control units 21 and 22 as shown by dotted lines, and the buffer 16 is not connected to the serial bus 15b as shown by solid lines. Therefore, if the expansion unit 11 shown in FIG. 4 is used, “2”, which is the number of wires of the serial buses 15a and 15b, is set as one cycle in each expansion unit 11 regardless of the position of the expansion unit 11. The buffers 16 can be inserted into the serial buses 15a and 15b periodically alternately according to the connection order.

  From the above, in the embodiment, the number of serial bus lines is “2” of the serial buses 15a and 15b. However, as shown in FIG. 5, the number of serial bus lines is “3” of the serial buses 15a, 15b and 15c. Alternatively, as shown in FIG. 6, the number of serial bus lines may be “4” of the serial buses 15a, 15b, 15c, and 15d. Alternatively, the number of serial bus wires may be larger.

  When the number of serial bus wiring is “2”, the cycle for connecting a buffer to the same serial bus is one of two expansion units, but any expansion unit is connected to the expansion unit. A buffer is inserted into the serial bus to be processed. In this case, the number of buffers inserted in a serial bus having a fixed bus wiring length increases and the signal transmission speed decreases, but the signal quality improves.

  When the number of serial bus wiring is “3”, the cycle for connecting buffers to the same serial bus is one of the three expansion units, but any expansion unit is connected to the expansion unit. A buffer is inserted into the serial bus to be processed. In this case, the number of buffers inserted into the serial bus having a fixed bus wiring length is less than that in the case of the serial bus wiring number “2”, so that the signal quality is higher than that in the case of the serial bus wiring number “2”. The signal transmission speed is improved as compared with the case where the number of serial bus wires is “2”.

  When the number of serial bus wires is “4”, the cycle for connecting buffers to the same serial bus is one of the four expansion units, but any expansion unit is connected to the expansion unit. A buffer is inserted into the serial bus to be processed. In this case, the number of buffers inserted into the serial bus having a fixed bus wiring length is smaller than that of the serial bus wiring number “3”, so that the signal quality is higher than that of the serial bus wiring number “3”. However, the signal transmission speed is improved as compared with the case where the number of serial bus wires is “3”.

  That is, by controlling the number of serial bus lines, the number of buffers connected to a certain bus line length can be increased or decreased to control both signal waveform deterioration and signal transmission speed.

  As described above, in the embodiment, the waveform quality of the transmission signal and the signal transmission speed in each expansion unit can be easily controlled by controlling the number of serial bus lines.

FIG. 1 is a diagram showing components of a PLC provided with a signal serial transmission system according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a state in which the PLC is configured when the number of serial bus lines is “2”. FIG. 3 is a diagram illustrating a connection state between the CPU unit and the extension unit. FIG. 4 is a diagram illustrating a modification of the extension unit. FIG. 5 is a diagram illustrating a configuration of the PLC when the number of serial bus wirings is “3”. FIG. 6 is a diagram showing the configuration of the PLC when the number of serial bus lines is “4”.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 CPU unit 10a Signal transmission / reception part in CPU unit 11 Expansion unit 12 Main serial bus in CPU unit 13a, 13b Serial bus in CPU unit 14a, 14b Serial bus in CPU unit 15a, 15b, 15c, 15d Serial bus in expansion unit 16 Buffer 17 Internal circuit 18, 18a Serial bus in expansion unit 19, 19a Serial bus in expansion unit 20, 20a Buffer 21 Bus connection control unit 22 Bus connection control unit 23 CPU unit OR gate C0 CPU unit connector c1 CPU unit first Output terminal c2 CPU unit second output terminal C1 Expansion unit connector ci1 First expansion unit input terminal ci2 Expansion unit second input terminal C2 Expansion unit connector co 1 First output terminal in expansion unit co2 Second output terminal in expansion unit P1, P1a Connection point P2, P2a Connection point P3, P3a Connection point P4, P4a Connection point

Claims (1)

  A plurality of signal transmission units are connected in a stackable manner, and a plurality of serial buses that transmit the same signal are connected in parallel in each signal transmission unit, and the number of wirings of the serial buses is equal to the number of signal transmission units within one cycle. As the number of connection stages, a buffer is inserted into one serial bus that is different for each signal transmission unit within the cycle, so that a buffer is inserted into the same serial bus every cycle. A signal serial transmission system characterized by being able to meet the required bus specifications.

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