JP4447496B2 - Bus control system - Google Patents

Description

  The present invention relates to a bus control system in which a plurality of slave devices and a master device that controls each slave device by specifying a device address assigned to each slave device are connected via a bus.

  Conventionally, an I2C (Inter Integrated Circuit) bus is known as an interface for transmitting information between devices. FIG. 6 is a block diagram showing a configuration of a conventional I2C bus control system. As shown in FIG. 6, a master device 101 and eight slave devices 201 to 208 are connected to the I2C bus 300.

  In the conventional I2C specification, when the same type of I2C slave device is connected to the I2C bus, only up to eight devices can be connected. This is because among the 7-bit device address specified by the I2C master device, the upper 4 bits are assigned to identify the type of device, and the remaining 3 bits are assigned to identify individual devices. It is. Therefore, as a technique for connecting nine or more I2C slave devices to the I2C bus, for example, there are Patent Document 1 and Patent Document 2.

  For example, in Patent Document 1, a control block is provided on an I2C bus in addition to an I2C master device and eight or more I2C slave devices. This control block has a memory inside, and can control which of the eight or more I2C slave devices is activated in advance.

  In other words, if you want to access any one of the eight or more I2C slave devices, activate the group that includes the I2C slave device in advance in the control block, and then operate the I2C slave device. Access can be made distinct from other overlapping I2C slave devices.

Also, for example, in Patent Document 2, an I2C bus multiplexer is arranged between an I2C master device and eight or more I2C slave devices. The I2C bus multiplexer switches the output from the I2C master device to the I2C slave device by the selector, and the switching is performed by the I2C master device operating the I2C bus multiplexer. When viewed from the I2C master device, the I2C bus multiplexer is also one of the I2C slave devices.
Japanese Patent Laid-Open No. 7-200458 Japanese Patent No. 3320657

  In the above-mentioned Patent Document 1, the I2C slave device to be used is activated by supplying power, and the power supplied to the I2C slave device is deactivated. However, this technique is not applicable to every case.

  For example, when the I2C slave device is a volatile memory or the like, data is erased by inactivating the volatile memory. Therefore, this technique cannot be used when it is desired to keep the data in the volatile memory. In addition, switching of the I2C slave device to be operated requires a switching instruction operation for the control block, which complicates the operation.

  Similarly, in the case of the above-described Patent Document 2, when the I2C slave device to be operated is switched, a switching instruction operation for the I2C bus multiplexer is necessarily required, and the operation becomes complicated.

  Moreover, what can be said in common in both patent documents is that it cannot support multi-master. That is, in the specification of the I2C bus, it is assumed that a plurality of I2C master devices exist on the bus. However, in Patent Documents 1 and 2, even if an I2C master device exists on one I2C bus side to which an I2C slave device group is connected, it exceeds the control block and the I / O expander, and the other I2C The bus side cannot be operated.

  The present invention has been made in order to solve the above-described problems. It eliminates the need for complicated bus switching operations, and allows more than the number of slave devices connected in advance determined in the specifications to be connected to the bus. An object of the present invention is to provide a bus control system that can be used.

  A bus control system according to the present invention is a bus control system in which a plurality of slave devices and a master device that controls each slave device by specifying a device address assigned to each slave device are connected via a bus. A first bus to which the master device and a plurality of slave devices are connected, a second bus to which at least one slave device is connected, and the first bus and the second bus are connected. A first connection circuit, wherein the device address includes device type information for identifying a device type, and the master device includes device type information of a plurality of slave devices connected to the first bus; Outputs data including different first device type information to the first bus, and the first connection circuit is input from the first bus. The first device type information included in the data that has been converted to device type information of the at least one slave device connected to the second bus, and outputs to the second bus.

  According to this configuration, the master device that controls each slave device by designating the device address assigned to each slave device by the first bus is connected to the plurality of slave devices, and the second bus is used to connect the master device. At least one slave device is connected, and the first bus and the second bus are connected by the first connection circuit. The device address includes device type information for identifying the type of device. Then, the master device outputs data including the first device type information different from the device type information of the plurality of slave devices connected to the first bus to the first bus. Thereafter, when data is input from the first bus, the first device type information included in the data input from the first bus is connected to the second bus by the first connection circuit. It is converted into device type information of one slave device and output to the second bus.

  Therefore, since the device type information different from the device type information of the slave device connected to the first bus is converted into the device type information of at least one slave device connected to the second bus, it is complicated. The bus switching operation is not required, and more slave devices than the number of slave devices connected in advance can be connected to the bus.

  In the above bus control system, a master device is connected to the second bus, and the master device connected to the second bus is a device of at least one slave device connected to the second bus. Data including second device type information different from the type information is output to the second bus, and the first connection circuit includes second device type information included in the data input from the second bus. Is converted into device type information of a plurality of slave devices connected to the first bus, and is output to the first bus.

  According to this configuration, the master device is connected to the second bus. The master device connected to the second bus outputs data including second device type information different from the device type information of at least one slave device connected to the second bus to the second bus. Is done. Then, the first connection circuit converts the second device type information included in the data input from the second bus into device type information of a plurality of slave devices connected to the first bus. To the other bus.

  Therefore, even if the master device exists on both the first bus and the second bus, the master device connected to the first bus is not connected to the slave device connected to the second bus. A master device that can be operated and is connected to the second bus can operate a slave device that is connected to the first bus. For example, the master device can support a multi-master on the I2C bus. it can.

  The bus control system may further include a third bus to which at least one slave device is connected, and a second connection circuit that connects the second bus and the third bus, The device is different from the device type information of a plurality of slave devices connected to the first bus, the device type information of at least one slave device connected to the second bus, and the first device type information. Data including third device type information is output to the first bus, and the first connection circuit includes the device type information included in the data input from the first bus as the third device type information. The second connection circuit outputs the third device type information included in the data input from the second bus to the third bus as it is. Converting the device type information of the at least one slave device is connected, it is preferable to output to the third bus.

  According to this configuration, at least one slave device is connected by the third bus, and the second bus and the third bus are connected by the second connection circuit. The device type information of a plurality of slave devices connected to the first bus by the master device, the device type information of at least one slave device connected to the second bus, and the first device type information Data including different third device type information is output to the first bus. When data is input from the first bus, when the device type information included in the data input from the first bus is the third device type information by the first connection circuit, the second bus is used as it is. Is output. After that, when data is input from the second bus, at least one of the third device type information included in the data input from the second bus is connected to the third bus by the second connection circuit. It is converted into device type information of one slave device and output to the third bus.

  Therefore, the first bus, the second bus, and the third bus are connected, and the device type information of the slave device connected to the first bus, the device type information of the slave device connected to the second bus Since the device type information different from the first device type information is converted into the device type information of at least one slave device connected to the third bus, a plurality of slave devices are further connected to the bus. be able to.

  In the above bus control system, the fourth bus to which at least one slave device is connected, and the first bus and the fourth bus so that the fourth bus is in parallel with the second bus. A fourth connection type different from the first device type information and the device type information of the plurality of slave devices connected to the first bus. Data including information is output to the first bus, and the third connection circuit connects at least the fourth device type information included in the data input from the first bus to the fourth bus. It is preferable that the information is converted into device type information of one slave device and output to the fourth bus.

  According to this configuration, at least one slave device is connected by the fourth bus, and the first bus and the second bus are arranged in parallel with the second bus by the third connection circuit. 4 buses are connected. Then, the master device outputs data including device type information of a plurality of slave devices connected to the first bus and fourth device type information different from the first device type information to the first bus. The Thereafter, when data is input from the first bus, at least one of the fourth device type information included in the data input from the first bus is connected to the fourth bus by the third connection circuit. Is converted into device type information of one slave device and output to the fourth bus.

  Therefore, the device type information different from the device type information and the first device type information of the slave device connected to the first bus is connected to the first bus, the second bus, and the fourth bus, Since it is converted into device type information of at least one slave device connected to the fourth bus, a plurality of slave devices can be further connected to the bus.

  In the above bus control system, the bus is preferably an I2C bus. According to this configuration, since the bus is an I2C bus, it is possible to connect the same type of slave devices equal to or greater than the number of the same type of slave devices (eight units) determined in advance in the specifications of the I2C bus to the bus. it can.

  According to the present invention, device type information different from the device type information of the slave device connected to the first bus is converted into device type information of at least one slave device connected to the second bus. Therefore, complicated bus switching operation is unnecessary, and more slave devices than the number of slave devices connected in advance can be connected to the bus.

  Hereinafter, a bus control system according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the bus control system according to the first embodiment of the present invention. The bus control system shown in FIG. 1 includes an I2C (Inter Integrated Circuit) bus 3a to which a master device 1 and a plurality of slave devices 2a to 2h are connected, and a plurality of slave devices 2i to 2p (slave devices 2i and 2p in FIG. 1). 2m (only 2m is illustrated) is connected, and an expansion circuit 4 is connected to connect the I2C bus 3a and the I2C bus 3b.

  The master device 1 controls each slave device by designating a device address assigned to each slave device. The slave devices 2 a to 2 p are nonvolatile memories such as an EEPROM (Electrically Erasable Programmable Read-Only Memory), and are controlled by the master device 1.

  In the present embodiment, the slave devices 2a to 2p are EEPROMs. However, the present invention is not particularly limited to this, and may be a volatile memory such as a RAM (Random Access Memory) or other various devices. It may be. In the present embodiment, eight slave devices 2a to 2h of the same type are connected to the I2C bus 3a. However, the present invention is not particularly limited to this, and eight slave devices of the same type. In addition to 2a to 2h, other types of slave devices may be connected.

  Furthermore, in the present embodiment, eight slave devices 2i to 2p of the same type are connected to the I2C bus 3b. However, the present invention is not particularly limited to this, and seven or less slave devices of the same type are connected. Devices may be connected, and at least one slave device is connected. When a plurality of slave devices are connected to the I2C bus 3b, each slave device is the same type of device.

  Here, a transmission format of data output by the master device 1 on the I2C bus will be described. FIG. 2 is a diagram illustrating an example of a transmission format of data output by the master device on the I2C bus.

  As shown in FIG. 2, in the I2C bus transmission format, a device address for designating a slave device is transmitted following the start bit. The device address is 7 bits, the upper 4 bits represent device type information for identifying the type of the slave device, and the remaining 3 bits represent individual identification information of the slave device. In FIG. 2, the device type information is “1010”, which indicates that the slave device is an EEPROM.

  For example, it is assumed that the individual identification information of the slave devices 2a to 2h is “000” to “111”. At this time, when the master device 1 designates the slave device 2a, the device address is “1010000”, and when the master device 1 designates the slave device 2b, the device address is “1010001”.

  When the master device 1 controls the slave devices 2a to 2h connected to the I2C bus 3a, the master device 1 outputs data including device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a to the I2C bus 3a. .

  When the same type of slave device is connected to the I2C bus, the upper 4 bits of the device address are fixed, so that only the remaining 3 bits can be used to identify individual slave devices. Therefore, only up to eight slave devices of the same type can be connected.

  Therefore, when the master device 1 controls the slave devices 2i to 2p connected to the I2C bus 3b, the first device type different from the device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a. Data including information is output to the I2C bus 3a.

  That is, when eight or more slave devices of the same type are connected, the master device 1 sets a value other than “1010” representing EEPROM, for example, “1011”, when specifying 4 bits indicating device type information. To do. In this way, when the master device 1 outputs data with the device type information “1011”, the slave devices 2a to 2h connected to the I2C bus 3a do not respond because the device addresses do not match.

  Then, when the device type information included in the data input from the I2C bus 3a is the first device type information, the extension circuit 4 displays the first device type information included in the data input from the I2C bus 3a. The information is converted into device type information of a plurality of slave devices 2i to 2p connected to the I2C bus 3b and output to the I2C bus 3b. For example, when receiving data with device type information “1011”, the expansion circuit 4 converts the device type information from “1011” to “1010” and outputs the data to the I2C bus 3b. Then, the slave devices 2i to 2p connected to the I2C bus 3b can recognize and respond to access to the slave devices 2i to 2p.

  Here, a specific operation when the master device 1 transmits data to the slave device 2i will be described. In the following description, the device address of the slave device 2i is “1010000”.

  First, the master device 1 outputs data having a device address “1011000” to the I2C bus 3a. In this case, the slave devices 2a to 2h connected to the I2C bus 3a do not respond because the device addresses are “1010000” to “1010111”. When the device type information included in the data input from the I2C bus 3a is “1011”, the extension circuit 4 converts the device type information from “1011” to “1010” and sets the device address to “1010000”. Data is output to the I2C bus 3b. When data having a device address “1010000” is input to the I2C bus 3b, only the slave device 2i having the device address “1010000” among the slave devices 2i to 2p connected to the I2C bus 3b receives the data. Receive. Then, the slave device 2 i responds to the master device 1.

  In this way, the master device 1 that controls each slave device by specifying the device address assigned to each slave device by the I2C bus 3a and the plurality of slave devices 2a to 2h are connected, and the I2C bus 3b A plurality of slave devices 2 i to 2 p are connected, and the extension circuit 4 connects the I2C bus 3 a and the I2C bus 3 b. The device address includes device type information for identifying the type of device. Then, the master device 1 outputs data including first device type information different from the device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a to the I2C bus 3a. Thereafter, when data is input from the I2C bus 3a, the expansion circuit 4 causes the first device type information included in the data input from the I2C bus 3a to be connected to the plurality of slave devices 2i to 2p connected to the I2C bus 3b. And is output to the I2C bus 3b.

  Therefore, device type information different from the device type information of the slave devices 2a to 2h connected to the I2C bus 3a is converted into device type information of the plurality of slave devices 2i to 2p connected to the I2C bus 3b. A complicated bus switching operation is unnecessary, and more slave devices than the number of slave devices connected in advance can be connected to the bus.

  In addition, since the bus is an I2C bus, it is possible to connect and control more than the number of slave devices connected in advance (eight) according to the specifications of the I2C bus to the bus.

  In the present embodiment, the I2C bus 3a corresponds to an example of the first bus, the I2C bus 3b corresponds to an example of the second bus, and the expansion circuit 4 corresponds to an example of the first connection circuit. .

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the first embodiment described above, only a plurality of slave devices are connected to the I2C bus 3b. In the second embodiment, a master device and a plurality of slave devices are connected to the I2C bus 3b. .

  FIG. 3 is a block diagram showing the configuration of the bus control system according to the second embodiment of the present invention. The bus control system shown in FIG. 3 includes an I2C bus 3a to which a master device 1a and a plurality of slave devices 2a to 2h are connected, and an I2C bus 3b to which a master device 1b and a plurality of slave devices 2i to 2p are connected. The I2C bus 3a and the expansion circuit 4 for connecting the I2C bus 3b.

  The master devices 1a and 1b control the slave devices 2a to 2p by designating device addresses assigned to the slave devices 2a to 2p. The slave devices 2a to 2p are nonvolatile memories such as an EEPROM, for example, and are controlled by the master devices 1a and 1b.

  In the present embodiment, the slave devices 2a to 2p are EEPROMs. However, the present invention is not particularly limited to this, and may be a volatile memory such as a RAM or other various devices. . In the present embodiment, eight slave devices 2a to 2h of the same type are connected to the I2C bus 3a. However, the present invention is not particularly limited to this, and eight slave devices of the same type. In addition to 2a to 2h, other types of slave devices may be connected.

  Furthermore, in the present embodiment, eight slave devices 2i to 2p of the same type are connected to the I2C bus 3b. However, the present invention is not particularly limited to this, and seven or less slave devices of the same type are connected. Devices may be connected, and at least one slave device is connected. When a plurality of slave devices are connected to the I2C bus 3b, each slave device is the same type of device.

  When the master device 1a connected to the I2C bus 3a controls the slave devices 2a to 2h connected to the I2C bus 3a, data including device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a Is output to the I2C bus 3a. When the master device 1a controls the plurality of slave devices 2i to 2p connected to the I2C bus 3b, the master device 1a is different from the device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a. Data including device type information is output to the I2C bus 3a.

  When the master device 1b connected to the I2C bus 3b controls the slave devices 2i to 2p connected to the I2C bus 3b, data including device type information of the plurality of slave devices 2i to 2p connected to the I2C bus 3b Is output to the I2C bus 3b. Further, when the master device 1b controls the plurality of slave devices 2a to 2h connected to the I2C bus 3a, the master device 1b is different from the device type information of the plurality of slave devices 2i to 2p connected to the I2C bus 3b. Data including device type information is output to the I2C bus 3b.

  When the device type information included in the data input from the I2C bus 3a is the first device type information, the extension circuit 4 converts the first device type information included in the data input from the I2C bus 3a into the I2C bus. The information is converted into device type information of a plurality of slave devices 2i to 2p connected to 3b and output to the I2C bus 3b.

  Further, when the device type information included in the data input from the I2C bus 3b is the second device type information, the extension circuit 4 displays the second device type information included in the data input from the I2C bus 3b. The information is converted into device type information of a plurality of slave devices 2a to 2h connected to the I2C bus 3a, and is output to the I2C bus 3a.

  Here, a specific operation when the master device 1b transmits data to the slave device 2a will be described. In the following description, the device address of the slave device 2a is “1010000”. The operation when the master device 1a transmits data to the slave devices 2i to 2p is the same as the operation when the master device 1 according to the first embodiment transmits data to the slave devices 2i to 2p. Description is omitted.

  First, the master device 1b outputs data having a device address “1011000” to the I2C bus 3b. In this case, the slave devices 2i to 2p connected to the I2C bus 3b do not respond because the device addresses are “1010000” to “1010111”. When the device type information included in the data input from the I2C bus 3b is “1011”, the extension circuit 4 converts the device type information from “1011” to “1010” and sets the device address to “1010000”. Data is output to the I2C bus 3a. When data with the device address “1010000” is input to the I2C bus 3a, only the slave device 2a with the device address “1010000” among the slave devices 2a to 2h connected to the I2C bus 3a receives the data. Receive. Then, the slave device 2a responds to the master device 1b.

  Thus, the master device 1b and the plurality of slave devices 2i to 2p are connected to the I2C bus 3b. The master device 1b connected to the I2C bus 3b outputs data including second device type information different from the device type information of the plurality of slave devices 2i to 2p connected to the I2C bus 3b to the I2C bus 3b. The Then, the extension circuit 4 converts the second device type information included in the data input from the I2C bus 3b into device type information of a plurality of slave devices connected to the I2C bus 3a, and outputs the device type information to the I2C bus 3a. The

  Therefore, even if there are master devices on both the I2C bus 3a and the I2C bus 3b, the master device 1a connected to the I2C bus 3a does not connect the slave devices 2i to 2p connected to the I2C bus 3b. The master device 1b connected to the I2C bus 3b can operate the slave devices 2a to 2h connected to the I2C bus 3a, and can correspond to the multi-master on the I2C bus. it can.

  In the present embodiment, the I2C bus 3a corresponds to an example of the first bus, the I2C bus 3b corresponds to an example of the second bus, and the expansion circuit 4 corresponds to an example of the first connection circuit. .

(Third embodiment)
Next, a third embodiment of the present invention will be described. In the first embodiment described above, the I2C bus 3a and the I2C bus 3b are connected via the expansion circuit 4, but in the third embodiment, the I2C bus 3b and the I2C bus 3c are further expanded. They are connected in series via the circuit 4b.

  FIG. 4 is a block diagram showing the configuration of the bus control system according to the third embodiment of the present invention. The bus control system shown in FIG. 4 includes an I2C bus 3a to which a master device 1 and a plurality of slave devices 2a to 2h are connected, an I2C bus 3b to which a plurality of slave devices 2i to 2p are connected, and a plurality of slave devices. 2q to 2x (only the slave devices 2q and 2u are shown in FIG. 4), an expansion circuit 4a that connects the I2C bus 3a and the I2C bus 3b, an I2C bus 3b and an I2C bus 3c, And an extension circuit 4b for connecting the two.

  The master device 1 controls the slave devices 2a to 2x by designating device addresses assigned to the slave devices 2a to 2x. The slave devices 2 a to 2 x are non-volatile memories such as EEPROM, for example, and are controlled by the master device 1.

  In the present embodiment, the slave devices 2a to 2x are EEPROMs. However, the present invention is not particularly limited to this, and may be a volatile memory such as a RAM or other various devices. . In the present embodiment, eight identical slave devices 2a to 2h and 2i to 2p are connected to the I2C bus 3a and the I2C bus 3b, respectively, but the present invention is not particularly limited to this. In addition to the eight slave devices 2a to 2h and 2i to 2p of the same type, other types of slave devices may be connected respectively.

  Furthermore, in the present embodiment, eight slave devices 2q to 2x of the same type are connected to the I2C bus 3c, but the present invention is not particularly limited to this, and seven or less slave devices of the same type are connected. Devices may be connected, and at least one slave device is connected. When a plurality of slave devices are connected to the I2C bus 3c, each slave device is the same type of device.

  When the master device 1 controls the slave devices 2a to 2h connected to the I2C bus 3a, the master device 1 outputs data including device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a to the I2C bus 3a. .

  When the master device 1 controls the slave devices 2i to 2p connected to the I2C bus 3b, the first device type different from the device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a. Data including information is output to the I2C bus 3a.

  Further, when the master device 1 controls the slave devices 2q to 2x connected to the I2C bus 3c, the master device 1 is connected to the device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a and the I2C bus 3b. Data including device type information of the plurality of slave devices 2i to 2p and third device type information different from the first device type information specified by the master device 1 for converting the device type information in the extension circuit 4a. Output to the I2C bus 3a.

  When the device type information included in the data input from the I2C bus 3a is the first device type information, the extension circuit 4a converts the first device type information into a plurality of slave devices 2i to 2 connected to the I2C bus 3b. The data is converted into 2p device type information, and the data is output to the I2C bus 3b. Further, when the device type information included in the data input from the I2C bus 3a is the third device type information, the extension circuit 4a uses the third device type information as the slave device 2i connected to the I2C bus 3b. The data is output to the I2C bus 3b as it is without being converted into device type information of ˜2p.

  When the device type information included in the data input from the I2C bus 3b is the third device type information, the extension circuit 4b converts the third device type information included in the data input from the I2C bus 3b into the I2C bus. The device type information of the plurality of slave devices 2q to 2x connected to 3c is converted, and the data is output to the I2C bus 3c.

  Here, a specific operation when the master device 1 transmits data to the slave device 2q will be described. In the following description, the device address of the slave device 2q is “1010000”. The operation when the master device 1 transmits data to the slave devices 2i to 2p is the same as the operation when the master device 1 according to the first embodiment transmits data to the slave devices 2i to 2p. Description is omitted.

  First, the master device 1 outputs data having a device address “1101000” to the I2C bus 3a. In this case, the slave devices 2a to 2h connected to the I2C bus 3a do not respond because the device addresses are “1010000” to “1010111”. When the device type information included in the data input from the I2C bus 3a is “1101”, the extension circuit 4a does not convert the device type information, and directly converts the data with the device address “1101000” into the I2C bus 3b. Output to. In this case, the slave devices 2i to 2p connected to the I2C bus 3b do not respond because the device addresses are “1010000” to “1010111”.

  When the device type information included in the data input from the I2C bus 3b is “1101”, the extension circuit 4b converts the device type information from “1101” to “1010” and sets the device address to “1010000”. Data is output to the I2C bus 3c. When data having a device address “1010000” is input to the I2C bus 3c, only the slave device 2q having the device address “1010000” among the slave devices 2q to 2x connected to the I2C bus 3c receives the data. Receive. Then, the slave device 2q responds to the master device 1.

  Thus, the plurality of slave devices 2q to 2x are connected by the I2C bus 3c, and the I2C bus 3b and the I2C bus 3c are connected by the expansion circuit 4b. Then, by the master device 1, the device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a, the device type information of the plurality of slave devices 2i to 2p connected to the I2C bus 3b, and the master device 1 Data including third device type information different from the first device type information specified for converting the device type information in the extension circuit 4a is output to the I2C bus 3a. When data is input from the I2C bus 3a, when the device type information included in the data input from the I2C bus 3a is the third device type information by the extension circuit 4a, the third device type information is converted to the I2C bus. The data is output to the I2C bus 3b as it is without being converted into the device type information of the slave devices 2i to 2p connected to 3b. Thereafter, when data is input from the I2C bus 3b, the extension circuit 4b causes the third device type information included in the data input from the I2C bus 3b to be a plurality of slave devices 2q to 2x connected to the I2C bus 3c. And is output to the I2C bus 3c.

  Accordingly, the I2C bus 3a, the I2C bus 3b, and the I2C bus 3c are connected, and device type information of the slave devices 2a to 2h connected to the I2C bus 3a, and device types of the slave devices 2i to 2p connected to the I2C bus 3b Information and device type information different from the first device type information designated by the master device 1 for converting the device type information in the extension circuit 4a are the slave devices 2q to 2x connected to the I2C bus 3c. Since it is converted into device type information, a plurality of slave devices can be further connected to the bus.

  In the present embodiment, the three I2C buses of the I2C bus 3a, the I2C bus 3b, and the I2C bus 3c are connected by the expansion circuits 4a and 4b. However, the present invention is not particularly limited to this, and the expansion circuit Four or more I2C buses may be connected via the terminal.

  Also in this embodiment, as in the second embodiment, a master device may be connected to the I2C bus 3b, and further, a master device may be connected to the I2C bus 3c.

  In the present embodiment, the I2C bus 3a corresponds to an example of a first bus, the I2C bus 3b corresponds to an example of a second bus, and the I2C bus 3c corresponds to an example of a third bus. The extension circuit 4a corresponds to an example of a first connection circuit, and the extension circuit 4b corresponds to an example of a second connection circuit.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described. In the third embodiment described above, the I2C bus 3a, the I2C bus 3b, and the I2C bus 3c are connected in series via the expansion circuits 4a and 4b. In the fourth embodiment, the I2C bus 3c is connected. Are connected in parallel to the I2C bus 3b via the expansion circuit 4b.

  FIG. 5 is a block diagram showing a configuration of a bus control system according to the fourth embodiment of the present invention. The bus control system shown in FIG. 5 includes an I2C bus 3a to which the master device 1 and a plurality of slave devices 2a to 2h are connected, and a plurality of slave devices 2i to 2p (only the slave device 2i is shown in FIG. 5). An I2C bus 3b to be connected, an I2C bus 3c to which a plurality of slave devices 2q to 2x (only the slave device 2q is shown in FIG. 5) is connected, and an expansion circuit 4a to connect the I2C bus 3a and the I2C bus 3b And an expansion circuit 4b for connecting the I2C bus 3a and the I2C bus 3c.

  The master device 1 controls the slave devices 2a to 2x by designating device addresses assigned to the slave devices 2a to 2x. The slave devices 2 a to 2 x are non-volatile memories such as EEPROM, for example, and are controlled by the master device 1.

  In the present embodiment, the slave devices 2a to 2x are EEPROMs. However, the present invention is not particularly limited to this, and may be a volatile memory such as a RAM or other various devices. . In the present embodiment, eight slave devices 2a to 2h of the same type are connected to the I2C bus 3a. However, the present invention is not particularly limited to this, and eight slave devices of the same type. In addition to 2a to 2h, other types of slave devices may be connected.

  Further, in the present embodiment, eight slave devices 2i to 2x of the same type are connected to the I2C bus 3b and the I2C bus 3c, respectively. However, the present invention is not particularly limited to this, and each of the seven slave devices 2i to 2x. The following slave devices of the same type may be connected, each of which is connected with at least one slave device. When a plurality of slave devices are connected to the I2C bus 3b and the I2C bus 3c, respectively, each slave device is the same type of device.

  When the master device 1 controls the slave devices 2a to 2h connected to the I2C bus 3a, the master device 1 outputs data including device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a to the I2C bus 3a. .

  When the master device 1 controls the slave devices 2i to 2p connected to the I2C bus 3b, the first device type different from the device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a. Data including information is output to the I2C bus 3a.

  Further, when the master device 1 controls the slave devices 2q to 2x connected to the I2C bus 3c, the device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a, and the master device 1 is an extension circuit. The data including the fourth device type information different from the first device type information designated for converting the device type information in 4a is output to the I2C bus 3a.

  When the device type information included in the data input from the I2C bus 3a is the first device type information, the extension circuit 4a converts the first device type information into a plurality of slave devices 2i to 2 connected to the I2C bus 3b. The data is converted into 2p device type information, and the data is output to the I2C bus 3b.

  When the device type information included in the data input from the I2C bus 3a is the fourth device type information, the extension circuit 4b converts the fourth device type information included in the data input from the I2C bus 3a into the I2C bus. The device type information of the plurality of slave devices 2q to 2x connected to 3c is converted, and the data is output to the I2C bus 3c.

  Here, a specific operation when the master device 1 transmits data to the slave device 2q will be described. In the following description, the device address of the slave device 2q is “1010000”. The operation when the master device 1 transmits data to the slave devices 2i to 2p is the same as the operation when the master device 1 according to the first embodiment transmits data to the slave devices 2i to 2p. Description is omitted.

  First, the master device 1 outputs data having a device address “1101000” to the I2C bus 3a. In this case, the slave devices 2a to 2h connected to the I2C bus 3a do not respond because the device addresses are “1010000” to “1010111”. Also, the extension circuit 4a sets the device type information “1011” to the slave devices 2i to 2p connected to the I2C bus 3b only when the device type information included in the data input from the I2C bus 3a is “1011”. Device type information “1010”. Therefore, the extension circuit 4a does not convert the device type information when the device type information included in the data input from the I2C bus 3a is “1101”.

  When the device type information included in the data input from the I2C bus 3a is “1101”, the extension circuit 4b converts the device type information from “1101” to “1010” and sets the device address to “1010000”. Data is output to the I2C bus 3c. When data having a device address “1010000” is input to the I2C bus 3c, only the slave device 2q having the device address “1010000” among the slave devices 2q to 2x connected to the I2C bus 3c receives the data. Receive. Then, the slave device 2q responds to the master device 1.

  Thus, the plurality of slave devices 2q to 2x are connected by the I2C bus 3c, and the I2C bus 3c is connected to the I2C bus 3a in parallel with the I2C bus 3b by the extension circuit 4b. The device type information of the plurality of slave devices 2a to 2h connected to the I2C bus 3a by the master device 1 and the first device type designated by the master device 1 for converting the device type information in the extension circuit 4a Data including fourth device type information different from the information is output to the I2C bus 3a. Thereafter, when data is input from the I2C bus 3a, the extension circuit 4b causes the fourth device type information included in the data input from the I2C bus 3a to be a plurality of slave devices 2q to 2x connected to the I2C bus 3c. And is output to the I2C bus 3c.

  Therefore, the I2C bus 3a, the I2C bus 3b, and the I2C bus 3c are connected, and the device type information of the slave device connected to the I2C bus 3a and the master device 1 are designated to convert the device type information in the expansion circuit 4a. Since device type information different from the first device type information to be converted into device type information of the plurality of slave devices 2q to 2x connected to the I2C bus 3c, further connecting a plurality of slave devices to the bus Can do.

  In the present embodiment, the three I2C buses of the I2C bus 3a, the I2C bus 3b, and the I2C bus 3c are connected by the expansion circuits 4a and 4b. However, the present invention is not particularly limited to this, and the I2C bus is not limited thereto. A plurality of extension circuits may be connected to 3a in parallel, and four or more I2C buses may be connected via the plurality of extension circuits.

  Also in this embodiment, as in the second embodiment, a master device may be connected to the I2C bus 3b, and further, a master device may be connected to the I2C bus 3c.

  In the present embodiment, the I2C bus 3a corresponds to an example of the first bus, the I2C bus 3b corresponds to an example of the second bus, and the I2C bus 3c corresponds to an example of the fourth bus. The extension circuit 4a corresponds to an example of a first connection circuit, and the extension circuit 4b corresponds to an example of a third connection circuit.

It is a block diagram which shows the structure of the bus control system by the 1st Embodiment of this invention. It is a figure which shows an example of the transmission format of the data output by a master device in an I2C bus. It is a block diagram which shows the structure of the bus control system by the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the bus control system by the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the bus control system by the 4th Embodiment of this invention. It is a block diagram which shows the structure of the conventional I2C bus control system.

Explanation of symbols

1, 1a, 1b Master device 2a-2x Slave device 3a-3c I2C bus 4, 4a, 4b Expansion circuit

Claims (5)

A bus control system in which a plurality of slave devices and a master device that controls each slave device by specifying a device address assigned to each slave device are connected via a bus,
A first bus to which a master device and a plurality of slave devices are connected;
A second bus to which at least one slave device is connected;
A first connection circuit for connecting the first bus and the second bus;
The device address includes device type information for identifying a device type,
The master device outputs data including first device type information different from device type information of a plurality of slave devices connected to the first bus to the first bus,
The first connection circuit converts the first device type information included in the data input from the first bus into device type information of at least one slave device connected to the second bus, A bus control system for outputting to a second bus. A master device is connected to the second bus,
The master device connected to the second bus outputs data including second device type information different from the device type information of at least one slave device connected to the second bus to the second bus. ,
The first connection circuit converts second device type information included in the data input from a second bus into device type information of a plurality of slave devices connected to the first bus, 2. The bus control system according to claim 1, wherein the bus control system outputs to the bus. A third bus to which at least one slave device is connected;
A second connection circuit for connecting the second bus and the third bus;
The master device includes device type information of a plurality of slave devices connected to a first bus, device type information of at least one slave device connected to a second bus, and the first device type information. Outputs data including different third device type information to the first bus,
When the device type information included in the data input from the first bus is the third device type information, the first connection circuit outputs the data to the second bus as it is,
The second connection circuit converts the third device type information included in the data input from the second bus into device type information of at least one slave device connected to the third bus, 3. The bus control system according to claim 1, wherein the bus control system outputs to a third bus. A fourth bus to which at least one slave device is connected;
A third connection circuit for connecting the first bus and the fourth bus so that the fourth bus is in parallel with the second bus;
The master device outputs data including device type information of a plurality of slave devices connected to a first bus and fourth device type information different from the first device type information to the first bus,
The third connection circuit converts the fourth device type information included in the data input from the first bus into device type information of at least one slave device connected to the fourth bus, 3. The bus control system according to claim 1, wherein the bus control system outputs to a fourth bus.   The bus control system according to claim 1, wherein the bus is an I2C bus.

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