JP4920434B2 - Semiconductor switching element drive circuit - Google Patents

Description

  The present invention relates to a drive circuit for a semiconductor switching element, and more particularly to a drive circuit for detecting occurrence of an abnormality in a power semiconductor switching element.

  As a conventional power semiconductor element (IGBT) driving circuit, when the sampling circuit detects the gate voltage during the period when the gate voltage detection processing is permitted and the gate voltage exceeds a reference value, an abnormality in the IGBT is detected. A technique for detecting the occurrence is shown (for example, see Patent Document 1).

JP 2004-064930 A

  In the power semiconductor element (IGBT) driving circuit disclosed in Patent Document 1, the gate voltage is the reference when the OFF period from the OFF command to the ON command is short and the IGBT gate voltage is not fully reduced. There was a problem of exceeding the value and misdetecting the abnormality.

  The present invention has been made to solve the above problems, and in a drive circuit having an abnormality detection function of a semiconductor switching element, when an off period from an off command to an on command is short. The object is to improve the reliability of abnormality detection by preventing erroneous detection of abnormality.

The drive circuit for the first semiconductor switching element according to the present invention includes a control circuit for generating an on / off command based on a command from the outside, and the on / off operation is controlled by the control electrode. And an abnormality detecting means for detecting an abnormality when a control amount of the control electrode is out of a threshold range during a preset period within a turn-on transient period of the control electrode after an on command is generated from the control circuit. And an abnormality detection canceling means for stopping the abnormality detection by the abnormality detecting means when the control amount of the control electrode immediately after the ON command is generated from the control circuit is out of a predetermined range .

  The drive circuit for the second semiconductor switching element according to the present invention includes a control circuit for generating an on / off command based on a command from the outside, and the on / off operation is controlled by the control electrode. And an abnormality detecting means for detecting an abnormality when a control amount of the control electrode is out of a threshold range during a preset period within a turn-on transient period of the control electrode after an on command is generated from the control circuit. And an abnormality detection canceling means for stopping the abnormality detection by the abnormality detecting means in accordance with the length of the off period before the on command is generated from the control circuit.

The drive circuit for the first semiconductor switching element according to the present invention turns on from the off command in order to stop the abnormality detection by the abnormality detecting means when the control amount of the control electrode immediately after the on command from the control circuit is out of the predetermined range. When the off period until the command is short, it is possible to prevent erroneous detection of abnormality, and the reliability of abnormality detection is improved.
Further, the drive circuit for the second semiconductor switching element according to the present invention stops the abnormality detection by the abnormality detection means according to the length of the off period before the on command is generated from the control circuit. It is possible to prevent erroneous detection of an abnormality and improve the reliability of abnormality detection.

Embodiment 1 FIG.
A semiconductor switching element drive circuit according to Embodiment 1 of the present invention will be described below with reference to the drawings.
FIG. 1 shows a configuration of a drive circuit 500 that drives, for example, an IGBT (Insulated Gate Bipolar Transistor) in which a freewheeling diode 9 is connected in antiparallel as a semiconductor switching element.
As shown in the figure, the control circuit 2 outputs a gate command (ON / OFF command) for turning on and off the IGBT 1 to the buffer 3 based on a command from the outside, and the buffer 3 is connected via the gate resistor 4. It is connected to a gate which is a control electrode of the IGBT 1, and drives the IGBT 1 in accordance with a gate command from the control circuit 2.
Further, in a preset period determined by the sampling circuit 8, an abnormality detection circuit 7 that detects an abnormality in the gate voltage of the IGBT 1, a cutoff speed adjustment circuit 5 that slows down a cutoff speed that turns off the IGBT 1 when an abnormality is detected, And a cancel circuit 6 that outputs a cancel signal that causes the abnormality detection circuit 7 to stop abnormality detection based on the gate voltage immediately after the ON command is generated from the control circuit 2.

FIG. 2 is a circuit diagram showing a half bridge circuit to which the IGBTs 1a and 1b are applied. In FIG. 2, IGBTs 1 a and 1 b to which free-wheeling diodes 9 a and 9 b are connected in antiparallel are connected in series, and a DC power supply 10 is connected to both ends thereof. An inductive load 11 is connected between the midpoint of the IGBT 1 a and IGBT 1 b and the positive side of the DC power supply 10. Each of the IGBTs 1a and 1b includes the drive circuit 500 shown in FIG.
In general, during normal switching of the IGBT, the gate voltage when turning on is as shown by the solid line in FIG. When two IGBTs connected in series cause an arm short circuit for some reason, and a large short circuit current flows through the IGBT, the gate voltage becomes like a broken line in the figure. The drive circuit 500 detects such an IGBT short-circuit abnormality and performs a safe shut-off operation.
Here, the IGBT is applied to the half-bridge circuit, but may be applied to other circuits.

FIG. 4 is a partial detail view of the drive circuit 500 shown in FIG. 1 and shows a specific example of the buffer 3, the gate resistor 4, and the cutoff speed adjustment circuit 5. The buffer 3 is composed of two semiconductor switching elements 3a and 3b, and the gate resistor 4 is composed of an on-gate resistor 4a and an off-gate resistor 4b. The buffer 3 connects the gate of the IGBT 1 and the control voltage via the on-gate resistor 4a according to an on command from the control circuit 2, and connects the gate and the ground of the IGBT 1 via the off-gate resistor 4b according to an off command.
The cutoff speed adjusting circuit 5 is composed of a speed adjusting off-gate resistor 12 and a semiconductor switching element 13, and the speed adjusting off-gate resistor 12 has a resistance value larger than that of the normal off-gate resistor 4b. For this reason, the current value drawn from the gate terminal of the IGBT 1 is small as compared with the normal turn-off operation, and the interruption speed at the time of turn-off becomes slow. As described above, when the abnormality detection circuit 7 detects the short-circuit abnormality of the IGBT 1, the cutoff speed adjusting circuit 5 is a circuit that turns off by making the cutoff speed slower than the normal turn-off, and a large current flows. Suppresses the surge voltage generated at the time of interruption in the state where it is present to prevent damage to the IGBT 1 and safely shuts off.

  As shown in FIG. 5, a cutoff speed adjusting circuit 5a provided with a Zener diode 14 may be used. In this case, the Zener voltage of the Zener diode 14 is set to a value smaller than the threshold voltage Vth of the gate of the IGBT 1. ing. Also in this case, when the short circuit abnormality of the IGBT 1 is detected by the abnormality detection circuit 7, the interruption speed is made slower than the normal turn-off and the turn-off is performed.

FIG. 6 shows a detailed configuration example of the cancel circuit 6 and the abnormality detection circuit 7 in the overall configuration of the drive circuit 500. 7 to 9 are time charts showing waveforms of respective parts for explaining the operation of the drive circuit 500. FIG. 7 shows a case where the off period of the IGBT 1 is long, and FIG. 8 shows a case where the off period of the IGBT 1 is short. FIG. 9 shows a case where a short circuit abnormality has occurred in the IGBT 1.
First, the operation when the off period from the off command to the on command is sufficiently long and the gate voltage of the IGBT 1 is sufficiently lowered and there is no abnormality in the IGBT 1 will be described with reference to FIG. When the control signal (ON / OFF command) shown in FIG. 7A is output from the control circuit 2, the gate voltage of the IGBT 1 becomes as shown in FIG. 7B.

The sampling circuit 8 is composed of a pulse signal generator. When an ON command is input from the control circuit 2, the sampling circuit 8 outputs a pulse 8a during a preset period within the turn-on transient period (FIG. 7C). The timing and pulse width at which the pulse 8a is output depend on the characteristics of the IGBT 1 and the drive circuit 500, but are set during the turn-on transient period of the IGBT 1 so as to include a period in which a difference occurs in the gate voltage between the normal time and the short circuit abnormality. Is done.
The abnormality detection circuit 7 includes a comparator 15, and inputs the first gate voltage signal 15 a that is the gate voltage divided by the resistors 17 and 18 to the comparator 15 only during the period of the pulse 8 a from the sampling circuit 8. 15 outputs an abnormal signal when the gate voltage signal 15a is higher than a predetermined first threshold voltage 15b. The first threshold voltage 15b is set to a predetermined voltage at which a short-circuit abnormality in the gate voltage at turn-on can be detected. In this case, the first gate voltage signal 15a is equal to or lower than the first threshold voltage 15b, and the output of the comparator 15 remains Low (no abnormality) (FIG. 7 (h), FIG. 7 (i)).

  The abnormality detection circuit 7 detects the gate voltage (first gate voltage signal 15a) only during the period of the pulse 8a from the sampling circuit 8. The detection of the gate voltage generates a cancel signal from the cancellation circuit 7. Only works if not. In this case, the output of the NOT circuit 21 that receives the cancel signal from the cancel circuit 7 is High as shown in FIG. 7F, and the NAND that receives the High signal and the pulse 8a from the sampling circuit 8 as inputs. The output of the circuit 20 is Low only during the period of the pulse 8a from the sampling circuit 8 (FIG. 7 (g)). The switch 19 is controlled by the output of the NAND circuit 20, and the input of the + terminal of the comparator 15 becomes 0 when the output of the NAND circuit 20 is High, and the gate voltage (first gate) divided by the resistors 17 and 18 when Low. Voltage signal 15a).

The cancel circuit 6 includes a pulse generation circuit 27, a comparator 23, and a pulse waveform output circuit 22. The pulse generation circuit 27 generates a short ON pulse simultaneously with the ON command from the control circuit 2 (FIG. 7D). The switch 25 is controlled by the output of the pulse generation circuit 27, and the gate voltage (second gate voltage signal 23a) is input to the + terminal of the comparator 23 only during the on-pulse period. The comparator 23 outputs a High signal to the pulse waveform output circuit 22 when the second gate voltage signal 23a is higher than a predetermined second threshold voltage 23b. The pulse waveform output circuit 22 is a circuit that outputs a high pulse signal having a certain length as a cancel signal when a high signal is input.
In this way, the cancel circuit 6 detects the gate voltage immediately after the ON command from the control circuit 2 and inputs it to the comparator 23, and the gate voltage (second gate voltage signal 23a) is the predetermined second threshold voltage 23b. Is higher, the pulse waveform output circuit 22 outputs a high pulse signal of a certain length as a cancel signal. In this case, as shown in FIG. 7E, the second gate voltage signal 23a is equal to or lower than the second threshold voltage 23b, the output of the comparator 23 remains low, and no cancel signal is generated. For convenience, the output of the pulse waveform output circuit 22 and the output of the comparator 23 are not shown.

Next, an operation when the off period from the off command to the on command is short and the IGBT is turned on in a state where the gate voltage of the IGBT cannot be lowered will be described with reference to FIG. When the control signal (ON / OFF command) shown in FIG. 8A is output from the control circuit 2, the gate voltage of the IGBT 1 becomes as shown in FIG. 8B. Compared with the case shown in FIG. 7, since the off period is short, the gate voltage rises again before decreasing to 0 V, so the gate voltage at turn-on is high.
When an ON command is input from the control circuit 2, the sampling circuit 8 outputs a pulse 8a during a preset period within the turn-on transient period (FIG. 8C).

  The pulse generation circuit 27 generates a short on-pulse simultaneously with the on-command from the control circuit 2 (FIG. 8D), and the second gate voltage signal 23a is applied to the + terminal of the comparator 23 only during the on-pulse period. Entered. The comparator 23 outputs a High signal to the pulse waveform output circuit 22 when the second gate voltage signal 23a is higher than a predetermined second threshold voltage 23b. In this case, as shown in FIG. 8 (e), the second gate voltage signal 23a exceeds the second threshold voltage 23b, and the output of the comparator 23 becomes a High signal. A high pulse signal having a certain length is output as a cancel signal. This High pulse signal is output in a period including the pulse 8a generation period of the sampling circuit 8, and the output of the NOT circuit 21 that receives the High pulse signal is generated as shown in FIG. 8 (f). The output of the NAND circuit 20 that is Low in the period including the period and receives the Low signal and the pulse 8a from the sampling circuit 8 becomes High (FIG. 8 (g)). Since the switch 19 is controlled by the output of the NAND circuit 20 and the input of the + terminal of the comparator 15 becomes 0, the input of the + terminal is equal to or lower than the first threshold voltage 15b, and the output of the comparator 15 is Low (no abnormality). (FIG. 8 (h), FIG. 8 (i)).

  In this way, the cancel circuit 6 detects the second gate voltage signal 23a immediately after the ON command from the control circuit 2 and inputs it to the comparator 23, and the second gate voltage signal 23a is a predetermined second threshold voltage. When it is higher than 23b, the pulse waveform output circuit 22 outputs a high pulse signal of a certain length as a cancel signal. In this case, since the IGBT OFF period is short and the gate voltage is on without being lowered, the second gate voltage signal 23a input to the comparator 23 becomes higher than the second threshold voltage 23b, and the High pulse The signal is output as a cancel signal. As described above, the abnormality detection circuit 7 detects the gate voltage (first gate voltage signal 15a) only during the period of the pulse 8a from the sampling circuit 8. The detection of the gate voltage is performed by the cancel circuit 7. Is canceled by the high pulse signal from. In this case, the IGBT 1 does not cause a short-circuit abnormality, but the gate voltage becomes transiently higher than normal because the off period is short. If the gate voltage is detected, the comparator 15 outputs an abnormal signal. is there. Here, the detection of the gate voltage is canceled by the high pulse signal from the cancel circuit 7, that is, the abnormality detection is canceled, so that it is possible to avoid erroneously detecting the abnormality.

Next, an operation when a short circuit abnormality occurs in the IGBT 1 will be described with reference to FIG. If a control signal (ON / OFF command) shown in FIG. 9A is output from the control circuit 2 and a short circuit abnormality occurs when the IGBT 1 is turned ON, the gate voltage is as shown in FIG. 9B.
In this case, the OFF period is sufficiently long as in the case shown in FIG. 7, and the gate voltage immediately after the ON command from the control circuit 2 is at the same level as in the normal state. For this reason, the operations and waveforms of the respective parts shown in FIGS. 9A to 9G are the same as those shown in FIGS. 7A to 7G. That is, the cancel circuit 6 does not generate a cancel signal, and the abnormality detection circuit 7 has a gate voltage (first gate voltage signal 15a) divided by the resistors 17 and 18 only during the period of the pulse 8a from the sampling circuit 8. Is input to the comparator 15 and compared with the first threshold voltage 15b. In this case, because of the short circuit abnormality, the first gate voltage signal 15a is higher than the first threshold voltage 15b, and the comparator 15 generates the abnormality signal 15c (FIG. 9 (h), FIG. 9 (i)).

  As described above, in this embodiment, within the IGBT 1 turn-on transition period, the gate voltage is detected only during the pulse 8a generation period from the sampling circuit 8, and the abnormality detection circuit 7 detects an abnormality when the threshold is exceeded. And a cancel circuit 6 for generating a cancel signal when the gate voltage immediately after the ON command from the circuit 2 exceeds a predetermined value (second threshold value). When the cancel signal is generated, the gate voltage is set in the pulse 8a generation period. The detection of abnormality by the abnormality detection circuit 7 is stopped without detection. For this reason, when the IGBT 1 is turned on in a short off period and the gate voltage is not fully reduced, the abnormality detection by the abnormality detection circuit 7 is stopped, so that erroneous detection of the abnormality can be avoided, and the reliability of the drive circuit 500 is improved. improves. Further, since the IGBT 1 is not shut off due to erroneous abnormality detection, the operation of the circuit using the IGBT 1 is stabilized.

  The semiconductor switching element is not limited to the IGBT, and may be a voltage-driven semiconductor element such as a MOSFET, for example, as long as it is a semiconductor switching element that requires detection when a short circuit is abnormal.

Embodiment 2. FIG.
Next, a driving circuit for a semiconductor switching element according to Embodiment 2 of the present invention will be described. FIG. 10 shows a configuration of drive circuit 500a of IGBT 1 according to the second embodiment of the present invention.
10, the same reference numerals as those in FIG. 6 of the first embodiment described above denote the same or corresponding parts, and thus the description thereof is omitted. In this case, the abnormality detection circuit 7a inputs the voltage across the gate resistor 4 to the differential amplifier circuit 30, detects the gate current, inputs it to the negative terminal of the comparator 15, and compares this gate current with a threshold value. Detects short circuit abnormality.
FIGS. 11 to 13 are time charts showing waveform diagrams of respective parts for explaining the operation of the drive circuit 500a. 11 shows a case where the off period of the IGBT 1 is long, and FIG. 12 shows a case where the off period of the IGBT 1 is short. FIG. 13 shows a case where a short circuit abnormality has occurred in the IGBT 1.

First, the operation when the OFF period from the OFF command to the ON command is sufficiently long and the gate voltage of the IGBT 1 is sufficiently lowered and there is no abnormality in the IGBT 1 will be described with reference to FIG. When the control signal (ON / OFF command) shown in FIG. 11A is output from the control circuit 2, the gate current of the IGBT 1 becomes as shown in FIG. 11B.
When an ON command is input from the control circuit 2, the sampling circuit 8 outputs a pulse 8a during a preset period within the turn-on transient period (FIG. 11C).
The pulse generation circuit 27 generates a short on-pulse simultaneously with the on-command from the control circuit 2 (FIG. 11 (d)), and the second gate voltage signal 23a is applied to the + terminal of the comparator 23 only during the on-pulse period. Entered. The comparator 23 outputs a High signal to the pulse waveform output circuit 22 when the second gate voltage signal 23a is higher than a predetermined second threshold voltage 23b, and the pulse waveform output circuit 22 receives the High signal. Sometimes a high pulse signal of a certain length is output as a cancel signal. In this case, as shown in FIG. 11E, the second gate voltage signal 23a is equal to or lower than the second threshold voltage 23b, the output of the comparator 23 remains Low, and no cancel signal is generated. For convenience, the output of the pulse waveform output circuit 22 and the output of the comparator 23 are not shown.

  In the abnormality detection circuit 7a, the output of the NOT circuit 21 that receives the cancel signal from the cancel circuit 7 is High as shown in FIG. 11 (f), and this High signal and the pulse 8a from the sampling circuit 8 are input. The output of the NAND circuit 20 becomes Low only during the period of the pulse 8a from the sampling circuit 8 (FIG. 11 (g)). The switch 19 is controlled by the output of the NAND circuit 20, and the input of the + terminal of the comparator 15 becomes 0 when the output of the NAND circuit 20 is High, and the threshold signal 15e which is a control voltage divided by the resistors 28 and 29 when Low. It becomes. Further, the gate current signal 15 d from the differential amplifier circuit 30 is input to the negative terminal of the comparator 15 as described above. That is, only during the period of the pulse 8a from the sampling circuit 8, the threshold signal 15e is input to the + terminal of the comparator 15, and the comparator 15 outputs an abnormal signal when the gate current signal 15d is lower than the threshold signal 15e. In this case, the gate current signal 15d is equal to or greater than the threshold signal 15e, and the output of the comparator 15 remains Low (no abnormality) (FIGS. 11 (h) and 11 (i)).

Next, an operation in the case of turning on in a state where the off period from the off command to the on command is short and the gate voltage of the IGBT cannot be lowered will be described with reference to FIG. When the control signal (ON / OFF command) shown in FIG. 12A is output from the control circuit 2, the gate current of the IGBT 1 becomes as shown in FIG. Compared with the case shown in FIG. 11, since the off period is shorter, the gate current rises to 0 A and rises by the on command before returning, so the gate current at turn-on becomes lower.
When an ON command is input from the control circuit 2, the sampling circuit 8 outputs a pulse 8a in a preset period within the turn-on transient period (FIG. 12C).

  The pulse generation circuit 27 generates a short on-pulse simultaneously with the on-command from the control circuit 2 (FIG. 12 (d)), and the second gate voltage signal 23a is applied to the + terminal of the comparator 23 only during the on-pulse period. Entered. The comparator 23 outputs a High signal to the pulse waveform output circuit 22 when the second gate voltage signal 23a is higher than a predetermined second threshold voltage 23b. In this case, similarly to the case shown in FIG. 7, since the off period is short, the gate voltage at the time of turn-on becomes high. For this reason, as shown in FIG. 12 (e), the second gate voltage signal 23a exceeds the second threshold voltage 23b, and the output of the comparator 23 becomes a High signal. A high pulse signal having a certain length is output as a cancel signal. This High pulse signal is output in a period including the pulse 8a generation period of the sampling circuit 8, and the output of the NOT circuit 21 to which the High pulse signal is input is generated as shown in FIG. 12 (f). The period including the period is Low, and the output of the NAND circuit 20 that receives the Low signal and the pulse 8a from the sampling circuit 8 is High (FIG. 12 (g)).

  The switch 19 is controlled by the output of the NAND circuit 20, and the input of the + terminal of the comparator 15 becomes zero. The gate current signal 15d from the differential amplifier circuit 30 is input to the negative terminal of the comparator 15, the gate current signal 15d is 0 or more, and the output of the comparator 15 remains Low (no abnormality) (FIG. 12 (h), FIG. 12 (i)).

  Also in this embodiment, the same cancel circuit 6 as in the first embodiment is provided, and the second gate voltage signal 23a immediately after the ON command from the control circuit 2 is detected and input to the comparator 23, and the second When the gate voltage signal 23a is higher than the predetermined second threshold voltage 23b, the pulse waveform output circuit 22 outputs a high pulse signal having a certain length as a cancel signal. The abnormality detection circuit 7a detects the gate current signal 15d by the comparator 15 and performs abnormality detection in comparison with the threshold signal 15e only during the period of the pulse 8a from the sampling circuit 8. The threshold signal 15e is Canceled by a high pulse signal from the cancel circuit 7. In the case of FIG. 12, the IGBT 1 does not cause a short-circuit abnormality, but since the off period is short, the gate current is transiently lower than normal and lower than the threshold signal 15e. Here, the threshold signal 15e is canceled by the high pulse signal from the cancel circuit 7, that is, the abnormality detection is canceled, so that erroneous detection of the abnormality can be avoided.

Next, an operation when a short circuit abnormality occurs in the IGBT 1 will be described with reference to FIG. If a control signal (ON / OFF command) shown in FIG. 13A is output from the control circuit 2 and a short circuit abnormality occurs when the IGBT 1 is turned ON, the gate current is as shown in FIG. 13B. When a short circuit abnormality occurs, the gate current at turn-on becomes transiently small as shown in the figure. In this case, the off period is sufficiently long as in the case shown in FIG. 11, and the gate voltage immediately after the on command from the control circuit 2 is at the same level as in the normal state.
For this reason, the operations and waveforms of the respective parts shown in FIGS. 13A to 13G are the same as those shown in FIGS. 11A to 11G. That is, the cancel circuit 6 does not generate a cancel signal, and the abnormality detection circuit 7a detects the gate current signal 15d by the comparator 15 and detects an abnormality by comparing with the threshold signal 15e only during the period of the pulse 8a from the sampling circuit 8. I do. In this case, because of the short circuit abnormality, the gate current signal 15d is lower than the threshold signal 15e, and the comparator 15 generates the abnormality signal 15f (FIGS. 13 (h) and 13 (i)).

  As described above, in this embodiment, the abnormality detection circuit 7a that detects abnormality by comparing the gate current with the threshold only during the pulse 8a generation period from the sampling circuit 8 within the turn-on transient period of the IGBT 1, and the control circuit 2 And a cancel circuit 6 for generating a cancel signal when the gate voltage immediately after the ON command exceeds a predetermined value (second threshold), and when the cancel signal is generated, the threshold of the gate current is set in the generation period of the pulse 8a. The abnormality detection by the abnormality detection circuit 7a is stopped without being generated. For this reason, when the IGBT 1 is turned on in a state where the off period is short and the gate voltage cannot be lowered, the abnormality detection by the abnormality detection circuit 7a is stopped, and it is possible to avoid erroneous abnormality detection, and the reliability of the drive circuit 500a is improved. improves. Further, since the IGBT 1 is not shut off due to erroneous abnormality detection, the operation of the circuit using the IGBT 1 is stabilized.

Embodiment 3 FIG.
Next, a driving circuit for a semiconductor switching element according to Embodiment 3 of the present invention will be described. FIG. 14 shows a configuration of drive circuit 500c of IGBT 1 according to the third embodiment of the present invention.
In FIG. 14, the same reference numerals as those in FIG. 6 of the first embodiment described above denote the same or corresponding parts, and thus description thereof is omitted. In this case, instead of the cancel circuit 6, a timer circuit 31 is provided as an abnormality detection canceling means for outputting a cancel signal that causes the abnormality detection circuit 7 to stop detecting abnormality. The timer circuit 31 outputs a pulse signal serving as a cancel command for a predetermined period from the time when the off command from the control circuit 2 is generated.

FIG. 15 is a time chart showing the waveform of each part for explaining the operation of the drive circuit 500c when the off period of the IGBT 1 is short.
When the control signal (ON / OFF command) shown in FIG. 15A is output from the control circuit 2, the gate voltage of the IGBT 1 becomes as shown in FIG. Since the off period is short, the gate voltage rises again before decreasing to 0 V, so the gate voltage at turn-on is high.
When an ON command is input from the control circuit 2, the sampling circuit 8 outputs a pulse 8a during a preset period within the turn-on transient period (FIG. 15C).
The timer circuit 31 outputs a cancel command pulse 31a with a constant pulse width using a falling edge of the control signal, that is, an OFF command as a trigger. As shown in FIG. 16, the pulse width of the cancel command pulse 31a is such that when the gate voltage starts to decrease immediately after the IGBT 1 operates to decrease immediately after the gate voltage decreases to 0V, It is set to a predetermined period during the transition period.

  In this case, the cancel command pulse 31a is output in a period including the generation period of the pulse 8a of the sampling circuit 8, and the output of the NOT circuit 21 having the pulse 31a as an input is a pulse as shown in FIG. The period including the 8a generation period is Low, and the output of the NAND circuit 20 that receives the Low signal and the pulse 8a from the sampling circuit 8 is High (FIG. 15 (f)). Since the switch 19 is controlled by the output of the NAND circuit 20 and the input of the + terminal of the comparator 15 becomes 0, the input of the + terminal is equal to or lower than the first threshold voltage 15b, and the output of the comparator 15 is Low (no abnormality). (FIG. 15 (g), FIG. 15 (h)).

In this way, the timer circuit 31 outputs the cancel command pulse 31a as a cancel signal with a constant pulse width, using the OFF command from the control circuit 2 as a trigger. The cancel command pulse 31a overlaps the pulse 8a generation period of the sampling circuit 8 according to the length of the off period. When the off period is long and the gate voltage decreases to 0V and then rises, the pulse 8a of the sampling circuit 8 is generated after the end of the cancel instruction pulse 31a. When the off period is short as shown in FIG. 15, the cancel instruction The pulse 31a is output in a period including the generation period of the pulse 8a.
As described above, the abnormality detection circuit 7 detects the gate voltage (first gate voltage signal 15a) only during the period of the pulse 8a from the sampling circuit 8, but when the pulse 8a overlaps with the cancel command pulse 31a. In the overlap period, the detection of the gate voltage is cancelled. In this case, since the off period is short, the gate voltage becomes transiently higher than normal. However, since the detection of the gate voltage is canceled and the abnormality detection is cancelled, erroneous detection of the abnormality can be avoided.

  Although the time chart when the off period is long is omitted for the sake of convenience, the pulse 8a of the sampling circuit 8 is generated after the end of the cancel command pulse 31a, and the operation of the abnormality detection circuit 7 when the IGBT 1 is normal and when the short circuit is abnormal is as follows. This is the same as that shown in FIGS.

  In the third embodiment, the cancel command pulse 31a serving as the cancel command is generated using the timer circuit 31, but a similar cancel command 32a is generated by the CPU 32 of the microcomputer as in the drive circuit 500c shown in FIG. Then, it may be input to the NOT circuit 21 of the abnormality detection circuit 7.

Embodiment 4 FIG.
Next, a driving circuit for a semiconductor switching element according to Embodiment 4 of the present invention will be described. FIG. 18 shows a configuration of drive circuit 500d of IGBT 1 according to the fourth embodiment of the present invention. In this embodiment, the timer circuit 31 in the third embodiment is applied to the second embodiment. That is, the timer circuit 31 outputs the cancel command pulse 31a as a cancel signal with a constant pulse width, using the OFF command from the control circuit 2 as a trigger. Further, the abnormality detection circuit 7a inputs the voltage across the gate resistor 4 to the differential amplifier circuit 30, detects the gate current, inputs it to the negative terminal of the comparator 15, and compares this gate current with a threshold value to detect a short circuit abnormality. Detection is performed.

FIG. 19 is a time chart showing the waveform of each part for explaining the operation of the drive circuit 500d when the off-period of the IGBT 1 is short.
Although the time chart when the off period is long is omitted for the sake of convenience, the pulse 8a of the sampling circuit 8 is generated after the end of the cancel command pulse 31a, and the operation of the abnormality detection circuit 7a when the IGBT 1 is normal and when the short circuit is abnormal is as follows. This is the same as that shown in FIGS.
When the control signal (ON / OFF command) shown in FIG. 19A is output from the control circuit 2, the gate current of the IGBT 1 becomes as shown in FIG. 19B. Since the off period is short, the gate current rises to 0 A and rises by an on command before returning, so the gate current at turn-on becomes low.
When an ON command is input from the control circuit 2, the sampling circuit 8 outputs a pulse 8a during a preset period within the turn-on transient period (FIG. 19C).
The timer circuit 31 outputs a cancel command pulse 31a with a constant pulse width using a falling edge of the control signal, that is, an OFF command as a trigger.

In this case, the cancel command pulse 31a is output in a period including the generation period of the pulse 8a of the sampling circuit 8, and the output of the NOT circuit 21 having the pulse 31a as an input is a pulse as shown in FIG. The period including the 8a generation period is Low, and the output of the NAND circuit 20 that receives the Low signal and the pulse 8a from the sampling circuit 8 is High (FIG. 19F).
The switch 19 is controlled by the output of the NAND circuit 20, and the input of the + terminal of the comparator 15 becomes zero. The gate current signal 15d from the differential amplifier circuit 30 is input to the negative terminal of the comparator 15, the gate current signal 15d is 0 or more, and the output of the comparator 15 remains Low (no abnormality) (FIG. 19 (g), FIG. 19 (h)).

  Also in this embodiment, the cancel command pulse 31a output from the timer circuit 31 overlaps with the pulse 8a generation period of the sampling circuit 8 according to the length of the off period, and when the off period is short as shown in FIG. The cancel command pulse 31a is output in a period including the generation period of the pulse 8a. The abnormality detection circuit 7a detects the gate current signal 15d by the comparator 15 and performs abnormality detection in comparison with the threshold signal 15e only during the period of the pulse 8a from the sampling circuit 8, but the pulse 8a is a cancel command pulse. When it overlaps with 31a, the threshold signal 15e is canceled in the overlap period. In this case, since the off period is short, the gate current is transiently lower than that in the normal state. However, since the abnormality detection is canceled by canceling the threshold signal 15e, erroneous detection of the abnormality can be avoided.

  In this case as well, like the drive circuit 500e shown in FIG. 20, the CPU 32 of the microcomputer may create a cancel command 32a similar to the cancel command pulse 31a and input it to the NOT circuit 21 of the abnormality detection circuit 7a. .

Embodiment 5 FIG.
Next, a driving circuit for a semiconductor switching element according to a fifth embodiment of the present invention will be described. FIG. 21 shows a configuration of drive circuit 500f of IGBT 1 according to the fifth embodiment of the present invention.
In FIG. 21, the same reference numerals as those in FIG. 10 of the second embodiment described above denote the same or corresponding parts. In this case, the abnormality detection circuit 7b detects the gate current by inputting the voltage across the gate resistor 4 to the differential amplifier circuit 30 and inputs it to the negative terminal of the comparator 15, as in the second embodiment. A short circuit abnormality is detected by comparing the gate current with a threshold value. Here, the gate current signal 15d input to the negative terminal of the comparator 15 is also input to the positive terminal of the comparator 23 of the cancel circuit 6, and it is determined whether cancellation is necessary for abnormality detection.

FIG. 22 is a time chart showing the waveform of each part for explaining the operation of the drive circuit 500f.
When the ON command is output from the control circuit 2, the gate current of the IGBT 1 becomes as shown in FIG. (i) is a case where the off period from the off command to the on command is long and there is no abnormality in the IGBT 1, (ii) is a case where the off period is short, (iii) is a long off period and a short circuit is abnormal in the IGBT 1 (arm short circuit) ) Occurs.
The pulse generation circuit 27 generates a short ON pulse simultaneously with the ON command from the control circuit 2 (FIG. 22B), and the gate current signal 15d is input to the + terminal of the comparator 23 only during the ON pulse period. The comparator 23 outputs a High signal to the pulse waveform output circuit 22 when the gate current signal 15d is higher than a predetermined threshold, and the pulse waveform output circuit 22 has a certain length of High when the High signal is input. Outputs a pulse signal.

When the off periods of (i) and (iii) are long, the pulse waveform output circuit 22 outputs a high pulse signal (FIG. 22 (c)).
When an ON command is input from the control circuit 2, the sampling circuit 8 outputs a pulse 8a during a preset period within the turn-on transition period (FIG. 22D).
In the abnormality detection circuit 7b, the output of the NAND circuit 600 that receives the high pulse signal from the pulse waveform output circuit 22 in the cancel circuit 6 and the pulse 8a from the sampling circuit 8 is the period of the pulse 8a from the sampling circuit 8. Only becomes Low (FIG. 22E). The switch 19 is controlled by the output of the NAND circuit 600, and the input of the + terminal of the comparator 15 becomes 0 when the output of the NAND circuit 600 is High, and the threshold signal 15e that is a control voltage divided by the resistors 28 and 29 when Low. It becomes. Further, the gate current signal 15 d from the differential amplifier circuit 30 is input to the negative terminal of the comparator 15 as described above. That is, only during the period of the pulse 8a from the sampling circuit 8, the threshold signal 15e is input to the + terminal of the comparator 15, and the comparator 15 outputs an abnormal signal when the gate current signal 15d is lower than the threshold signal 15e.

Here, the High pulse signal output from the cancel circuit 6 is used as an inversion cancel signal, and the threshold signal 15e is not generated if the High pulse signal is not generated and remains Low.
As described above, in this embodiment, the abnormality detection circuit 7b that detects the abnormality by comparing the gate current with the threshold only during the pulse 8a generation period from the sampling circuit 8 within the turn-on transient period of the IGBT 1, and the control circuit 2 And a cancel circuit 7 for generating an inversion cancel signal when the gate current immediately after the ON command from the counter exceeds the threshold value, and when the inversion cancel signal is not generated and remains low, the threshold value of the gate current is set during the pulse 8a generation period. The abnormality detection by the abnormality detection circuit 7b is stopped without being generated. For this reason, when the IGBT 1 is turned on in a short off period and the gate voltage does not fall down, the abnormality detection by the abnormality detection circuit 7b is stopped, so that erroneous detection of the abnormality can be avoided, and the reliability of the drive circuit 500f is improved. improves. Further, since the IGBT 1 is not shut off due to erroneous abnormality detection, the operation of the circuit using the IGBT 1 is stabilized.

It is a figure which shows the structure of the drive circuit of IGBT by Embodiment 1 of this invention. It is a figure which shows the structure of the half-bridge circuit to which IGBT by Embodiment 1 of this invention is applied. It is a figure which shows the gate voltage waveform at the time of switching of IGBT by Embodiment 1 of this invention. It is a partial detail drawing of the drive circuit of IGBT by Embodiment 1 of this invention. FIG. 5 is a partial detailed view of another example of the IGBT drive circuit according to the first embodiment of the present invention. It is a figure which shows the detailed structure of the drive circuit of IGBT by Embodiment 1 of this invention. It is a wave form diagram explaining operation | movement of the drive circuit of IGBT by Embodiment 1 of this invention. It is a wave form diagram explaining operation | movement of the drive circuit of IGBT by Embodiment 1 of this invention. It is a wave form diagram explaining operation | movement of the drive circuit of IGBT by Embodiment 1 of this invention. It is a figure which shows the detailed structure of the drive circuit of IGBT by Embodiment 2 of this invention. It is a wave form diagram explaining operation | movement of the drive circuit of IGBT by Embodiment 2 of this invention. It is a wave form diagram explaining operation | movement of the drive circuit of IGBT by Embodiment 2 of this invention. It is a wave form diagram explaining operation | movement of the drive circuit of IGBT by Embodiment 2 of this invention. It is a figure which shows the detailed structure of the drive circuit of IGBT by Embodiment 3 of this invention. It is a wave form diagram explaining operation | movement of the drive circuit of IGBT by Embodiment 3 of this invention. It is a figure which shows the output pulse width of the timer circuit by Embodiment 3 of this invention. It is a figure which shows the detailed structure of the drive circuit of IGBT by another example of Embodiment 3 of this invention. It is a figure which shows the detailed structure of the drive circuit of IGBT by Embodiment 4 of this invention. It is a wave form diagram explaining operation | movement of the drive circuit of IGBT by Embodiment 4 of this invention. It is a figure which shows the detailed structure of the drive circuit of IGBT by another example of Embodiment 4 of this invention. It is a figure which shows the detailed structure of the drive circuit of IGBT by Embodiment 5 of this invention. It is a wave form diagram explaining operation | movement of the drive circuit of IGBT by Embodiment 5 of this invention.

Explanation of symbols

1, 1a, 1b IGBT, 2 control circuit, 6 cancel circuit,
7, 7a, 7b Abnormality detection circuit, 8 sampling circuit,
15a first gate voltage signal, 15b first threshold, 15c, 15f abnormal signal,
15d gate current signal, 15e threshold signal, 23a second gate voltage signal,
23b 2nd threshold value, 31 Timer circuit as anomaly detection cancellation means,
31a cancel command pulse, 32 CPU, 32a cancel command,
500, 500a to 500f Drive circuit.

Claims (7)

In a drive circuit of a semiconductor switching element that includes a control circuit that generates an on / off command based on a command from the outside and whose on / off operation is controlled by a control electrode,
An abnormality detecting means for detecting an abnormality when a control amount of the control electrode is out of a threshold range during a preset period within a turn-on transition period of the control electrode after an on command is generated from the control circuit; A drive circuit for a semiconductor switching element, comprising: abnormality detection canceling means for stopping abnormality detection by the abnormality detection means when the control amount of the control electrode immediately after the ON command from the control circuit is out of a predetermined range . The abnormality detection canceling means detects a control voltage as a control amount of the control electrode immediately after the ON command is generated from the control circuit, and when the control voltage is outside the predetermined range higher than a predetermined value, 2. The drive circuit for a semiconductor switching element according to claim 1, wherein abnormality detection by the detection means is stopped. The abnormality detection canceling means detects a current flowing through the control electrode as a control amount of the control electrode immediately after the ON command is generated from the control circuit, and when the current is outside the predetermined range lower than a predetermined value, 2. The semiconductor switching element drive circuit according to claim 1, wherein abnormality detection by the abnormality detection means is stopped. In a drive circuit of a semiconductor switching element that includes a control circuit that generates an on / off command based on a command from the outside and whose on / off operation is controlled by a control electrode,
An abnormality detecting means for detecting an abnormality when a control amount of the control electrode is out of a threshold range during a preset period within a turn-on transition period of the control electrode after an on command is generated from the control circuit; A drive circuit for a semiconductor switching element, comprising: abnormality detection canceling means for stopping abnormality detection by the abnormality detection means according to the length of an off period before an on command is generated from the control circuit. The abnormality detection canceling means generates a cancellation command for a predetermined fixed period from the time when the off command is generated from the control circuit, and the generation period of the cancellation command is determined according to the length of the off period. 5. The drive circuit for a semiconductor switching element according to claim 4, wherein an abnormality detection by the abnormality detection means is stopped during the overlapped period for detecting an abnormality. 6. The semiconductor switching element according to claim 1, wherein the abnormality detecting means detects a control voltage as a control amount of the control electrode, and detects an abnormality when the control voltage exceeds a threshold value. Drive circuit. 6. The abnormality detection unit according to claim 1, wherein the abnormality detection unit detects an abnormality when a current flowing through the control electrode is detected as a control amount of the control electrode, and the current is less than a threshold value. The semiconductor switching element drive circuit.

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