JP6094410B2 - Switching element drive circuit - Google Patents

Description

  The present invention relates to a switching element drive circuit including charging means for charging an opening / closing control terminal of the switching element to switch the switching element to an on state.

  As this type of drive circuit, for example, as shown in Patent Document 1 below, a drive circuit including an overcurrent protection circuit that protects a switching element when an overcurrent flows through the switching element (IGBT) is known. Specifically, the switching element includes a sense terminal that outputs a minute current having a correlation with a collector current flowing through the switching element. Then, the protection circuit determines that an overcurrent flows through the switching element based on the minute current output from the sense terminal exceeding the threshold current, and forcibly switches the switching element to the OFF state.

Japanese Patent No. 2999887

  Here, the present inventors consider adopting a new method different from the method described in Patent Document 1 as a method for detecting that an overcurrent flows through the switching element.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a new switching element drive circuit capable of detecting that an overcurrent flows through the switching element.

  In order to solve the above-described problems, the present invention provides a charging means (24, 26) for charging an opening / closing control terminal of the switching element to switch the switching element (S ¥ #) to an ON state, and a first timing. Overcurrent determination means for determining that an overcurrent is flowing between a pair of main terminals of the switching element when the voltage of the switching control terminal exceeds a determination voltage within an overcurrent detection period from to the second timing. The determination voltage is higher than a mirror voltage of the switching element, and is set to a voltage equal to or lower than an upper limit voltage of the switching control terminal, and the first timing is the pair of main terminals. When the overcurrent is assumed to flow in between, the voltage at the switching control terminal is set to a timing before the timing when the voltage reaches the determination voltage, and the second timing is A period from a timing after the first timing to a timing before the timing at which the voltage of the switching control terminal reaches the determination voltage when it is assumed that no overcurrent flows between the pair of main terminals It is characterized by being set in.

  When an overcurrent flows between a pair of main terminals of the switching element, the mirror period of the switching element is lost or the mirror period is shortened. In view of this point, in the above invention, the overcurrent determination unit is provided, and the determination voltage and the first timing and the second timing for determining the overcurrent detection period are set as described above.

  Here, the reason why the determination voltage is higher than the mirror voltage is to avoid a situation in which it is erroneously determined that an overcurrent flows even though no overcurrent flows. In addition, the latest timing among the possible timings of the second timing is set as the timing before the arrival timing, as in the case of the determination voltage setting, although the overcurrent does not flow. This is to avoid a situation in which it is erroneously determined that a current is flowing. Further, the reason why the latest timing in the range that can be taken by the first timing is set as the timing before the arrival timing is to detect early that an overcurrent flows.

  According to the above setting, when no overcurrent flows, the voltage at the switching control terminal does not exceed the determination voltage within the overcurrent detection period. On the other hand, when an overcurrent flows, the voltage of the switching control terminal exceeds the determination voltage within the overcurrent detection period. Thus, according to the said invention, it can detect appropriately that overcurrent is flowing using the voltage of a switching control terminal.

The lineblock diagram of the motor control system concerning a 1st embodiment. The block diagram of the drive circuit concerning the embodiment. 6 is a flowchart showing a procedure of overcurrent protection processing according to the embodiment. The time chart which shows an example of the overcurrent protection process concerning the embodiment. The time chart which shows an example of the overcurrent protection process concerning the embodiment. The block diagram of the drive circuit concerning 2nd Embodiment. 6 is a flowchart showing a procedure of overcurrent protection processing according to the embodiment. The figure which shows the magnetic coupling aspect at the time of the overcurrent rise concerning 3rd Embodiment. The figure which shows the magnetic coupling aspect at the time of the overcurrent reduction concerning the embodiment. The time chart which shows an example of the overcurrent protection process concerning the embodiment.

(First embodiment)
Hereinafter, a first embodiment in which a driving circuit for a switching element according to the present invention is applied to a vehicle (for example, a hybrid vehicle or an electric vehicle) including a rotating machine as an in-vehicle main unit will be described with reference to the drawings.

  As shown in FIG. 1, the motor generator 10 is a multi-phase rotating machine (three-phase rotating machine) as an in-vehicle main machine, and is connected to driving wheels (not shown). The motor generator 10 is connected to a high voltage battery 12 as a “DC power supply” via an inverter 11. The output voltage of the high voltage battery 12 is, for example, 100 V or more. As the high voltage battery 12, for example, a lithium ion storage battery or a nickel hydride storage battery can be used. In the present embodiment, a synchronous machine (permanent magnet synchronous machine) is used as the motor generator 10.

  The inverter 11 includes a series connection body of a switching element S ¥ p (¥ = U, V, W) on the high potential side (upper arm side) and a switching element S ¥ n on the low potential side (lower arm side). . Specifically, the inverter 11 includes a series connection body of three sets of switching elements S ¥ p, S ¥ n, and the connection point of the switching elements S ¥ p, S ¥ n is connected to the ¥ phase of the motor generator 10. Yes.

  Incidentally, in the present embodiment, a voltage-controlled semiconductor switching element is used as the switching element S ¥ # (# = p, n), and more specifically, an IGBT is used. In the present embodiment, the output terminal (emitter) and the input terminal (collector) of the switching element S ¥ # correspond to “a pair of main terminals”. Here, when the collector is the “first main terminal” and the emitter is the “second main terminal”, the voltage (gate) of the switching control terminal (gate) of the switching element S ¥ # with respect to the voltage of the second main terminal By setting the voltage to be equal to or higher than the threshold voltage Vth, the switching element S ¥ # can be switched to the on state. Here, the threshold voltage Vth is a voltage at which the switching element S ¥ # switches from the off state to the on state. A free wheel diode D ¥ # is connected in antiparallel to the switching element S ¥ #.

  The control device 14 is composed mainly of a microcomputer using the low voltage battery 16 as a power source. The control device 14 operates the inverter 11 to control the control amount (for example, torque) of the motor generator 10 to the command value. Specifically, the control device 14 generates an operation signal g ¥ # and outputs it to the drive circuit DU corresponding to the switching element S ¥ # in order to operate the switching element S ¥ # constituting the inverter 11. Here, the high-potential side operation signal g ¥ p and the corresponding low-potential side operation signal g ¥ n are complementary to each other. That is, the switching element S ¥ p on the high potential side and the corresponding switching element S ¥ n on the low potential side are alternately turned on.

  The interface 18 has a function of transmitting signals between these high-voltage systems and low-voltage systems while electrically insulating them. Here, the high voltage system is a system including the high voltage battery 12, the inverter 11, and the motor generator 10. The low voltage system is a system including the low voltage battery 16 and the control device 14. In the present embodiment, the interface 18 includes an optical insulating element (photocoupler).

  Next, the configuration of the drive circuit DU will be described with reference to FIG.

  As shown in the figure, the drive circuit DU includes a drive IC 20 that is a one-chip semiconductor integrated circuit, a constant voltage power supply 22 having a predetermined output voltage Vom (for example, 15 V), and the constant voltage power supply 22 as a power supply source. The constant current power supply 24 is provided. Specifically, the constant current power supply 24 is connected to the drain of a P-channel MOSFET (hereinafter, charging switching element 26) via a first terminal T1 of the drive IC 20. The source of the charging switching element 26 is connected to the gate of the switching element S ¥ # via the second terminal T2 of the drive IC 20. Here, in the present embodiment, an electric path from the constant current power supply 24 to the gate through the first terminal T1, the charging switching element 26, and the second terminal T2 is referred to as a “charging path Lcha”. And In the present embodiment, the constant current power supply 24 and the charging switching element 26 constitute “charging means”.

  The gate of the switching element S ¥ # is connected to the third terminal T3 of the drive IC 20 via the discharging resistor 28. The third terminal T3 is connected to the emitter of the switching element S ¥ # via an N-channel MOSFET (hereinafter, discharge switching element 30).

  The gate of the switching element S ¥ # is also connected to the emitter via a second terminal T2 and an N-channel MOSFET (hereinafter, clamping switching element 32). The connection point between the second terminal T2 and the clamp switching element 32 is connected to the non-inverting input terminal of the operational amplifier 34, and the inverting input terminal of the operational amplifier 34 is connected to the power source 36.

  Here, the output voltage of the power source 36 (hereinafter referred to as the clamp voltage Vclamp) is switched to a voltage (for example, 12V) that does not flow a current that causes the reliability of the switching element S ¥ # to decrease excessively in a short time. It is set to a value that limits the gate voltage of the element S ¥ #. In the present embodiment, the clamp voltage Vclamp is specifically set to a voltage equal to or higher than the threshold voltage Vth and lower than the output voltage Vom of the constant voltage power supply 22.

  The gate of the switching element S ¥ # is further connected to the emitter via the soft cutoff resistor 38, the fourth terminal T4 of the drive IC 20, and an N-channel MOSFET (hereinafter, soft cutoff switching element 40). In the present embodiment, the soft cutoff resistor 38 and the soft cutoff switching element 40 constitute “soft cutoff means”.

  The switching element S ¥ # includes a sense terminal St that outputs a minute current (for example, “1/10000” of the collector current Ic) having a correlation with a current flowing between the collector and the emitter (hereinafter, collector current Ic). . The sense terminal St is connected to the emitter via a resistor (sense resistor 42). As a result, a voltage drop occurs in the sense resistor 42 due to a small current output from the sense terminal St. Therefore, the potential on the sense terminal St side of the sense resistor 42 (hereinafter, the sense voltage Vse) has a correlation with the collector current Ic. It can be an electrical state quantity. In the present embodiment, the emitter potential is defined as “0”, and the sense voltage Vse when the potential on the sense terminal St side of both ends of the sense resistor 42 is higher than the emitter potential is defined as positive. In the present embodiment, the sense terminal St and the sense resistor 42 constitute “current detection means”.

  The sense voltage Vse is input to the drive control unit 44 included in the drive IC 20 via the fifth terminal T5 of the drive IC 20. Based on the operation signal g ¥ # input via the sixth terminal T6 of the drive IC 20, the drive control unit 44 alternately performs the charging process and the discharging process by operating the charging switching element 26 and the discharging switching element 30. To drive the switching element S ¥ #. Specifically, the charging process is a process of turning off the discharging switching element 30 and turning on the charging switching element 26 when it is determined that the operation signal g ¥ # is an on-operation command. That is, the charging process is a constant current control process for supplying a constant current to the gate. Thereby, switching element S ¥ # is switched to the ON state.

  In addition, according to the constant current control process, it is possible to avoid an increase in the mirror period of the switching element S ¥ # due to a decrease in the gate charging current caused by the clamp process described later, thereby avoiding an increase in switching loss and the like. be able to.

  On the other hand, the discharging process is a process of switching the discharging switching element 30 to an on operation and switching the charging switching element 26 to an off operation when it is determined that the operation signal g ¥ # is an off operation command. Thereby, switching element S ¥ # is switched to the off state.

  The drive control unit 44 further performs a clamping process. The clamp process is a process of outputting an enable signal to the operational amplifier 34 over the clamp filter time Tclamp from the timing when the gate voltage Vge reaches the predetermined voltage Vα when the charging process is performed. That is, the clamping process is a process of limiting the gate voltage Vge with the clamp voltage Vclamp before the gate voltage Vge reaches the upper limit voltage (the output voltage Vom of the constant voltage power supply 22). Thus, the on-resistance of the clamp switching element 32 is adjusted by the operation of the gate voltage of the clamp switching element 32, and the voltage at the connection point between the second terminal T2 and the clamp switching element 32 is limited by the clamp voltage Vclamp.

  Here, in the present embodiment, the predetermined voltage Vα is set to a voltage equal to or higher than the threshold voltage Vth and lower than the clamp voltage Vclamp. More specifically, the predetermined voltage Vα is set to a maximum value Vthmax within a range “Vthmin to Vthmax” that the threshold voltage Vth can take. This is a setting for starting the clamping process after the switching element S ¥ # is reliably switched to the on state. That is, the threshold voltage Vth varies depending on the collector current Ic, the individual difference of the switching element S ¥ #, and the like. Therefore, by setting the predetermined voltage Vα to the maximum value assumed as the threshold voltage Vth, the clamping process can be started after the switching element S ¥ # is reliably switched to the on state.

  According to the clamping process, for example, when the upper and lower arms are short-circuited and an overcurrent (short-circuit current) flows through the switching element S ¥ #, switching is performed until the switching element S ¥ # is switched to the OFF state by the soft cutoff processing described later The collector current Ic flowing through the element S ¥ # can be limited.

  Incidentally, the clamp filter time Tclamp is set to a time slightly longer than the maximum value of the time from when the gate voltage Vge reaches the predetermined voltage Vα until the sense voltage Vse exceeds the short-circuit threshold SC (corresponding to “threshold current”). do it. Here, the short-circuit threshold SC is set to the sense voltage Vse corresponding to the upper limit value of the collector current Ic that can maintain the reliability of the switching element S ¥ #.

  Next, the overcurrent protection process according to the present embodiment will be described with reference to FIG. Here, FIG. 3 is a flowchart showing the procedure of the above processing. This process is repeatedly executed by the drive control unit 44 at a predetermined cycle, for example.

  In this series of processing, first, in step S10, it is determined whether or not the current timing is within the overcurrent detection period. Here, the overcurrent detection period is a period determined by the first timing and the second timing. Hereinafter, the first timing, the second timing, and a method for setting the determination voltage Vjde necessary for determining these timings will be described.

  First, the determination voltage Vjde will be described. The determination voltage Vjde is higher than the mirror voltage Vmil of the switching element S ¥ # and is set to a voltage (for example, 14.5 V) that is equal to or lower than the upper limit voltage Vom. Here, the determination voltage Vjde is set to a voltage higher than the mirror voltage because the overcurrent flows in the switching element S ¥ # even though the overcurrent does not flow in the situation where the charging process is performed. This is to avoid a situation in which it is mistakenly determined that there is.

  Here, in the present embodiment, the determination voltage Vjde is set to a voltage equal to or higher than the maximum value Vthmax (> Vmil) of the threshold voltage Vth and lower than the upper limit voltage Vom. More specifically, the determination voltage Vjde is higher than the clamp voltage Vclamp and is set to a voltage lower than the upper limit voltage Vom.

  Subsequently, the first timing will be described. The first timing is the gate voltage Vge when it is assumed that an overcurrent flows to the switching element S ¥ # from the charging processing start timing (charging start timing by the charging means). Is set within a period up to the timing when it reaches the determination voltage Vjde. Here, the reason why the latest timing in the range that can be taken by the first timing is set as the arrival timing is to detect early that an overcurrent flows through the switching element S ¥ #. In other words, if the first timing is set later than the arrival timing, the detection of the overcurrent is delayed by the time from the arrival timing to the first timing. Here, in the present embodiment, the first timing is set to the start timing of the charging process.

  Subsequently, the second timing will be described. In the second timing, when it is assumed that no overcurrent flows to the switching element S ¥ # from the timing after the first timing, the gate voltage Vge is the determination voltage. It is set within a period up to the timing before the timing of reaching Vjde. Here, the latest timing in the range that can be taken by the second timing is the previous timing, even though the overcurrent does not flow through the switching element S ¥ # in the situation where the charging process is performed. This is to avoid a situation in which it is erroneously determined that an overcurrent is flowing. That is, when the second timing is set to a timing after the previous timing, the gate voltage Vge exceeds the determination voltage Vjde within the overcurrent detection period even though no overcurrent flows, and as a result, There is a risk of misjudging that overcurrent is flowing.

  Here, in the present embodiment, the second timing is set to a timing at which the mirror period of the switching element S ¥ # ends when it is assumed that no overcurrent flows through the switching element S ¥ #.

  If an affirmative determination is made in step S10, it is determined in steps S12 and S14 whether an overcurrent is flowing through the switching element S ¥ #. Specifically, in step S12, it is determined whether or not the gate voltage Vge has continued to exceed the determination voltage Vjde for the determination time Tjde.

  If an affirmative determination is made in step S12, the process proceeds to step S14 to determine whether or not the sense voltage Vse exceeds the short-circuit threshold value SC. In the present embodiment, the processing of steps S10 to S14 constitutes “overcurrent determination means”.

  If an affirmative determination is made in step S14, it is determined that an overcurrent is flowing through the switching element S ¥ #, and the process proceeds to step S16. In step S14, a soft cutoff process is performed in which the charging switching element 26 and the discharging switching element 30 are turned off and the soft cutoff switching element 40 is turned on. Thereby, switching element S ¥ # is forcibly switched to the off state.

  Incidentally, the soft blocking resistor 38 is provided to increase the resistance value of the discharge path of the gate charge. This is because, under a situation where the collector current Ic is excessive, if the switching element S ¥ # is switched from the on state to the off state (the discharge rate of the gate charge) is increased, the surge voltage may be excessive. This setting is based on the fact that In the present embodiment, the resistance value Ra of the soft blocking resistor 38 is set to be higher than the resistance value Rb of the discharging resistor 28. That is, the discharge rate when the gate charge is discharged via the soft blocking resistor 38 is lower than the discharge rate when the gate charge is discharged via the discharge resistor 28 by the discharge process.

  In the subsequent step S18, processing for outputting a fail signal FL is performed. Accordingly, the fail signal FL is output to the low voltage system (control device 14) via the seventh terminal T7 of the drive IC 20. The inverter 11 is shut down by the fail signal FL.

  If a negative determination is made in steps S10 to S14, or if the process of step S18 is completed, this series of processes is temporarily terminated.

  4 and 5 show an example of overcurrent protection processing. Specifically, FIG. 4 is an example of an overcurrent protection process at a normal time when no overcurrent flows, and FIG. 5 is an example of an overcurrent protection process when an upper and lower arm short circuit occurs.

  First, it demonstrates using FIG. 4A shows the transition of the gate voltage Vge, FIG. 4B shows the transition of the operating state of the charging switching element 26, and FIG. 4C shows the switching element 32 for clamping. The transition of the operation state is shown. FIG. 4D shows the transition of the operating state of the soft cutoff switching element 40, and FIG. 4E shows the transition of the sense voltage Vse.

  In the illustrated example, at time t1 that is the first timing, the charging process is started, whereby the discharging switching element 30 is switched to the off operation, and the charging switching element 26 is switched to the on operation. . As a result, the gate voltage Vge begins to rise.

  Thereafter, at time t2, when the gate voltage Vge reaches the threshold voltage Vth, the collector current Ic and the sense voltage Vse start to rise.

  Thereafter, the gate voltage Vge reaches the mirror voltage Vmil at time t3, and the mirror period end timing (second timing) is reached at time t4. Here, in a normal time when no overcurrent flows, a mirror period exists, and therefore the gate voltage does not exceed the determination voltage Vjde within the overcurrent detection period.

  Thereafter, at time t5, it is determined that the gate voltage Vge has reached the predetermined voltage Vα. As a result, an enable signal is output to the operational amplifier 34, whereby the clamping process is started. Thereafter, at time t6, the gate voltage Vge becomes the clamp voltage Vclamp.

  Then, at time t7 when the clamp filter time Tclamp elapses from time t5, the clamping process ends, and the clamp switching element 32 is switched to the off operation. Thereby, after that, the gate voltage Vge reaches the output voltage Vom of the constant voltage power supply 22.

  Subsequently, an example of a case where the upper and lower arms are short-circuited will be described with reference to FIG. Here, FIGS. 5A to 5E correspond to FIGS. 4A to 4E.

  In the illustrated example, the gate voltage Vge starts to rise when the charging process is started at time t1. Here, when an overcurrent flows through the switching element S ¥ #, the mirror period is eliminated. Therefore, after time t1, it is determined that the gate voltage Vge has reached the predetermined voltage Vα at time t2 without passing through the mirror period. Thereby, the clamping process is started. In the present embodiment, when it is determined that the sense voltage Vse exceeds the short-circuit threshold SC during the period from when the gate voltage Vge reaches the predetermined voltage Vα until the clamp filter time Tclamp elapses, the time t2 Even when the clamp filter time Tclamp elapses, the clamp process is continued.

  Thereafter, at time t3, it is determined that the gate voltage Vge has exceeded the determination voltage Vjde. Then, at time t4 within the overcurrent detection period (time t1 to t5), the condition that the gate voltage Vge continuously exceeds the determination voltage Vjde from time t3 over the determination time Tjde, and the sense voltage Vse is short-circuited. It is determined that the logical product of the condition that the threshold value SC has been exceeded is true. Accordingly, the switching element S * # is forcibly turned off by switching the soft cutoff switching element 40 to the on operation.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) In the overcurrent detection period, the logical product of the condition that the gate voltage Vge continuously exceeds the determination voltage Vjde and the determination time Tjde and the condition that the sense voltage Vse exceeds the short-circuit threshold SC is true. When it is determined, it is determined that an overcurrent flows through the switching element S ¥ #. Thereby, it can detect appropriately that overcurrent is flowing.

  In particular, in the present embodiment, the use of the sense voltage Vse for overcurrent detection contributes to avoiding erroneous detection of overcurrent caused by noise or the like and improving the overcurrent detection accuracy.

  (2) When it is determined that an overcurrent flows through the switching element S ¥ #, a soft shut-off process is performed. As a result, a surge voltage generated when switching element S ¥ # is switched to the off state can be suppressed, and as a result, it is possible to avoid a decrease in reliability of switching element S ¥ #.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  In the present embodiment, as shown in FIG. 6, the sense terminal, the sense resistor 42, and the fifth terminal T5 are removed. Then, it is detected that an overcurrent flows through the switching element S ¥ # using only the gate voltage Vge. FIG. 6 is a diagram illustrating the drive circuit DU according to the present embodiment. 6, the same members as those shown in FIG. 2 are given the same reference numerals for the sake of convenience.

  FIG. 7 shows a processing procedure according to the present embodiment. This process is repeatedly executed by the drive control unit 44 at a predetermined cycle, for example. In FIG. 7, the same steps as those shown in FIG. 3 are given the same step numbers for the sake of convenience.

  In the present embodiment, the process of step S14 in FIG. 3 is removed. In other words, in the present embodiment, if it is determined that the gate voltage Vge has exceeded the determination voltage Vjde in the overcurrent detection period and continues for the determination time Tjde, it is determined that an overcurrent flows through the switching element S ¥ #. .

  If a negative determination is made in steps S10 and S12 described above, or if the process in step S18 is completed, this series of processes is temporarily terminated.

  According to the present embodiment described above, the following effects can be obtained in addition to the effect (2) of the first embodiment.

  (3) In the overcurrent detection period, it was determined that the overcurrent flows through the switching element S ¥ # only by the fact that the gate voltage Vge continuously exceeded the determination voltage Vjde for the determination time Tjde. Thereby, it can detect appropriately that overcurrent is flowing.

  In particular, in the present embodiment, a configuration in which only the gate voltage Vge is used for overcurrent detection is employed. With such a configuration, in order to detect an overcurrent, means for detecting the collector current Ic, such as the sense terminal St, the sense resistor 42, and the fifth terminal T5, can be made unnecessary. Thereby, the configuration of the drive circuit DU and the like can be simplified, and as a result, the substrate on which the drive circuit DU is mounted can be reduced in size.

(Third embodiment)
Hereinafter, the third embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  In the present embodiment, as the drive circuit DU, in a state where the collector current Ic increases, at least one of the charge path Lcha and the collector and emitter such that the charge moves toward the gate in the charge path Lcha connected to the gate. A main current flow path (flow path of collector current Ic) connected to one side is magnetically coupled.

  First, the mechanism of magnetic coupling will be described with reference to FIGS. Here, FIG. 8 and FIG. 9 are diagrams showing the configuration around the switching element S ¥ n on the low potential side in the drive circuit DU shown in FIG. 8 and 9, illustration of the charging switching element 26, the terminals of the drive IC 20, and the like are omitted.

  As shown in the figure, wiring inductance exists in the main current flow path connected to at least one of the collector and the emitter, and the charging path Lcha connected to the gate. 8 and 9 show that the wiring inductance “lm” exists in the path connected to the collector of the pair of main current flow paths, and shows that the wiring inductance “lg” exists in the charging path Lcha. It was. In this embodiment, these wiring inductances lm and lg are magnetically coupled. Specifically, as shown in FIG. 8, under the situation where the collector current Ic increases (the change rate of the collector current Ic becomes a positive value), the charge moves from the constant current power supply 24 side to the gate in the charging path Lcha. Thus, these wiring inductances lm and lg are magnetically coupled. Here, the movement of charge from the constant current power supply 24 side to the gate is due to the current flowing from the gate side to the emitter side via the gate and emitter capacitance of the switching element S ¥ n.

  As shown in FIG. 9, under the situation where the collector current Ic decreases (the rate of change of the collector current Ic becomes a negative value), the wiring inductance is set so that the gate charge is discharged in the charging path Lcha. lm and lg are magnetically coupled. Here, the gate charge is discharged because current flows from the emitter side to the gate side via the gate-emitter capacitance.

  FIG. 10 shows an example of overcurrent protection processing according to the present embodiment. FIG. 10 corresponds to the previous FIG.

  In the illustrated example, the gate voltage starts to rise due to the charging process at time t1. Here, the rising speed of the gate voltage Vge in the drive circuit DU that is magnetically coupled is higher than the rising speed of the gate voltage Vge in the drive circuit DU that is not magnetically coupled. Therefore, the timing (time t2) at which the gate voltage Vge reaches the determination voltage Vjde in the drive circuit DU that is magnetically coupled is from the timing (time t3) at which the gate voltage Vge reaches the determination voltage Vjde in the drive circuit DU that is not magnetically coupled. Will also be faster. That is, the overcurrent detection timing in the drive circuit DU that is magnetically coupled is earlier than the overcurrent detection timing in the drive circuit DU that is not magnetically coupled.

  As a result, the timing (time t4) at which the soft cutoff process is started in the drive circuit DU that is magnetically coupled is earlier than the timing (time t5) at which the soft cutoff process is started in the drive circuit DU that is not magnetically coupled. Therefore, according to the present embodiment, in addition to the effect obtained in the first embodiment, it is possible to obtain an effect that the switching element S ¥ # can be quickly switched to an off state when an overcurrent flows. it can.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  The first timing that determines the start timing of the overcurrent detection period is not limited to the start timing of the charging process. For example, the first timing may be set to a timing at which the gate voltage Vge reaches the determination voltage Vjde when it is assumed that an overcurrent flows through the switching element S ¥ #. Further, for example, the first timing may be set to a timing slightly before the start timing of the charging process.

  The second timing for determining the end timing of the overcurrent detection period is not limited to the end timing of the mirror period. For example, the second timing may be set within a period from a timing later than the end timing of the mirror period to a timing before the gate voltage Vge reaches the upper limit voltage Vom.

  In the first and second embodiments, the process of step S12 of FIGS. 3 and 7 may be changed to a process of determining whether or not the gate voltage Vge exceeds the determination voltage Vjde. That is, in this case, since the determination time Tjde becomes “0”, for example, in the second embodiment, the soft cutoff process is started at the timing when the gate voltage Vge exceeds the determination voltage Vjde within the overcurrent detection period. It will be.

  The determination voltage Vjde may be set to the upper limit voltage Vom.

  In each of the above embodiments, the situation where the mirror period disappears due to the overcurrent flowing through the switching element S ¥ # is exemplified, but the present invention is not limited thereto. For example, depending on the magnitude of the overcurrent, the mirror period can be shortened even if the mirror period does not disappear. Even in this case, when overcurrent flows, the gate voltage Vge exceeds the determination voltage Vjde within the overcurrent detection period, so that it can be detected that the overcurrent flows.

  The “current detection unit” is not limited to the one having the sense terminal St and the sense resistor 42. For example, as long as the current flowing through the electrical path from the sense terminal St to the emitter can be detected, other current detection means such as one equipped with a Hall element may be used. Further, for example, a voltage detection means (voltage sensor) for detecting the collector-emitter voltage Vce may be provided in the drive circuit DU, and the collector current may be detected based on the detection value of the voltage sensor.

  The “soft blocking means” is not limited to one that decreases the gate charge discharge rate by increasing the resistance value of the gate charge discharge path. For example, it may be described in the following (A) and (B).

  (A) In FIG. 2, the soft blocking resistor 38, the fourth terminal T4, and the soft blocking switching element 40 are removed. Then, a power source (constant current power source) is connected to a connection point between the third terminal T3 and the discharging switching element 30 via a switching element (eg, MOSFET). A configuration in which the discharge rate of the gate charge during the soft shut-off process is made lower than the normal discharge rate at which no overcurrent flows by supplying the charge from the power source to the connection point by turning on the switching element. May be used as a soft shut-off means. This utilizes the fact that the gate charge is prevented from being discharged by supplying a charge from the power source to the connection point.

  (B) In FIG. 2, the soft cutoff resistor 38, the fourth terminal T4, and the soft cutoff switching element 40 are removed. Then, the source of the discharge switching element 30 is selectively selected from either the emitter of the switching element S ¥ # or a part having a higher potential than the emitter (for example, a power source having an output potential higher than the emitter potential). Are connected by an energizing operation type switching element (for example, MOSFET). Then, the soft shut-off means has a configuration in which the discharge rate of the gate charge is lowered by connecting the source of the discharge switching element 30 and the portion having the high potential by the energization operation of the switching element during the soft shut-off process. It may be used.

  The clamp circuit that limits the gate voltage Vge with the clamp voltage Vclamp is not limited to that illustrated in FIG. For example, a Zener diode with the second terminal T2 side as a cathode may be provided between the second terminal T2 and the clamping switching element 32, and a comparator may be used instead of the operational amplifier 34. Note that the clamp circuit is not essential.

  -"Charging means" is not limited to charging the gate by constant current control. For example, in FIG. 2, the constant current power supply 24 may be removed, the constant voltage power supply 22 may be connected to the first terminal T1, and the gate may be charged by constant voltage control.

  The “switching element” is not limited to the IGBT but may be a MOSFET, for example.

  24 ... constant current power source, 26 ... switching element for charging, S ¥ # ... switching element.

Claims (4)

Charging means (24, 26) for charging the opening / closing control terminal of the switching element in order to switch the switching element (S ¥ #) to the ON state;
If the voltage at the switching control terminal exceeds the determination voltage within the overcurrent detection period from the first timing to the second timing, it is determined that an overcurrent flows between the pair of main terminals of the switching element. Overcurrent determination means;
With
The determination voltage is a voltage higher than a mirror voltage of the switching element, and is set to a voltage equal to or lower than an upper limit voltage of the switching control terminal,
The first timing is set to a timing before the timing when the voltage of the switching control terminal reaches the determination voltage when it is assumed that an overcurrent flows between the pair of main terminals.
The second timing is a timing at which the voltage at the switching control terminal reaches the determination voltage when it is assumed that an overcurrent does not flow between the pair of main terminals from a timing later than the first timing. Set in the period up to the earlier timing ,
The current connected to the open / close control terminal so that the charge moves toward the open / close control terminal in the current flow path connected to the open / close control terminal under a situation where the current flowing between the pair of main terminals rises. A switching element drive circuit , wherein a flow path and a main current flow path connected to at least one of the pair of main terminals are magnetically coupled . Current detection means (St, 42) for detecting current flowing between the pair of main terminals;
In the overcurrent detection period, the overcurrent determination means, in addition to the voltage of the switching control terminal exceeds the determination voltage, in addition, when the current detected by the current detection means exceeds a threshold current, 2. The switching element drive circuit according to claim 1, wherein it is determined that an overcurrent flows between the pair of main terminals.   The overcurrent determination means determines that overcurrent flows between the pair of main terminals only when the voltage of the switching control terminal exceeds the determination voltage within the overcurrent detection period. The switching element drive circuit according to claim 1. When it is determined by the overcurrent determination means that an overcurrent is flowing, a discharge rate lower than a charge discharge rate of the switching control terminal when the switching element is switched to an off state when the overcurrent does not flow The switching element according to any one of claims 1 to 3 , further comprising a soft shut-off means (38, 40) for forcibly switching the switching element to an OFF state by discharging electric charge at Drive circuit.

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